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e3c18babe9
Including the following patches: commit 0f7723bb09440ae69743fed38cf558a838aa9bdf Author: Bryan Huntsman <bryanh@codeaurora.org> Date: Thu Oct 6 23:13:56 2011 -0700 Revert "spi_qsd: GPIO configuration changes for SPI chip-select line" This reverts commit 7eaa08b75995289a91c7dd1f3616f79227f5f923. Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org> commit 7eaa08b75995289a91c7dd1f3616f79227f5f923 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Wed Sep 28 16:26:39 2011 -0600 spi_qsd: GPIO configuration changes for SPI chip-select line The chip-select GPIO's pertaining to each slave remains in suspended configuration until the first transfer is intiated by the slave. Change-Id: I3aa8555289be7ce457b91a969cf03909be0965d7 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit e47df9f9b932968152ab2908153e60adab4402d7 Author: Jordan Crouse <jcrouse@codeaurora.org> Date: Mon Sep 19 11:21:16 2011 -0600 spi_qsd: Fix possible uninitialized variable Change-Id: Ic0dedbad184046e9835cde015ad5d592f33e82a6 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> commit 4ae02c76b98f2b96bfb8c4fa02f40cfda2f16f97 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Tue Sep 20 17:28:50 2011 -0600 spi_qsd: Fix Klocwork errors in SPI driver Change-Id: I1fe6632e68ea625966aced37a1b140b30534e101 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit 52e065ba3d86977b59937693ac7e85836cf4eca8 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Thu Sep 1 12:12:58 2011 -0600 spi_qsd: Fix for SPI Operational State Invalid error This error is reproted randomly when the SPI core is put into RUN state and occurs when the ACPU clock is low. When the timer expires, we check again to ensure that the STATE_VALID bit is set before returning. Change-Id: Ic8912534f4924efd999b8aa1d75a9fd19749e870 CRs-fixed: 304672 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit a9a8816913e5466e06b443c42cbf8ae866b95fd1 Author: Jeff Ohlstein <johlstei@codeaurora.org> Date: Fri Sep 2 13:55:16 2011 -0700 msm: dma: remove crci conflict checking The crci conflict checking code was designed for a system where a crci's mux could be changed at runtime. In reality, our chips configure these statically, so it is not necessary. Change-Id: I4d5f32cd8728d3c78fca8f64aed0e02b57b6afba Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> commit 36c6f1bb48af3e65db281cc7ccb913a8e81a598e Author: Matt Wagantall <mattw@codeaurora.org> Date: Wed Aug 17 15:44:58 2011 -0700 msm: clock: Rename all I2C/SPI clocks to 'core_clk' or "iface_clk" Drivers should now use their device names to distinguish between clocks of the same type rather than the clock name. Change-Id: Iab12caf4eab163773d68f1b2adc1bb4c72c69e83 Signed-off-by: Matt Wagantall <mattw@codeaurora.org> commit 55e656e68cac78eaa367341df2e693a483a53f84 Author: Stepan Moskovchenko <stepanm@codeaurora.org> Date: Mon Jun 6 14:34:38 2011 -0700 drivers: barriers: Replace dsb() with mb() Replace explicit dsb() calls with mb(). Now that the generic ARM implementation defines mb() to mean (at least) dsb(), it is appropriate to switch back to the generic kernel version of the barriers. This is also needed for correctness on certain targets (such as 7x27) where dsb() is insufficient and other operations (such as outer cache sync or writing to strongly-ordered memory) are required to ensure proper I/O operations ordering. In some cases, remove explicit calls to outer_sync following a barrier since the barrier will now have an explicit outer_sync call. Change-Id: I2c53b8534af9c3cbac4d4d77b322f897a39e7758 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> commit 17194a32164b868f80ce84e313f9148d1dc77e7b Author: Harini Jayaraman <harinij@codeaurora.org> Date: Fri Jun 3 18:10:09 2011 -0600 spi_qsd: GPIO configuration changes On suspend, the SPI related GPIO's enter a low power configuration and on resume they move to an active configuration. This helps conserving power during power collapse. Change-Id: I0911867e10fadcfc6950f6dddf74226bd6321c16 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit 1777d88688511cd59bad7674c6a2246e0c93142b Author: Harini Jayaraman <harinij@codeaurora.org> Date: Wed Jun 1 16:54:07 2011 -0600 spi_qsd: Remove restriction on SPI clock speed. When multiple slaves are connected to the SPI controller, the driver does not allow the clock to go from lower speed to a higher speed. This restriction is not required since there can only be one slave listening at a time. Also, there are no hardware limitations in doing so. Change-Id: I4ecabfb3a1515416f050c18678cf0987dcde9d1e CRs-fixed: 290127 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit 4b7c7bfc546cb02141da9d034421aefe5635f857 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Tue Jun 7 14:18:42 2011 -0600 spi_qsd: Add null pointer check before dereferencing During probe, there is no cur_msg to set the status. Change-Id: I82e00b9d74d45c36b70078b171db1bb150d1bfac Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit bf514c766fcc2bdee680f80a2ea16c7fead0be96 Author: Stepan Moskovchenko <stepanm@codeaurora.org> Date: Mon May 16 13:37:11 2011 -0700 msm: spi: Fix access to unclocked registers Don't program the GSBI configuration until the clocks have been turned on. Change-Id: Idee5f5dffcb5ed0f7de18f1e508ee8c76b618894 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> commit d9c248213f4cd025f3d3586f0de81e4bc44a5a54 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Mon May 16 16:43:08 2011 -0600 spi_qsd: Fix for SPI input overrun error This error occurs due to a bug in the controller. This bogus error is reported when a transition from run to reset state occurs and if the input FIFO has an odd number of entries. Change-Id: I555864d4855ac6d416997da69d8bc6aee7a82178 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit e99ceb5b3da7bec51be853809c25df8e32b2c1e6 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Thu Apr 14 18:36:34 2011 -0600 spi_qsd: Multi-transfer handling When there are mulitple SPI transfers in a message, we default to using FIFO mode for all the transfers. As special case, we handle a WR-WR or WR-RD transfer where we choose between FIFO mode and DM mode based on the total length of the transaction. Change-Id: I6fbc1a06a22f9782db5b97c9b87cc53392a8c2fa CRs-fixed: 276666 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit 8f3d3aaa51603a929027bc820fe2d3515e959779 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Tue Apr 19 14:19:29 2011 -0600 spi_qsd: Ensure IO operation ordering Adding memory barriers to ensure that the writes and reads to the SPI and QUP registers happen in the correct order. Change-Id: I86d8f63b0e9547a2339ee4ab5c713cf8864fef04 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit 36b3fae5f54230cd1e4ca072d1f55cb2f79d8945 Author: Laura Abbott <lauraa@codeaurora.org> Date: Thu Oct 14 12:48:16 2010 -0700 spi_qsd: Fix section mismatch The function msm_spi_probe is referenced outside of the __init section. This fixes the problem by calling platform_driver_probe instead of platform_driver_register since this device is not hotplugable. Change-Id: I3a563c6fc562ada959317b54ff60a38f9ce517d8 Signed-off-by: Laura Abbott <lauraa@codeaurora.org> commit dc2e36eecefb6628031afeff28afd9d97f2f3f6f Author: Harini Jayaraman <harinij@codeaurora.org> Date: Wed Sep 29 16:58:20 2010 -0600 spi_qsd: Changes to support DM mode. The dma_config function may not always be present. This change makes sure the driver gets DM resources irrespective of the dma_config function. Change-Id: I25a2497d20e973f22b76f2b5d6f68c86bd4d5f1d Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit a39bd4a398674c320925540eec91d94d2b7d53f3 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Thu Aug 19 17:48:01 2010 -0600 spi_qsd: Modify timeout mechanism to check SPI state valid bit. In order to allow sufficient time for the SPI state transition to occur, calculate the timeout based on the SPI clock speed. Change-Id: I3d6955b2a64a8bf8980590e352fbd564250210fb CRs-fixed: 250998 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit b5887b644ba9545672d637985713c7e0e2e5bb50 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Tue Aug 3 16:57:33 2010 -0600 spi_qsd: Use FIFO mode when DM mode configuration fails. When the Data Mover configuration fails, the driver uses FIFO mode. Change-Id: Iaf83e50fe725654c58260c5cd1150cdeb56f51c8 CRs-fixed: 249238 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit ced8ad320d480006643a3aa3474f5c0d77457454 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Mon Jun 28 16:01:33 2010 -0600 spi_qsd: Use SW timeout instead of SPI_TIME_OUT register. Since the software timeout is already present in the driver, the hardware SPI_TIME_OUT register is being removed.It is just redundant and used only for debugging purposes. Change-Id: I829cb944444fc3e5053bc810adffe2b87f511b63 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit 35e9155f59317e8ef63b8ce5190f26f5cae6a8ee Author: Harini Jayaraman <harinij@codeaurora.org> Date: Fri Jun 25 16:48:25 2010 -0600 spi_qsd: Disable irqs in the probe function. The irqs are disabled at all times in the probe function irrespective of the use of remote lock. Change-Id: I0997d07b93c97a12bca6d80a9bba59682b1bec3e Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit e6af92d74a35ba267125bc61c2c6c18034c03af3 Author: Harini Jayaraman <harinij@codeaurora.org> Date: Tue Jun 22 12:20:46 2010 -0600 spi_qsd: Disable clocks and irqs when SPI bus is not in use. The SPI clocks and irqs are enabled per workqueue and correspondingly disabled once the workqueue is completed. Change-Id: Ib22b7e3b946eb4c829940e43327caaf5aff7721b CRs-fixed: 242866 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org> commit b25e4220efdacc231cb150fc263af1e3f525b165 Author: Lena Salman <esalman@qualcomm.com> Date: Tue Jun 8 15:25:47 2010 +0300 spi_qsd: Add usage of MX_WRITE_COUNT register Use MX_WRITE_COUNT register to reduce the amount of TX interrupts in FIFO mode for transfers smaller than FIFO size. Change-Id: I7208fdc85b626a31a8b781ee5c56f73beee6c427 Signed-off-by: Lena Salman <esalman@qualcomm.com> commit 7ed56f3441c5ebe7fd8107fb8468207a88bc743f Author: Lena Salman <esalman@qualcomm.com> Date: Wed Jun 9 16:14:44 2010 +0300 spi_qsd: Minor changes to support Data Mover mode on QUPe core Minor changes to support Data Mover made on QUPe core. Change-Id: I54663115a43f7fd9b52a2ddee796b5499d5f239a Signed-off-by: Lena Salman <esalman@qualcomm.com> commit a85fd0ab6484eb2ef404c062adffce1ee22337f1 Author: Lena Salman <esalman@qualcomm.com> Date: Thu Jun 3 13:57:02 2010 +0300 spi_qsd: Add support for QUPe controller QUPe controller is a new version of Qualcomm SPI controller. The controller also supports other peripheral protocols, however its SPI functionality is very similar to previous SPI core, supported by spi_qsd. Therefore the same driver is being utilized with some register address modification and minor flow change. Change-Id: Ic091ef2c2ed699b43f786c278b613e69a7e9039b Signed-off-by: Lena Salman <esalman@qualcomm.com> commit ce270f6f9198cf40ee5638b35e595da81116241e Author: Jeff Ohlstein <johlstei@quicinc.com> Date: Thu Apr 29 13:40:53 2010 -0700 drivers: spi: Support ADM3 in spi_qsd driver Change-Id: I6dfa38a4c33a8e4619d56ce30787e1aeafc8356d Signed-off-by: Jeff Ohlstein <johlstei@quicinc.com> commit 47346fa611773ef92d12d9145ea33a7f2c79052f Author: Lena Salman <esalman@qualcomm.com> Date: Wed Apr 28 11:33:15 2010 +0300 spi_qsd: Add disable/enable of pclk to suspend/resume functions Add disable/enable of pclk to suspend/resume functions to improve power performance. Change-Id: I871e5ac90a998f2942778bb1e8c2c9d583a9ae00 CRs-fixed: 235046 Signed-off-by: Lena Salman <esalman@qualcomm.com> commit a96eba98fbbd21ac657f5d551466909352766ead Author: Lena Salman <esalman@qualcomm.com> Date: Sun Apr 11 10:40:37 2010 +0300 spi_qsd: Making irq code implicit for the core mode in use Make code clear regarding what mode is in use in the irq. Signed-off-by: Lena Salman <esalman@qualcomm.com> commit 6a02d85f8f48cf6f86cddc38c9fce9c1179208b4 Author: Lena Salman <esalman@qualcomm.com> Date: Tue Apr 13 21:16:45 2010 +0300 spi_qsd: Separate tx/rx/error statistics between contexts To improve SMP safety, separate the tx/error statistics between contexts. This protects the statistics from accidentally being access from another context at the same time. Change-Id: Ibc52406e7b06a4bb5142f8a09a2f35442cb9df8a Signed-off-by: Lena Salman <esalman@qualcomm.com> commit 31f301c171aab8e42f8b6abe9b7866412cb546a8 Author: Lena Salman <esalman@qualcomm.com> Date: Tue Mar 23 14:51:00 2010 +0200 spi_qsd: Add better handling for pending transfers during suspend To improve SMP safety, add better handling in suspend function to wait for graceful closure of pending transfers. This graceful closure waits for all the pending transfers to finish or timeout, while not allowing new ones to queue up. This allows correct handling of all the resources involved in a transfer before suspend. Signed-off-by: Lena Salman <esalman@qualcomm.com> commit 8fbf6e4c5371520b5f9de2001e2ebd15773e918b Author: Lena Salman <esalman@qualcomm.com> Date: Thu Mar 25 10:44:10 2010 +0200 spi_qsd: Add mutex to get exclusive access to controller registers To improve SMP safety, add mutex to get exclusive access to controller registers. Signed-off-by: Lena Salman <esalman@qualcomm.com> commit 9405adda67d8c6a856243e599f09d806b4bc6de5 Author: Kenneth Heitke <kheitke@quicinc.com> Date: Thu Apr 15 16:33:16 2010 -0600 spi_qsd: Move global input_fifo_size to device context. Fix reference to device data input_fifo_size which is missing from the previous patch. Change-Id: Ia469896edd0fd90d7ded2b8ec44f9075474b3ec8 Signed-off-by: Kenneth Heitke <kheitke@quicinc.com> commit 6031094ca6a940a47437bc6a092e813b4bc41d2a Author: Lena Salman <esalman@qualcomm.com> Date: Sun Apr 11 10:34:48 2010 +0300 spi_qsd: Move global input_fifo_size to device context. To improve SMP safety move global variable input_fifo_size to device context. Signed-off-by: Lena Salman <esalman@qualcomm.com> commit 97f585033413b1f8ae210bbffd617a4af3462982 Author: Lena Salman <esalman@qualcomm.com> Date: Wed Apr 14 18:35:54 2010 +0300 spi_qsd: Initial contribution of the MSM SPI driver This adds MSM SPI controller driver. The driver is SPI master, and allows slave connections. Current version of the driver supports FIFO and DM modes chosen upon the message size. The driver also supports loopback mode which can be used for testing purposes. This is a squashed version of all the MSM SPI driver changes on the QuIC MSM 2.6.29 kernel which can be found at www.codeaurora.org. It also contains all relevant adaptations to SPI core changes in 2.6.32 kernel. https://www.codeaurora.org/gitweb/quic/la/?p=kernel/msm.git;a=blob;f=drivers/spi/spi_qsd.c;h=1c8e3ec727b29040648ef9a4949396f7109528ae;hb=refs/heads/android-msm-2.6.29b Change-Id: Ibc1e71deb662af87deed77f10dcc8a3a46a8f012 Signed-off-by: Lena Salman <esalman@qualcomm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
79 lines
3.2 KiB
Makefile
79 lines
3.2 KiB
Makefile
#
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# Makefile for kernel SPI drivers.
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#
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ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
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# small core, mostly translating board-specific
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# config declarations into driver model code
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obj-$(CONFIG_SPI_MASTER) += spi.o
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obj-$(CONFIG_SPI_SPIDEV) += spidev.o
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# SPI master controller drivers (bus)
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obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
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obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
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obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
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obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
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obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
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obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
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obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
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obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
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obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
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obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
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obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
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obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
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obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
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obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
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spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
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obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
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obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
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obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
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obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
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obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
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obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
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obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
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obj-$(CONFIG_SPI_IMX) += spi-imx.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
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obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
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obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
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obj-$(CONFIG_SPI_MXS) += spi-mxs.o
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obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
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obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
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obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
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obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
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obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
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obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
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obj-$(CONFIG_SPI_ORION) += spi-orion.o
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obj-$(CONFIG_SPI_PL022) += spi-pl022.o
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obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
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spi-pxa2xx-platform-objs := spi-pxa2xx.o
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spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o
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spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
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obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
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obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
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obj-$(CONFIG_SPI_QSD) += spi_qsd.o
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obj-$(CONFIG_SPI_QUP) += spi_qsd.o
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obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
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obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
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spi-s3c24xx-hw-y := spi-s3c24xx.o
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spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
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obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
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obj-$(CONFIG_SPI_SC18IS602) += spi-sc18is602.o
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obj-$(CONFIG_SPI_SH) += spi-sh.o
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obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
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obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
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obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
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obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
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obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o
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obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
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obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
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obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
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obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
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obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
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