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clk: qcom: 8939: Add support for oxili_timer_clk

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The gfx driver needs to control the oxili_timer_clk. Add
the support in this change.

Change-Id: I9582c7370f6713828bb010ffb996573f25528657
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
This commit is contained in:
Tianyi Gou 2015-01-30 17:55:05 -08:00
parent 0f7d8a5330
commit 05a1fc9fed
2 changed files with 17 additions and 1 deletions
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15
drivers/clk/qcom/clock-gcc-8936.c
View File

@ -268,6 +268,7 @@ static void __iomem *virt_dbgbase;
#define OXILI_GFX3D_CBCR 0x59020
#define OXILI_GMEM_CBCR 0x59024
#define OXILI_AHB_CBCR 0x59028
#define OXILI_TIMER_CBCR 0x59040
#define CAMSS_TOP_AHB_CMD_RCGR 0x5A000
#define BIMC_GFX_CBCR 0x31024
#define BIMC_GPU_CBCR 0x31040
@ -2531,6 +2532,18 @@ static struct branch_clk gcc_oxili_gfx3d_clk = {
},
};
static struct branch_clk gcc_oxili_timer_clk = {
.cbcr_reg = OXILI_TIMER_CBCR,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_oxili_timer_clk",
.parent = &gcc_xo.c,
.ops = &clk_ops_branch,
CLK_INIT(gcc_oxili_timer_clk.c),
},
};
static struct branch_clk gcc_pdm2_clk = {
.cbcr_reg = PDM2_CBCR,
.has_sibling = 0,
@ -3051,6 +3064,7 @@ static struct mux_clk gcc_debug_mux = {
{&gcc_crypto_clk.c, 0x0138},
{&gcc_crypto_axi_clk.c, 0x0139},
{&gcc_crypto_ahb_clk.c, 0x013a},
{&gcc_oxili_timer_clk.c, 0x01e9},
{&gcc_oxili_gfx3d_clk.c, 0x01ea},
{&gcc_oxili_ahb_clk.c, 0x01eb},
{&gcc_oxili_gmem_clk.c, 0x01f0},
@ -3236,6 +3250,7 @@ static struct clk_lookup msm_clocks_lookup[] = {
CLK_LIST(gcc_mss_cfg_ahb_clk),
CLK_LIST(gcc_mss_q6_bimc_axi_clk),
CLK_LIST(gcc_oxili_ahb_clk),
CLK_LIST(gcc_oxili_timer_clk),
CLK_LIST(gcc_oxili_gfx3d_clk),
CLK_LIST(gcc_pdm2_clk),
CLK_LIST(gcc_pdm_ahb_clk),

3
include/dt-bindings/clock/msm-clocks-8936.h
View File

@ -1,4 +1,4 @@
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -169,6 +169,7 @@
#define clk_gcc_mdss_vsync_clk 0x32a09f1f
#define clk_gcc_mss_cfg_ahb_clk 0x111cde81
#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62
#define clk_gcc_oxili_timer_clk 0x1180db06
#define clk_gcc_oxili_ahb_clk 0xd15c8a00
#define clk_gcc_oxili_gfx3d_clk 0x49a51fd9
#define clk_gcc_pdm2_clk 0x99d55711