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https://github.com/joel16/android_kernel_sony_msm8994_rework.git
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atmel_spi: clean up baud rate divisor calculation
Make the baud rate divisor calculation code a bit more readable and add a few comments. Also fix wrong debug information being displayed when !new_1 and max_speed_hz == 0. [david-b@pacbell.net: fix it] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: "Janesh Ramakrishnan" <jramakrishnan@neuropace.com> Acked-by David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -497,7 +497,7 @@ static int atmel_spi_setup(struct spi_device *spi)
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struct atmel_spi *as;
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u32 scbr, csr;
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unsigned int bits = spi->bits_per_word;
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unsigned long bus_hz, sck_hz;
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unsigned long bus_hz;
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unsigned int npcs_pin;
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int ret;
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@ -536,14 +536,25 @@ static int atmel_spi_setup(struct spi_device *spi)
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return -EINVAL;
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}
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/* speed zero convention is used by some upper layers */
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/*
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* Pre-new_1 chips start out at half the peripheral
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* bus speed.
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*/
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bus_hz = clk_get_rate(as->clk);
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if (!as->new_1)
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bus_hz /= 2;
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if (spi->max_speed_hz) {
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/* assume div32/fdiv/mbz == 0 */
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if (!as->new_1)
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bus_hz /= 2;
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scbr = ((bus_hz + spi->max_speed_hz - 1)
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/ spi->max_speed_hz);
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/*
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* Calculate the lowest divider that satisfies the
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* constraint, assuming div32/fdiv/mbz == 0.
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*/
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scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
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/*
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* If the resulting divider doesn't fit into the
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* register bitfield, we can't satisfy the constraint.
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*/
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if (scbr >= (1 << SPI_SCBR_SIZE)) {
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dev_dbg(&spi->dev,
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"setup: %d Hz too slow, scbr %u; min %ld Hz\n",
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@ -551,8 +562,8 @@ static int atmel_spi_setup(struct spi_device *spi)
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return -EINVAL;
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}
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} else
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/* speed zero means "as slow as possible" */
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scbr = 0xff;
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sck_hz = bus_hz / scbr;
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csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
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if (spi->mode & SPI_CPOL)
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@ -589,7 +600,7 @@ static int atmel_spi_setup(struct spi_device *spi)
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dev_dbg(&spi->dev,
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"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
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sck_hz, bits, spi->mode, spi->chip_select, csr);
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bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
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spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
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