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https://github.com/joel16/android_kernel_sony_msm8994_rework.git
synced 2024-11-27 05:40:41 +00:00
Merge "ARM: dts: msm: vp-ipa simulation dts"
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76b175f95d
@ -7,7 +7,7 @@ optionally have a register which encodes the maximum rate supported by hw.
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Required properties:
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- compatible: "qcom,clock-a7-8226", "qcom,clock-a7-9630",
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"qcom,clock-a53-8916", "qcom,clock-a7-9640"
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"qcom,clock-a53-8916", "qcom,clock-a7-9640", "qcom,clock-a7-vpipa"
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- reg: pairs of physical address and region size
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- reg-names: "rcg-base" is expected
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- clock-names: list of names of clock inputs
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@ -71,6 +71,9 @@ SoCs:
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- MDM9640
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compatible = "qcom,mdm9640"
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- VPIPA
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compatible = "qcom,msmvpipa"
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- FSM9010
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compatible = "qcom,fsm9010"
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@ -198,3 +201,4 @@ compatible = "qcom,fsm9010-cdp"
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compatible = "qcom,fsm9010-mtp"
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compatible = "qcom,fsm9900-cdp"
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compatible = "qcom,fsm9900-mtp"
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compatible = "qcom,msmvpipa-sim"
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@ -13,6 +13,7 @@ semantics.
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"qcom,msm-tlmm-8226"
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"qcom,msm-tlmm-8974"
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"qcom,msm-tlmm-mdm9640"
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"qcom,msm-tlmm-vpipa"
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- reg: Base address of the pin controller hardware module and length of
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the address space it occupies.
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@ -180,6 +180,7 @@ dtb-$(CONFIG_ARCH_MDM9640) += mdm9640-sim.dtb \
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mdm9640-emmc-cdp.dtb \
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mdm9640-nand-cdp.dtb \
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mdm9640-mtp.dtb
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dtb-$(CONFIG_ARCH_MSMVPIPA) += msmvpipa-sim.dtb
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dtb-$(CONFIG_ARCH_MDMFERRUM) += mdmferrum-sim.dtb \
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mdmferrum-rumi.dtb \
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mdmferrum-cdp.dtb \
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45
arch/arm/boot/dts/qcom/msmvpipa-pinctrl.dtsi
Normal file
45
arch/arm/boot/dts/qcom/msmvpipa-pinctrl.dtsi
Normal file
@ -0,0 +1,45 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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tlmm_pinmux: pinctrl@1000000 {
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compatible = "qcom,msm-tlmm-vpipa", "qcom,msm-tlmm-8916";
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reg = <0x1000000 0x300000>;
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interrupts = <0 208 0>;
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/* General purpose pins */
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gp: gp {
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qcom,num-pins = <100>;
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#qcom,pin-cells = <1>;
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msm_gpio: msm_gpio {
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compatible = "qcom,msm-tlmm-gp";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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num_irqs = <100>;
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};
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};
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pmx-uart2console {
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qcom,pins = <&gp 4>, <&gp 5>;
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qcom,num-grp-pins = <2>;
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qcom,pin-func = <2>;
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label = "uart2-console";
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uart2_console_active: uart2-console {
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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};
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206
arch/arm/boot/dts/qcom/msmvpipa-regulator.dtsi
Normal file
206
arch/arm/boot/dts/qcom/msmvpipa-regulator.dtsi
Normal file
@ -0,0 +1,206 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Stub Regulators */
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&soc {
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pmd9635_s1: regulator-s1 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_s1";
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qcom,hpm-min-load = <100000>;
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1100000>;
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};
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pmd9635_s2: regulator-s2 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_s2";
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qcom,hpm-min-load = <100000>;
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regulator-min-microvolt = <1250000>;
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regulator-max-microvolt = <1250000>;
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};
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pmd9635_s3: regulator-s3 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_s3";
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qcom,hpm-min-load = <100000>;
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regulator-min-microvolt = <1025000>;
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regulator-max-microvolt = <1025000>;
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};
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pmd9635_s4: regulator-s4 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_s4";
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qcom,hpm-min-load = <100000>;
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regulator-min-microvolt = <1850000>;
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regulator-max-microvolt = <1850000>;
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};
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/* PMD9635 S5 = VDD_CX supply */
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pmd9635_s5_corner: regulator-s5-corner {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_s5_corner";
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qcom,hpm-min-load = <100000>;
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regulator-min-microvolt = <1>;
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regulator-max-microvolt = <7>;
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};
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pmd9635_s5_corner_ao: regulator-s5-corner-ao {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_s5_corner_ao";
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qcom,hpm-min-load = <100000>;
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regulator-min-microvolt = <1>;
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regulator-max-microvolt = <7>;
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};
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pmd9635_s5_floor_corner: regulator-s5-floor-corner {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_s5_floor_corner";
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qcom,hpm-min-load = <100000>;
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regulator-min-microvolt = <1>;
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regulator-max-microvolt = <7>;
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};
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pmd9635_l1: regulator-l1 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l1";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1225000>;
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regulator-max-microvolt = <1225000>;
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};
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pmd9635_l2: regulator-l2 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l2";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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pmd9635_l3: regulator-l3 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l3";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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};
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pmd9635_l4: regulator-l4 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l4";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <950000>;
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};
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pmd9635_l5: regulator-l5 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l5";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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pmd9635_l6: regulator-l6 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l6";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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pmd9635_l7: regulator-l7 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l7";
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qcom,hpm-min-load = <5000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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pmd9635_l8: regulator-l8 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l8";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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/* PMD9635 L9 = VDD_MX supply */
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pmd9635_l9_corner: regulator-l9-corner {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l9_corner";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1>;
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regulator-max-microvolt = <7>;
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};
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pmd9635_l10: regulator-l10 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l10";
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qcom,hpm-min-load = <5000>;
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regulator-min-microvolt = <3200000>;
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regulator-max-microvolt = <3200000>;
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};
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pmd9635_l11: regulator-l11 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l11";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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pmd9635_l12: regulatorl12 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l12";
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qcom,hpm-min-load = <5000>;
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <2700000>;
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};
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pmd9635_l13: regulator-l13 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l13";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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pmd9635_l14: regulator-l14 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l14";
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qcom,hpm-min-load = <5000>;
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <2700000>;
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};
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pmd9635_l15: regulator-l15 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l15";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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pmd9635_l16: regulator-l16 {
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compatible = "qcom,stub-regulator";
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regulator-name = "9635_l16";
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qcom,hpm-min-load = <10000>;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <950000>;
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};
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spi_eth_vreg: spi_eth_phy_vreg {
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compatible = "regulator-fixed";
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regulator-name = "ethernet_phy";
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regulator-always-on;
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};
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};
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32
arch/arm/boot/dts/qcom/msmvpipa-sim.dts
Normal file
32
arch/arm/boot/dts/qcom/msmvpipa-sim.dts
Normal file
@ -0,0 +1,32 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
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/dts-v1/;
|
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|
||||
#include "msmvpipa.dtsi"
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#include "msmvpipa-pinctrl.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. MDM VPIPA SIM";
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compatible = "qcom,msmvpipa-sim", "qcom,msmvpipa", "qcom,sim";
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qcom,board-id = <16 0>;
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};
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&blsp1_uart2 {
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status = "ok";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_console_active>;
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};
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|
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&ipa_hw {
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qcom,ipa-hw-mode = <1>; /* IPA hw type = Virtual */
|
||||
};
|
||||
201
arch/arm/boot/dts/qcom/msmvpipa.dtsi
Normal file
201
arch/arm/boot/dts/qcom/msmvpipa.dtsi
Normal file
@ -0,0 +1,201 @@
|
||||
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/clock/msm-clocks-vpipa.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. MSM VPIPA";
|
||||
compatible = "qcom,msmvpipa";
|
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qcom,msm-id = <234 0x10000>, <235 0x10000>, <236 0x10000>,
|
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<237 0x10000>, <238 0x10000>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
soc: soc { };
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
intc: interrupt-controller@b000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0b000000 0x1000>,
|
||||
<0x0b002000 0x1000>;
|
||||
};
|
||||
|
||||
qcom,msm-imem@8600000 {
|
||||
compatible = "qcom,msm-imem";
|
||||
reg = <0x8600000 0x1000>; /* Address and size of IMEM */
|
||||
ranges = <0x0 0x8600000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mem_dump_table@10 {
|
||||
compatible = "qcom,msm-imem-mem_dump_table";
|
||||
reg = <0x10 8>;
|
||||
};
|
||||
|
||||
restart_reason@65c {
|
||||
compatible = "qcom,msm-imem-restart_reason";
|
||||
reg = <0x65c 4>;
|
||||
};
|
||||
|
||||
boot_stats@6b0 {
|
||||
compatible = "qcom,msm-imem-boot_stats";
|
||||
reg = <0x6b0 32>;
|
||||
};
|
||||
|
||||
pil@94c {
|
||||
compatible = "qcom,msm-imem-pil";
|
||||
reg = <0x94c 200>;
|
||||
};
|
||||
};
|
||||
|
||||
timer@b020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0xb020000 0x1000>;
|
||||
clock-frequency = <19200000>;
|
||||
|
||||
frame@b021000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <0 7 0x4>,
|
||||
<0 6 0x4>;
|
||||
reg = <0xb021000 0x1000>,
|
||||
<0xb022000 0x1000>;
|
||||
};
|
||||
|
||||
frame@b023000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <0 8 0x4>;
|
||||
reg = <0xb023000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b024000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <0 9 0x4>;
|
||||
reg = <0xb024000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b025000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <0 10 0x4>;
|
||||
reg = <0xb025000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b026000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <0 11 0x4>;
|
||||
reg = <0xb026000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b027000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <0 12 0x4>;
|
||||
reg = <0xb027000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b028000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <0 13 0x4>;
|
||||
reg = <0xb028000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b029000 {
|
||||
frame-number = <7>;
|
||||
interrupts = <0 14 0x4>;
|
||||
reg = <0xb029000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clock_gcc: qcom,gcc@1800000 {
|
||||
compatible = "qcom,dummycc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_rpm: qcom,rpmcc@1800000 {
|
||||
compatible = "qcom,dummycc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
blsp1_uart1: serial@78af000 {
|
||||
compatible = "qcom,msm-lsuart-v14";
|
||||
reg = <0x78af000 0x200>;
|
||||
interrupts = <0 107 0>;
|
||||
clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
|
||||
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
|
||||
clock-names = "core_clk", "iface_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@78b0000 {
|
||||
compatible = "qcom,msm-lsuart-v14";
|
||||
reg = <0x78b0000 0x200>;
|
||||
interrupts = <0 108 0>;
|
||||
clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
|
||||
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
|
||||
clock-names = "core_clk", "iface_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qcom,sps {
|
||||
compatible = "qcom,msm_sps_4k";
|
||||
qcom,device-type = <3>;
|
||||
qcom,pipe-attr-ee;
|
||||
};
|
||||
|
||||
ipa_hw: qcom,ipa@07900000 {
|
||||
compatible = "qcom,ipa";
|
||||
reg = <0x07900000 0x4EFFC>,
|
||||
<0x07904000 0x26934>;
|
||||
reg-names = "ipa-base", "bam-base";
|
||||
interrupts = <0 31 0>,
|
||||
<0 34 0>;
|
||||
interrupt-names = "ipa-irq", "bam-irq";
|
||||
qcom,ipa-hw-ver = <5>; /* IPA core version = IPAv2.0 */
|
||||
qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
|
||||
qcom,ee = <0>;
|
||||
qcom,use-ipa-tethering-bridge;
|
||||
clock-names = "core_clk";
|
||||
clocks = <&clock_rpm clk_ipa_a_clk>;
|
||||
};
|
||||
|
||||
qcom,clock-a7@0b011050 {
|
||||
compatible = "qcom,clock-a7-vpipa";
|
||||
reg = <0x0b011050 0x8>;
|
||||
reg-names = "rcg-base";
|
||||
|
||||
clock-names = "clk-1", "clk-5";
|
||||
qcom,speed0-bin-v0 =
|
||||
< 0 0>,
|
||||
< 400000000 4>,
|
||||
< 793000000 5>,
|
||||
<1160000000 7>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
#include "msmvpipa-regulator.dtsi"
|
||||
106
include/dt-bindings/clock/msm-clocks-vpipa.h
Normal file
106
include/dt-bindings/clock/msm-clocks-vpipa.h
Normal file
@ -0,0 +1,106 @@
|
||||
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MSM_CLOCKS_VPIPA_H
|
||||
#define __MSM_CLOCKS_VPIPA_H
|
||||
|
||||
/* clock_rpm controlled clocks */
|
||||
#define clk_xo_clk_src 0x23f5649f
|
||||
#define clk_xo_a_clk_src 0x2fdd2c7c
|
||||
#define clk_bimc_clk 0x4b80bf00
|
||||
#define clk_bimc_a_clk 0x4b25668a
|
||||
#define clk_bimc_msmbus_clk 0xd212feea
|
||||
#define clk_bimc_msmbus_a_clk 0x71d1a499
|
||||
#define clk_pcnoc_clk 0xc1296d0f
|
||||
#define clk_pcnoc_a_clk 0x9bcffee4
|
||||
#define clk_pcnoc_msmbus_clk 0x2b53b688
|
||||
#define clk_pcnoc_msmbus_a_clk 0x9753a54f
|
||||
#define clk_snoc_clk 0x2c341aa0
|
||||
#define clk_snoc_a_clk 0x8fcef2af
|
||||
#define clk_snoc_msmbus_clk 0xe6900bb6
|
||||
#define clk_snoc_msmbus_a_clk 0x5d4683bd
|
||||
#define clk_ipa_clk 0xfa685cda
|
||||
#define clk_ipa_a_clk 0xeeec2919
|
||||
#define clk_qdss_clk 0x1492202a
|
||||
#define clk_qdss_a_clk 0xdd121669
|
||||
#define clk_qpic_clk 0x3ce6f7bb
|
||||
#define clk_qpic_a_clk 0xd70ccb7c
|
||||
|
||||
/* clock_gcc controlled clocks */
|
||||
#define clk_gpll0 0x1ebe3bc4
|
||||
#define clk_gpll0_ao 0xa1368304
|
||||
#define clk_gpll0_out_main 0xe9374de7
|
||||
#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800
|
||||
#define clk_gcc_imem_axi_clk 0x3e52e7d8
|
||||
#define clk_gcc_imem_cfg_ahb_clk 0x5d4f462e
|
||||
#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96
|
||||
#define clk_gcc_sdcc1_ahb_clk 0x691e0caa
|
||||
#define clk_sdcc1_apps_clk_src 0xd4975db2
|
||||
#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f
|
||||
#define clk_gcc_blsp1_sleep_clk 0x989f22f3
|
||||
#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0
|
||||
#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9
|
||||
#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa
|
||||
#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e
|
||||
#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90
|
||||
#define clk_gcc_blsp1_uart1_sim_clk 0x36377c55
|
||||
#define clk_blsp1_uart1_apps_clk_src 0xf8146114
|
||||
#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f
|
||||
#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220
|
||||
#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a
|
||||
#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79
|
||||
#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96
|
||||
#define clk_gcc_blsp1_uart2_sim_clk 0xdeaa39fe
|
||||
#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73
|
||||
#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880
|
||||
#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82
|
||||
#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f
|
||||
#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902
|
||||
#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7
|
||||
#define clk_gcc_blsp1_uart3_sim_clk 0xbaf22819
|
||||
#define clk_blsp1_uart3_apps_clk_src 0x600497f2
|
||||
#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f
|
||||
#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f
|
||||
#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb
|
||||
#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68
|
||||
#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0
|
||||
#define clk_gcc_blsp1_uart4_sim_clk 0x0fe63389
|
||||
#define clk_blsp1_uart4_apps_clk_src 0x56bff15c
|
||||
#define clk_gcc_pdm_ahb_clk 0x365664f6
|
||||
#define clk_gcc_pdm_xo4_clk 0x3d32f1d0
|
||||
#define clk_gcc_pdm2_clk 0x99d55711
|
||||
#define clk_pdm2_clk_src 0x31e494fd
|
||||
#define clk_pdm_clk_src 0x388230aa
|
||||
#define clk_pdm_xo4_clk_src 0x842fef1a
|
||||
#define clk_apss_ahb_clk_src 0x36f8495f
|
||||
#define clk_apss_ahb_postdiv_clk_src 0x72168d9f
|
||||
#define clk_usb3_phy_wrapper_gcc_usb3_pipe_clk 0x283a7497
|
||||
#define clk_gcc_usb30_master_clk 0xb3b4e2cb
|
||||
#define clk_gcc_usb30_sleep_clk 0xd0b65c92
|
||||
#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a
|
||||
#define clk_usb30_master_clk_src 0xc6262f89
|
||||
#define clk_usb30_mock_utmi_clk_src 0xa024a976
|
||||
#define clk_usb30_mock_utmi_postdiv_clk_src 0xce6ee796
|
||||
#define clk_gcc_usb_phy_cfg_ahb_clk 0xccb7e26f
|
||||
#define clk_gcc_usb3_pipe_clk 0x26f8a97a
|
||||
#define clk_gcc_usb3_aux_clk 0x555d16b2
|
||||
#define clk_usb3_pipe_clk_src 0x8b922db4
|
||||
#define clk_usb3_aux_clk_src 0xfde7ae09
|
||||
#define clk_gcc_pcie_cfg_ahb_clk 0xddc9a515
|
||||
#define clk_gcc_pcie_pipe_clk 0x8be62558
|
||||
#define clk_gcc_pcie_axi_clk 0xb833d9e3
|
||||
#define clk_gcc_pcie_sleep_clk 0x8b8bfc3b
|
||||
#define clk_gcc_pcie_axi_mstr_clk 0x54d09178
|
||||
#define clk_pcie_pipe_clk_src 0x3ef3897d
|
||||
#define clk_pcie_aux_clk_src 0xebc50566
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user