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https://github.com/joel16/android_kernel_sony_msm8994_rework.git
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ALSA: azt3328: fix previous breakage, improve suspend, cleanups
- fix my previous codec activity breakage (_non-warned_ variable assignment issue) - convert suspend/resume to 32bit I/O access (I/O is painful; to improve suspend/resume performance) - change DEBUG_PLAY_REC to DEBUG_CODEC for consistency - printk cleanup - some logging improvements - minor cleanup/improvements The variable assignment issue above was a conditional assignment to the call_function variable (this ended with the non-preinitialized variable not getting assigned in some cases, thus a dangling stack value, yet gcc 4.3.3 unbelievably did _NOT_ warn about it in this case!!), needed to change this into _always_ assigning the check result. Practical result of this bug was that when shutting down _either_ playback or capture, _both_ streams dropped dead :P Tested, working (plus resume) and checkpatch.pl:ed on 2.6.30-rc5, applies cleanly to 2.6.30 proper with my previous (committed) patches applied. Signed-off-by: Andreas Mohr <andi@lisas.de> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Andreas Mohr
Takashi Iwai
parent
dfbf951115
commit
78df617acf
@ -15,7 +15,7 @@
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* has very good support out of the box;
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* just to make sure that the right people hit this and get to know that,
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* despite the high level of Internet ignorance - as usual :-P -
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* about Linux support for this card)
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* about very good support for this card - on Linux!)
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*
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* GPL LICENSE
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* This program is free software; you can redistribute it and/or modify
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@ -222,22 +222,23 @@ MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
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#define DEBUG_MISC 0
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#define DEBUG_CALLS 0
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#define DEBUG_MIXER 0
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#define DEBUG_PLAY_REC 0
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#define DEBUG_CODEC 0
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#define DEBUG_IO 0
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#define DEBUG_TIMER 0
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#define DEBUG_GAME 0
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#define DEBUG_PM 0
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#define MIXER_TESTING 0
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#if DEBUG_MISC
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#define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args)
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#define snd_azf3328_dbgmisc(format, args...) printk(KERN_DEBUG format, ##args)
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#else
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#define snd_azf3328_dbgmisc(format, args...)
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#endif
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#if DEBUG_CALLS
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#define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
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#define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __func__)
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#define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __func__)
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#define snd_azf3328_dbgcallenter() printk(KERN_DEBUG "--> %s\n", __func__)
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#define snd_azf3328_dbgcallleave() printk(KERN_DEBUG "<-- %s\n", __func__)
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#else
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#define snd_azf3328_dbgcalls(format, args...)
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#define snd_azf3328_dbgcallenter()
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@ -250,10 +251,10 @@ MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
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#define snd_azf3328_dbgmixer(format, args...)
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#endif
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#if DEBUG_PLAY_REC
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#define snd_azf3328_dbgplay(format, args...) printk(KERN_DEBUG format, ##args)
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#if DEBUG_CODEC
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#define snd_azf3328_dbgcodec(format, args...) printk(KERN_DEBUG format, ##args)
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#else
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#define snd_azf3328_dbgplay(format, args...)
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#define snd_azf3328_dbgcodec(format, args...)
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#endif
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#if DEBUG_MISC
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@ -268,6 +269,12 @@ MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
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#define snd_azf3328_dbggame(format, args...)
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#endif
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#if DEBUG_PM
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#define snd_azf3328_dbgpm(format, args...) printk(KERN_DEBUG format, ##args)
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#else
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#define snd_azf3328_dbgpm(format, args...)
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#endif
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static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
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module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
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@ -334,12 +341,12 @@ struct snd_azf3328 {
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#ifdef CONFIG_PM
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/* register value containers for power management
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* Note: not always full I/O range preserved (just like Win driver!) */
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u16 saved_regs_ctrl[AZF_IO_SIZE_CTRL_PM / 2];
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u16 saved_regs_game [AZF_IO_SIZE_GAME_PM / 2];
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u16 saved_regs_mpu [AZF_IO_SIZE_MPU_PM / 2];
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u16 saved_regs_opl3 [AZF_IO_SIZE_OPL3_PM / 2];
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u16 saved_regs_mixer[AZF_IO_SIZE_MIXER_PM / 2];
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* Note: not always full I/O range preserved (similar to Win driver!) */
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u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4];
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u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4];
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u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4];
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u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4];
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u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4];
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#endif
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};
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@ -1029,19 +1036,20 @@ snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
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bool enable
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)
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{
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if (enable)
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chip->shadow_reg_ctrl_6AH &= ~bitmask;
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else
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bool do_mask = !enable;
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if (do_mask)
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chip->shadow_reg_ctrl_6AH |= bitmask;
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snd_azf3328_dbgplay("6AH_update mask 0x%04x enable %d: val 0x%04x\n",
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bitmask, enable, chip->shadow_reg_ctrl_6AH);
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else
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chip->shadow_reg_ctrl_6AH &= ~bitmask;
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snd_azf3328_dbgcodec("6AH_update mask 0x%04x do_mask %d: val 0x%04x\n",
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bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
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snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH);
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}
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static inline void
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snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
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{
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snd_azf3328_dbgplay("codec_enable %d\n", enable);
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snd_azf3328_dbgcodec("codec_enable %d\n", enable);
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/* no idea what exactly is being done here, but I strongly assume it's
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* PM related */
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snd_azf3328_ctrl_reg_6AH_update(
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@ -1058,7 +1066,7 @@ snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
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struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
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bool need_change = (codec->running != enable);
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snd_azf3328_dbgplay(
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snd_azf3328_dbgcodec(
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"codec_activity: %s codec, enable %d, need_change %d\n",
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codec->name, enable, need_change
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);
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@ -1081,11 +1089,11 @@ snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
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(which globally shuts down operation of codecs)
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only in case the other codecs are currently
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not active either! */
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if ((!chip->codecs[peer_codecs[codec_type].other1]
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.running)
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&& (!chip->codecs[peer_codecs[codec_type].other2]
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.running))
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call_function = 1;
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call_function =
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((!chip->codecs[peer_codecs[codec_type].other1]
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.running)
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&& (!chip->codecs[peer_codecs[codec_type].other2]
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.running));
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}
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if (call_function)
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snd_azf3328_ctrl_enable_codecs(chip, enable);
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@ -1097,8 +1105,8 @@ snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
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chip,
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codec_type
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);
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codec->running = enable;
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}
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codec->running = enable;
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}
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static void
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@ -1114,15 +1122,16 @@ snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip,
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if (!codec->running) {
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/* AZF3328 uses a two buffer pointer DMA transfer approach */
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unsigned long flags;
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unsigned long flags, addr_area2;
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/* width 32bit (prevent overflow): */
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u32 addr_area2, count_areas, lengths;
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u32 count_areas, lengths;
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count_areas = size/2;
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addr_area2 = addr+count_areas;
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count_areas--; /* max. index */
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snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas);
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snd_azf3328_dbgcodec("setdma: buffers %08lx[%u] / %08lx[%u]\n",
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addr, count_areas, addr_area2, count_areas);
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/* build combined I/O buffer length word */
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lengths = (count_areas << 16) | (count_areas);
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@ -1176,7 +1185,7 @@ snd_azf3328_codec_trigger(enum snd_azf3328_codec_type codec_type,
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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snd_azf3328_dbgplay("START %s\n", codec->name);
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snd_azf3328_dbgcodec("START %s\n", codec->name);
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if (is_playback_codec) {
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/* mute WaveOut (avoid clicking during setup) */
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@ -1243,10 +1252,10 @@ snd_azf3328_codec_trigger(enum snd_azf3328_codec_type codec_type,
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);
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}
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snd_azf3328_dbgplay("STARTED %s\n", codec->name);
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snd_azf3328_dbgcodec("STARTED %s\n", codec->name);
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break;
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case SNDRV_PCM_TRIGGER_RESUME:
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snd_azf3328_dbgplay("RESUME %s\n", codec->name);
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snd_azf3328_dbgcodec("RESUME %s\n", codec->name);
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/* resume codec if we were active */
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spin_lock(&chip->reg_lock);
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if (codec->running)
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@ -1258,7 +1267,7 @@ snd_azf3328_codec_trigger(enum snd_azf3328_codec_type codec_type,
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spin_unlock(&chip->reg_lock);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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snd_azf3328_dbgplay("STOP %s\n", codec->name);
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snd_azf3328_dbgcodec("STOP %s\n", codec->name);
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if (is_playback_codec) {
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/* mute WaveOut (avoid clicking during setup) */
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@ -1294,10 +1303,10 @@ snd_azf3328_codec_trigger(enum snd_azf3328_codec_type codec_type,
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);
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}
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snd_azf3328_dbgplay("STOPPED %s\n", codec->name);
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snd_azf3328_dbgcodec("STOPPED %s\n", codec->name);
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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snd_azf3328_dbgplay("SUSPEND %s\n", codec->name);
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snd_azf3328_dbgcodec("SUSPEND %s\n", codec->name);
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/* make sure codec is stopped */
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snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
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snd_azf3328_codec_inw(
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@ -1312,7 +1321,7 @@ snd_azf3328_codec_trigger(enum snd_azf3328_codec_type codec_type,
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snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
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break;
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default:
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printk(KERN_ERR "FIXME: unknown trigger mode!\n");
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snd_printk(KERN_ERR "FIXME: unknown trigger mode!\n");
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return -EINVAL;
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}
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@ -1358,7 +1367,7 @@ snd_azf3328_codec_pointer(struct snd_pcm_substream *substream,
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/* calculate offset */
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result -= bufptr;
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frmres = bytes_to_frames( substream->runtime, result);
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snd_azf3328_dbgplay("%s @ 0x%8lx, frames %8ld\n",
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snd_azf3328_dbgcodec("%s @ 0x%8lx, frames %8ld\n",
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codec->name, result, frmres);
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return frmres;
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}
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@ -1607,7 +1616,7 @@ snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
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static inline void
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snd_azf3328_irq_log_unknown_type(u8 which)
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{
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snd_azf3328_dbgplay(
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snd_azf3328_dbgcodec(
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"azt3328: unknown IRQ type (%x) occurred, please report!\n",
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which
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);
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@ -1636,12 +1645,9 @@ snd_azf3328_codec_interrupt(struct snd_azf3328 *chip, u8 status)
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snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which);
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spin_unlock(&chip->reg_lock);
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if ((chip->pcm[codec_type])
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&& (chip->codecs[codec_type].substream)) {
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snd_pcm_period_elapsed(
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chip->codecs[codec_type].substream
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);
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snd_azf3328_dbgplay("%s period done (#%x), @ %x\n",
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if ((chip->pcm[codec_type]) && (codec->substream)) {
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snd_pcm_period_elapsed(codec->substream);
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snd_azf3328_dbgcodec("%s period done (#%x), @ %x\n",
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codec->name,
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which,
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snd_azf3328_codec_inl(
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@ -1660,7 +1666,7 @@ snd_azf3328_interrupt(int irq, void *dev_id)
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{
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struct snd_azf3328 *chip = dev_id;
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u8 status;
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#if DEBUG_PLAY_REC
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#if DEBUG_CODEC
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static unsigned long irq_count;
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#endif
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@ -1673,14 +1679,14 @@ snd_azf3328_interrupt(int irq, void *dev_id)
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))
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return IRQ_NONE; /* must be interrupt for another device */
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snd_azf3328_dbgplay(
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snd_azf3328_dbgcodec(
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"irq_count %ld! IDX_IO_IRQSTATUS %04x\n",
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irq_count++ /* debug-only */,
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status
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);
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if (status & IRQ_TIMER) {
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/* snd_azf3328_dbgplay("timer %ld\n",
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/* snd_azf3328_dbgcodec("timer %ld\n",
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snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
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& TIMER_VALUE_MASK
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); */
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@ -1690,7 +1696,7 @@ snd_azf3328_interrupt(int irq, void *dev_id)
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spin_lock(&chip->reg_lock);
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snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
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spin_unlock(&chip->reg_lock);
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snd_azf3328_dbgplay("azt3328: timer IRQ\n");
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snd_azf3328_dbgcodec("azt3328: timer IRQ\n");
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}
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if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT))
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@ -1706,7 +1712,7 @@ snd_azf3328_interrupt(int irq, void *dev_id)
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/* hmm, do we have to ack the IRQ here somehow?
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* If so, then I don't know how yet... */
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snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n");
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snd_azf3328_dbgcodec("azt3328: MPU401 IRQ\n");
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}
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return IRQ_HANDLED;
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}
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@ -2091,7 +2097,7 @@ snd_azf3328_test_bit(unsigned unsigned reg, int bit)
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outb(val, reg);
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printk(KERN_ERR "reg %04x bit %d: %02x %02x %02x\n",
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printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n",
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reg, bit, val, valoff, valon
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);
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}
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@ -2298,8 +2304,11 @@ snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
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card->private_data = chip;
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/* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401,
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since our hardware ought to be similar, thus use same ID. */
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err = snd_mpu401_uart_new(
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card, 0, MPU401_HW_MPU401, chip->mpu_io, MPU401_INFO_INTEGRATED,
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card, 0,
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MPU401_HW_AZT2320, chip->mpu_io, MPU401_INFO_INTEGRATED,
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pci->irq, 0, &chip->rmidi
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);
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if (err < 0) {
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@ -2342,7 +2351,7 @@ snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
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goto out_err;
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#ifdef MODULE
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printk(
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printk(KERN_INFO
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"azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"
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"azt3328: Hardware was completely undocumented, unfortunately.\n"
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"azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
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@ -2377,37 +2386,52 @@ snd_azf3328_remove(struct pci_dev *pci)
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}
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#ifdef CONFIG_PM
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static inline void
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snd_azf3328_suspend_regs(unsigned long io_addr, unsigned count, u32 *saved_regs)
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{
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unsigned reg;
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for (reg = 0; reg < count; ++reg) {
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*saved_regs = inl(io_addr);
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snd_azf3328_dbgpm("suspend: io 0x%04lx: 0x%08x\n",
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io_addr, *saved_regs);
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++saved_regs;
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io_addr += sizeof(*saved_regs);
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}
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}
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static int
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snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
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{
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struct snd_card *card = pci_get_drvdata(pci);
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struct snd_azf3328 *chip = card->private_data;
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unsigned reg;
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u16 *saved_regs_ctrl_u16;
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snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
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snd_pcm_suspend_all(chip->pcm[AZF_CODEC_PLAYBACK]);
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snd_pcm_suspend_all(chip->pcm[AZF_CODEC_I2S_OUT]);
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for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; ++reg)
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chip->saved_regs_mixer[reg] = inw(chip->mixer_io + reg * 2);
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snd_azf3328_suspend_regs(chip->mixer_io,
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ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
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/* make sure to disable master volume etc. to prevent looping sound */
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snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
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snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
|
||||
|
||||
for (reg = 0; reg < AZF_IO_SIZE_CTRL_PM / 2; ++reg)
|
||||
chip->saved_regs_ctrl[reg] = inw(chip->ctrl_io + reg * 2);
|
||||
snd_azf3328_suspend_regs(chip->ctrl_io,
|
||||
ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl);
|
||||
|
||||
/* manually store the one currently relevant write-only reg, too */
|
||||
chip->saved_regs_ctrl[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
|
||||
saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
|
||||
saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
|
||||
|
||||
for (reg = 0; reg < AZF_IO_SIZE_GAME_PM / 2; ++reg)
|
||||
chip->saved_regs_game[reg] = inw(chip->game_io + reg * 2);
|
||||
for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; ++reg)
|
||||
chip->saved_regs_mpu[reg] = inw(chip->mpu_io + reg * 2);
|
||||
for (reg = 0; reg < AZF_IO_SIZE_OPL3_PM / 2; ++reg)
|
||||
chip->saved_regs_opl3[reg] = inw(chip->opl3_io + reg * 2);
|
||||
snd_azf3328_suspend_regs(chip->game_io,
|
||||
ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game);
|
||||
snd_azf3328_suspend_regs(chip->mpu_io,
|
||||
ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu);
|
||||
snd_azf3328_suspend_regs(chip->opl3_io,
|
||||
ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3);
|
||||
|
||||
pci_disable_device(pci);
|
||||
pci_save_state(pci);
|
||||
@ -2415,12 +2439,28 @@ snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
snd_azf3328_resume_regs(const u32 *saved_regs,
|
||||
unsigned long io_addr,
|
||||
unsigned count
|
||||
)
|
||||
{
|
||||
unsigned reg;
|
||||
|
||||
for (reg = 0; reg < count; ++reg) {
|
||||
outl(*saved_regs, io_addr);
|
||||
snd_azf3328_dbgpm("resume: io 0x%04lx: 0x%08x --> 0x%08x\n",
|
||||
io_addr, *saved_regs, inl(io_addr));
|
||||
++saved_regs;
|
||||
io_addr += sizeof(*saved_regs);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
snd_azf3328_resume(struct pci_dev *pci)
|
||||
{
|
||||
struct snd_card *card = pci_get_drvdata(pci);
|
||||
const struct snd_azf3328 *chip = card->private_data;
|
||||
unsigned reg;
|
||||
|
||||
pci_set_power_state(pci, PCI_D0);
|
||||
pci_restore_state(pci);
|
||||
@ -2432,16 +2472,24 @@ snd_azf3328_resume(struct pci_dev *pci)
|
||||
}
|
||||
pci_set_master(pci);
|
||||
|
||||
for (reg = 0; reg < AZF_IO_SIZE_GAME_PM / 2; ++reg)
|
||||
outw(chip->saved_regs_game[reg], chip->game_io + reg * 2);
|
||||
for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; ++reg)
|
||||
outw(chip->saved_regs_mpu[reg], chip->mpu_io + reg * 2);
|
||||
for (reg = 0; reg < AZF_IO_SIZE_OPL3_PM / 2; ++reg)
|
||||
outw(chip->saved_regs_opl3[reg], chip->opl3_io + reg * 2);
|
||||
for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; ++reg)
|
||||
outw(chip->saved_regs_mixer[reg], chip->mixer_io + reg * 2);
|
||||
for (reg = 0; reg < AZF_IO_SIZE_CTRL_PM / 2; ++reg)
|
||||
outw(chip->saved_regs_ctrl[reg], chip->ctrl_io + reg * 2);
|
||||
snd_azf3328_resume_regs(chip->saved_regs_game, chip->game_io,
|
||||
ARRAY_SIZE(chip->saved_regs_game));
|
||||
snd_azf3328_resume_regs(chip->saved_regs_mpu, chip->mpu_io,
|
||||
ARRAY_SIZE(chip->saved_regs_mpu));
|
||||
snd_azf3328_resume_regs(chip->saved_regs_opl3, chip->opl3_io,
|
||||
ARRAY_SIZE(chip->saved_regs_opl3));
|
||||
|
||||
snd_azf3328_resume_regs(chip->saved_regs_mixer, chip->mixer_io,
|
||||
ARRAY_SIZE(chip->saved_regs_mixer));
|
||||
|
||||
/* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02)
|
||||
and IDX_MIXER_RESET (offset 0x00) get touched at the same time,
|
||||
resulting in a mixer reset condition persisting until _after_
|
||||
master vol was restored. Thus master vol needs an extra restore. */
|
||||
outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
|
||||
|
||||
snd_azf3328_resume_regs(chip->saved_regs_ctrl, chip->ctrl_io,
|
||||
ARRAY_SIZE(chip->saved_regs_ctrl));
|
||||
|
||||
snd_power_change_state(card, SNDRV_CTL_POWER_D0);
|
||||
return 0;
|
||||
|
||||
@ -120,8 +120,10 @@ enum azf_freq_t {
|
||||
#define IDX_IO_IRQSTATUS 0x64
|
||||
/* some IRQ bit in here might also be used to signal a power-management timer
|
||||
* timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing).
|
||||
* Some OPL3 hardware (e.g. in LM4560) has some special timer hardware which
|
||||
* can trigger an OPL3 timer IRQ, so maybe there's such a thing as well... */
|
||||
* OPL3 hardware contains several timers which confusingly in most cases
|
||||
* are NOT routed to an IRQ, but some designs (e.g. LM4560) DO support that,
|
||||
* so I wouldn't be surprised at all to discover that AZF3328
|
||||
* supports that thing as well... */
|
||||
|
||||
#define IRQ_PLAYBACK 0x0001
|
||||
#define IRQ_RECORDING 0x0002
|
||||
@ -129,8 +131,8 @@ enum azf_freq_t {
|
||||
#define IRQ_GAMEPORT 0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */
|
||||
#define IRQ_MPU401 0x0010
|
||||
#define IRQ_TIMER 0x0020 /* DirectX timer */
|
||||
#define IRQ_UNKNOWN2 0x0040 /* probably unused, or possibly I2S port? */
|
||||
#define IRQ_UNKNOWN3 0x0080 /* probably unused, or possibly I2S port? */
|
||||
#define IRQ_UNKNOWN2 0x0040 /* probably unused, or possibly OPL3 timer? */
|
||||
#define IRQ_UNKNOWN3 0x0080 /* probably unused, or possibly OPL3 timer? */
|
||||
#define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */
|
||||
/* this is set to e.g. 0x3ff or 0x300, and writable;
|
||||
* maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */
|
||||
@ -193,7 +195,7 @@ enum azf_freq_t {
|
||||
/*** Gameport area port indices ***/
|
||||
/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
|
||||
#define AZF_IO_SIZE_GAME 0x08
|
||||
#define AZF_IO_SIZE_GAME_PM 0x06
|
||||
#define AZF_IO_SIZE_GAME_PM 0x06
|
||||
|
||||
enum {
|
||||
AZF_GAME_LEGACY_IO_PORT = 0x200
|
||||
@ -274,6 +276,7 @@ enum {
|
||||
#define AZF_IO_SIZE_MPU_PM 0x04
|
||||
|
||||
/*** OPL3 synth ***/
|
||||
/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
|
||||
#define AZF_IO_SIZE_OPL3 0x08
|
||||
#define AZF_IO_SIZE_OPL3_PM 0x06
|
||||
/* hmm, given that a standard OPL3 has 4 registers only,
|
||||
@ -333,4 +336,7 @@ enum {
|
||||
#define SET_CHAN_LEFT 1
|
||||
#define SET_CHAN_RIGHT 2
|
||||
|
||||
/* helper macro to align I/O port ranges to 32bit I/O width */
|
||||
#define AZF_ALIGN(x) (((x) + 3) & (~3))
|
||||
|
||||
#endif /* __SOUND_AZT3328_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user