mirror of
https://github.com/joel16/android_kernel_sony_msm8994_rework.git
synced 2024-12-04 18:17:38 +00:00
spi_mpc83xx: much improved driver
The current driver may cause glitches on SPI CLK line since one must disable the SPI controller before changing any HW settings. Fix this by implementing a local spi_transfer function that won't change speed and/or word size while CS is active. While doing that heavy lifting a few other issues were addressed too: - Make word size 16 and 32 work too. - Honor bits_per_word and speed_hz in spi transaction. - Optimize the common path. This also stops using the "bitbang" framework (except for a few constants). [Roel Kluin <12o3l@tiscali.nl>: "irq" needs to be signed] Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Joakim Tjernlund
Linus Torvalds
parent
f4ed0deae8
commit
c9bfcb3151
@ -126,7 +126,6 @@ config SPI_MPC52xx_PSC
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config SPI_MPC83xx
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tristate "Freescale MPC83xx/QUICC Engine SPI controller"
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depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
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select SPI_BITBANG
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help
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This enables using the Freescale MPC83xx and QUICC Engine SPI
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controllers in master mode.
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@ -49,6 +49,7 @@ struct mpc83xx_spi_reg {
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#define SPMODE_LEN(x) ((x) << 20)
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#define SPMODE_PM(x) ((x) << 16)
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#define SPMODE_OP (1 << 14)
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#define SPMODE_CG(x) ((x) << 7)
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/*
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* Default for SPI Mode:
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@ -67,10 +68,6 @@ struct mpc83xx_spi_reg {
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/* SPI Controller driver's private data. */
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struct mpc83xx_spi {
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/* bitbang has to be first */
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struct spi_bitbang bitbang;
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struct completion done;
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struct mpc83xx_spi_reg __iomem *base;
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/* rx & tx bufs from the spi_transfer */
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@ -82,7 +79,7 @@ struct mpc83xx_spi {
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u32(*get_tx) (struct mpc83xx_spi *);
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unsigned int count;
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u32 irq;
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int irq;
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unsigned nsecs; /* (clock cycle time)/2 */
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@ -94,6 +91,25 @@ struct mpc83xx_spi {
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void (*activate_cs) (u8 cs, u8 polarity);
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void (*deactivate_cs) (u8 cs, u8 polarity);
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u8 busy;
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struct workqueue_struct *workqueue;
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struct work_struct work;
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struct list_head queue;
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spinlock_t lock;
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struct completion done;
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};
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struct spi_mpc83xx_cs {
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
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u32 (*get_tx) (struct mpc83xx_spi *);
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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u32 hw_mode; /* Holds HW mode register settings */
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};
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static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
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@ -137,6 +153,7 @@ static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
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{
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struct mpc83xx_spi *mpc83xx_spi;
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u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
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struct spi_mpc83xx_cs *cs = spi->controller_state;
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mpc83xx_spi = spi_master_get_devdata(spi->master);
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@ -147,50 +164,26 @@ static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
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if (value == BITBANG_CS_ACTIVE) {
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u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
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u32 len = spi->bits_per_word;
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u8 pm;
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if (len == 32)
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len = 0;
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else
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len = len - 1;
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mpc83xx_spi->rx_shift = cs->rx_shift;
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mpc83xx_spi->tx_shift = cs->tx_shift;
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mpc83xx_spi->get_rx = cs->get_rx;
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mpc83xx_spi->get_tx = cs->get_tx;
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/* mask out bits we are going to set */
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regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
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| SPMODE_LEN(0xF) | SPMODE_DIV16
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| SPMODE_PM(0xF) | SPMODE_REV | SPMODE_LOOP);
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if (cs->hw_mode != regval) {
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unsigned long flags;
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void *tmp_ptr = &mpc83xx_spi->base->mode;
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if (spi->mode & SPI_CPHA)
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regval |= SPMODE_CP_BEGIN_EDGECLK;
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if (spi->mode & SPI_CPOL)
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regval |= SPMODE_CI_INACTIVEHIGH;
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if (!(spi->mode & SPI_LSB_FIRST))
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regval |= SPMODE_REV;
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if (spi->mode & SPI_LOOP)
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regval |= SPMODE_LOOP;
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regval |= SPMODE_LEN(len);
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if ((mpc83xx_spi->spibrg / spi->max_speed_hz) >= 64) {
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pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 64) - 1;
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if (pm > 0x0f) {
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dev_err(&spi->dev, "Requested speed is too "
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"low: %d Hz. Will use %d Hz instead.\n",
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spi->max_speed_hz,
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mpc83xx_spi->spibrg / 1024);
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pm = 0x0f;
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}
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regval |= SPMODE_PM(pm) | SPMODE_DIV16;
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} else {
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pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 4);
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if (pm)
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pm--;
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regval |= SPMODE_PM(pm);
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regval = cs->hw_mode;
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/* Turn off IRQs locally to minimize time that
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* SPI is disabled
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*/
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
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mpc83xx_spi_write_reg(tmp_ptr, regval);
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local_irq_restore(flags);
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}
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/* Turn off SPI unit prior changing mode */
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mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
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mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
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if (mpc83xx_spi->activate_cs)
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mpc83xx_spi->activate_cs(spi->chip_select, pol);
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}
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@ -201,8 +194,9 @@ int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct mpc83xx_spi *mpc83xx_spi;
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u32 regval;
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u8 bits_per_word;
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u8 bits_per_word, pm;
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u32 hz;
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struct spi_mpc83xx_cs *cs = spi->controller_state;
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mpc83xx_spi = spi_master_get_devdata(spi->master);
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@ -223,122 +217,106 @@ int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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|| ((bits_per_word > 16) && (bits_per_word != 32)))
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return -EINVAL;
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mpc83xx_spi->rx_shift = 0;
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mpc83xx_spi->tx_shift = 0;
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if (!hz)
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hz = spi->max_speed_hz;
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cs->rx_shift = 0;
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cs->tx_shift = 0;
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if (bits_per_word <= 8) {
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mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
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mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
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cs->get_rx = mpc83xx_spi_rx_buf_u8;
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cs->get_tx = mpc83xx_spi_tx_buf_u8;
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if (mpc83xx_spi->qe_mode) {
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mpc83xx_spi->rx_shift = 16;
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mpc83xx_spi->tx_shift = 24;
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cs->rx_shift = 16;
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cs->tx_shift = 24;
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}
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} else if (bits_per_word <= 16) {
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mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
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mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
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cs->get_rx = mpc83xx_spi_rx_buf_u16;
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cs->get_tx = mpc83xx_spi_tx_buf_u16;
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if (mpc83xx_spi->qe_mode) {
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mpc83xx_spi->rx_shift = 16;
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mpc83xx_spi->tx_shift = 16;
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cs->rx_shift = 16;
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cs->tx_shift = 16;
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}
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} else if (bits_per_word <= 32) {
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mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
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mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
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cs->get_rx = mpc83xx_spi_rx_buf_u32;
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cs->get_tx = mpc83xx_spi_tx_buf_u32;
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} else
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return -EINVAL;
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if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
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mpc83xx_spi->tx_shift = 0;
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cs->tx_shift = 0;
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if (bits_per_word <= 8)
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mpc83xx_spi->rx_shift = 8;
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cs->rx_shift = 8;
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else
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mpc83xx_spi->rx_shift = 0;
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cs->rx_shift = 0;
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}
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/* nsecs = (clock period)/2 */
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if (!hz)
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hz = spi->max_speed_hz;
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mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
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if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
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return -EINVAL;
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mpc83xx_spi->rx_shift = cs->rx_shift;
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mpc83xx_spi->tx_shift = cs->tx_shift;
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mpc83xx_spi->get_rx = cs->get_rx;
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mpc83xx_spi->get_tx = cs->get_tx;
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if (bits_per_word == 32)
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bits_per_word = 0;
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else
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bits_per_word = bits_per_word - 1;
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regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
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/* mask out bits we are going to set */
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regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV);
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regval |= SPMODE_LEN(bits_per_word);
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if (!(spi->mode & SPI_LSB_FIRST))
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regval |= SPMODE_REV;
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cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
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| SPMODE_PM(0xF));
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/* Turn off SPI unit prior changing mode */
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mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
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mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
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cs->hw_mode |= SPMODE_LEN(bits_per_word);
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return 0;
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
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| SPI_LSB_FIRST | SPI_LOOP)
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static int mpc83xx_spi_setup(struct spi_device *spi)
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{
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struct spi_bitbang *bitbang;
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struct mpc83xx_spi *mpc83xx_spi;
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int retval;
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if (spi->mode & ~MODEBITS) {
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dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
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spi->mode & ~MODEBITS);
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return -EINVAL;
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if ((mpc83xx_spi->spibrg / hz) >= 64) {
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pm = mpc83xx_spi->spibrg / (hz * 64) - 1;
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if (pm > 0x0f) {
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dev_err(&spi->dev, "Requested speed is too "
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"low: %d Hz. Will use %d Hz instead.\n",
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hz, mpc83xx_spi->spibrg / 1024);
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pm = 0x0f;
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}
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cs->hw_mode |= SPMODE_PM(pm) | SPMODE_DIV16;
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} else {
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pm = mpc83xx_spi->spibrg / (hz * 4);
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if (pm)
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pm--;
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cs->hw_mode |= SPMODE_PM(pm);
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}
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regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
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if (cs->hw_mode != regval) {
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unsigned long flags;
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void *tmp_ptr = &mpc83xx_spi->base->mode;
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if (!spi->max_speed_hz)
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return -EINVAL;
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bitbang = spi_master_get_devdata(spi->master);
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mpc83xx_spi = spi_master_get_devdata(spi->master);
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if (!spi->bits_per_word)
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spi->bits_per_word = 8;
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retval = mpc83xx_spi_setup_transfer(spi, NULL);
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if (retval < 0)
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return retval;
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dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
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__func__, spi->mode & (SPI_CPOL | SPI_CPHA),
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spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
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/* NOTE we _need_ to call chipselect() early, ideally with adapter
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* setup, unless the hardware defaults cooperate to avoid confusion
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* between normal (active low) and inverted chipselects.
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*/
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/* deselect chip (low or high) */
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spin_lock(&bitbang->lock);
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if (!bitbang->busy) {
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bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(mpc83xx_spi->nsecs);
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regval = cs->hw_mode;
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/* Turn off IRQs locally to minimize time
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* that SPI is disabled
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*/
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
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mpc83xx_spi_write_reg(tmp_ptr, regval);
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local_irq_restore(flags);
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}
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spin_unlock(&bitbang->lock);
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return 0;
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}
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static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct mpc83xx_spi *mpc83xx_spi;
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u32 word;
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u32 word, len, bits_per_word;
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mpc83xx_spi = spi_master_get_devdata(spi->master);
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mpc83xx_spi->tx = t->tx_buf;
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mpc83xx_spi->rx = t->rx_buf;
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mpc83xx_spi->count = t->len;
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bits_per_word = spi->bits_per_word;
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if (t->bits_per_word)
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bits_per_word = t->bits_per_word;
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len = t->len;
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if (bits_per_word > 8)
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len /= 2;
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if (bits_per_word > 16)
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len /= 2;
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mpc83xx_spi->count = len;
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INIT_COMPLETION(mpc83xx_spi->done);
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/* enable rx ints */
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@ -353,7 +331,147 @@ static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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/* disable rx ints */
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mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
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return t->len - mpc83xx_spi->count;
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return mpc83xx_spi->count;
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}
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static void mpc83xx_spi_work(struct work_struct *work)
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{
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struct mpc83xx_spi *mpc83xx_spi =
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container_of(work, struct mpc83xx_spi, work);
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spin_lock_irq(&mpc83xx_spi->lock);
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mpc83xx_spi->busy = 1;
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while (!list_empty(&mpc83xx_spi->queue)) {
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struct spi_message *m;
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struct spi_device *spi;
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struct spi_transfer *t = NULL;
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unsigned cs_change;
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int status, nsecs = 50;
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m = container_of(mpc83xx_spi->queue.next,
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struct spi_message, queue);
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list_del_init(&m->queue);
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spin_unlock_irq(&mpc83xx_spi->lock);
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spi = m->spi;
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cs_change = 1;
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status = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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/* Don't allow changes if CS is active */
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status = -EINVAL;
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if (cs_change)
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status = mpc83xx_spi_setup_transfer(spi, t);
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if (status < 0)
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break;
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}
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if (cs_change)
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mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
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cs_change = t->cs_change;
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if (t->len)
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status = mpc83xx_spi_bufs(spi, t);
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if (status) {
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status = -EMSGSIZE;
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break;
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}
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m->actual_length += t->len;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (cs_change) {
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ndelay(nsecs);
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mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(nsecs);
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}
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}
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m->status = status;
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m->complete(m->context);
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if (status || !cs_change) {
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ndelay(nsecs);
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mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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}
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mpc83xx_spi_setup_transfer(spi, NULL);
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spin_lock_irq(&mpc83xx_spi->lock);
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}
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mpc83xx_spi->busy = 0;
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spin_unlock_irq(&mpc83xx_spi->lock);
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
|
||||
| SPI_LSB_FIRST | SPI_LOOP)
|
||||
|
||||
static int mpc83xx_spi_setup(struct spi_device *spi)
|
||||
{
|
||||
struct mpc83xx_spi *mpc83xx_spi;
|
||||
int retval;
|
||||
u32 hw_mode;
|
||||
struct spi_mpc83xx_cs *cs = spi->controller_state;
|
||||
|
||||
if (spi->mode & ~MODEBITS) {
|
||||
dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
|
||||
spi->mode & ~MODEBITS);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!spi->max_speed_hz)
|
||||
return -EINVAL;
|
||||
|
||||
if (!cs) {
|
||||
cs = kzalloc(sizeof *cs, GFP_KERNEL);
|
||||
if (!cs)
|
||||
return -ENOMEM;
|
||||
spi->controller_state = cs;
|
||||
}
|
||||
mpc83xx_spi = spi_master_get_devdata(spi->master);
|
||||
|
||||
if (!spi->bits_per_word)
|
||||
spi->bits_per_word = 8;
|
||||
|
||||
hw_mode = cs->hw_mode; /* Save orginal settings */
|
||||
cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
|
||||
/* mask out bits we are going to set */
|
||||
cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
|
||||
| SPMODE_REV | SPMODE_LOOP);
|
||||
|
||||
if (spi->mode & SPI_CPHA)
|
||||
cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
|
||||
if (spi->mode & SPI_CPOL)
|
||||
cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
|
||||
if (!(spi->mode & SPI_LSB_FIRST))
|
||||
cs->hw_mode |= SPMODE_REV;
|
||||
if (spi->mode & SPI_LOOP)
|
||||
cs->hw_mode |= SPMODE_LOOP;
|
||||
|
||||
retval = mpc83xx_spi_setup_transfer(spi, NULL);
|
||||
if (retval < 0) {
|
||||
cs->hw_mode = hw_mode; /* Restore settings */
|
||||
return retval;
|
||||
}
|
||||
|
||||
dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
|
||||
__func__, spi->mode & (SPI_CPOL | SPI_CPHA),
|
||||
spi->bits_per_word, spi->max_speed_hz);
|
||||
#if 0 /* Don't think this is needed */
|
||||
/* NOTE we _need_ to call chipselect() early, ideally with adapter
|
||||
* setup, unless the hardware defaults cooperate to avoid confusion
|
||||
* between normal (active low) and inverted chipselects.
|
||||
*/
|
||||
|
||||
/* deselect chip (low or high) */
|
||||
spin_lock(&mpc83xx_spi->lock);
|
||||
if (!mpc83xx_spi->busy)
|
||||
mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
|
||||
spin_unlock(&mpc83xx_spi->lock);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
|
||||
@ -395,6 +513,28 @@ irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
|
||||
|
||||
return ret;
|
||||
}
|
||||
static int mpc83xx_spi_transfer(struct spi_device *spi,
|
||||
struct spi_message *m)
|
||||
{
|
||||
struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
|
||||
unsigned long flags;
|
||||
|
||||
m->actual_length = 0;
|
||||
m->status = -EINPROGRESS;
|
||||
|
||||
spin_lock_irqsave(&mpc83xx_spi->lock, flags);
|
||||
list_add_tail(&m->queue, &mpc83xx_spi->queue);
|
||||
queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
|
||||
spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void mpc83xx_spi_cleanup(struct spi_device *spi)
|
||||
{
|
||||
kfree(spi->controller_state);
|
||||
}
|
||||
|
||||
static int __init mpc83xx_spi_probe(struct platform_device *dev)
|
||||
{
|
||||
@ -426,11 +566,11 @@ static int __init mpc83xx_spi_probe(struct platform_device *dev)
|
||||
ret = -ENODEV;
|
||||
goto free_master;
|
||||
}
|
||||
master->setup = mpc83xx_spi_setup;
|
||||
master->transfer = mpc83xx_spi_transfer;
|
||||
master->cleanup = mpc83xx_spi_cleanup;
|
||||
|
||||
mpc83xx_spi = spi_master_get_devdata(master);
|
||||
mpc83xx_spi->bitbang.master = spi_master_get(master);
|
||||
mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
|
||||
mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
|
||||
mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
|
||||
mpc83xx_spi->activate_cs = pdata->activate_cs;
|
||||
mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
|
||||
mpc83xx_spi->qe_mode = pdata->qe_mode;
|
||||
@ -445,7 +585,6 @@ static int __init mpc83xx_spi_probe(struct platform_device *dev)
|
||||
mpc83xx_spi->tx_shift = 24;
|
||||
}
|
||||
|
||||
mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
|
||||
init_completion(&mpc83xx_spi->done);
|
||||
|
||||
mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
|
||||
@ -483,11 +622,21 @@ static int __init mpc83xx_spi_probe(struct platform_device *dev)
|
||||
regval |= SPMODE_OP;
|
||||
|
||||
mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
|
||||
spin_lock_init(&mpc83xx_spi->lock);
|
||||
init_completion(&mpc83xx_spi->done);
|
||||
INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
|
||||
INIT_LIST_HEAD(&mpc83xx_spi->queue);
|
||||
|
||||
ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
|
||||
|
||||
if (ret != 0)
|
||||
mpc83xx_spi->workqueue = create_singlethread_workqueue(
|
||||
master->dev.parent->bus_id);
|
||||
if (mpc83xx_spi->workqueue == NULL) {
|
||||
ret = -EBUSY;
|
||||
goto free_irq;
|
||||
}
|
||||
|
||||
ret = spi_register_master(master);
|
||||
if (ret < 0)
|
||||
goto unreg_master;
|
||||
|
||||
printk(KERN_INFO
|
||||
"%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
|
||||
@ -495,6 +644,8 @@ static int __init mpc83xx_spi_probe(struct platform_device *dev)
|
||||
|
||||
return ret;
|
||||
|
||||
unreg_master:
|
||||
destroy_workqueue(mpc83xx_spi->workqueue);
|
||||
free_irq:
|
||||
free_irq(mpc83xx_spi->irq, mpc83xx_spi);
|
||||
unmap_io:
|
||||
@ -515,10 +666,12 @@ static int __exit mpc83xx_spi_remove(struct platform_device *dev)
|
||||
master = platform_get_drvdata(dev);
|
||||
mpc83xx_spi = spi_master_get_devdata(master);
|
||||
|
||||
spi_bitbang_stop(&mpc83xx_spi->bitbang);
|
||||
flush_workqueue(mpc83xx_spi->workqueue);
|
||||
destroy_workqueue(mpc83xx_spi->workqueue);
|
||||
spi_unregister_master(master);
|
||||
|
||||
free_irq(mpc83xx_spi->irq, mpc83xx_spi);
|
||||
iounmap(mpc83xx_spi->base);
|
||||
spi_master_put(mpc83xx_spi->bitbang.master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user