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https://github.com/joel16/android_kernel_sony_msm8994_rework.git
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SC26XX: New serial driver for SC2681 uarts
New serial driver for SC2681/SC2691 uarts. Older SNI RM400 machines are using these chips for onboard serial ports. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Torben Mathiasen <device@lanana.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Thomas Bogendoerfer
Linus Torvalds
parent
f5d3f30d0a
commit
eea63e0e8a
@ -1318,4 +1318,19 @@ config SERIAL_QE
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This driver supports the QE serial ports on Freescale embedded
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PowerPC that contain a QUICC Engine.
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config SERIAL_SC26XX
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tristate "SC2681/SC2692 serial port support"
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depends on SNI_RM
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select SERIAL_CORE
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help
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This is a driver for the onboard serial ports of
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older RM400 machines.
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config SERIAL_SC26XX_CONSOLE
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bool "Console on SC2681/SC2692 serial port"
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depends on SERIAL_SC26XX
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select SERIAL_CORE_CONSOLE
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help
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Support for Console on SC2681/SC2692 serial ports.
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endmenu
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@ -55,6 +55,7 @@ obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o
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obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
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obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
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obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
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obj-$(CONFIG_SERIAL_SC26XX) += sc26xx.o
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obj-$(CONFIG_SERIAL_JSM) += jsm/
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obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
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obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
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755
drivers/serial/sc26xx.c
Normal file
755
drivers/serial/sc26xx.c
Normal file
@ -0,0 +1,755 @@
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/*
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* SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
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*
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* Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/major.h>
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#include <linux/circ_buf.h>
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#include <linux/serial.h>
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#include <linux/sysrq.h>
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#include <linux/console.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#if defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/serial_core.h>
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#define SC26XX_MAJOR 204
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#define SC26XX_MINOR_START 205
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#define SC26XX_NR 2
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struct uart_sc26xx_port {
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struct uart_port port[2];
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u8 dsr_mask[2];
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u8 cts_mask[2];
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u8 dcd_mask[2];
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u8 ri_mask[2];
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u8 dtr_mask[2];
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u8 rts_mask[2];
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u8 imr;
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};
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/* register common to both ports */
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#define RD_ISR 0x14
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#define RD_IPR 0x34
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#define WR_ACR 0x10
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#define WR_IMR 0x14
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#define WR_OPCR 0x34
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#define WR_OPR_SET 0x38
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#define WR_OPR_CLR 0x3C
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/* access common register */
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#define READ_SC(p, r) readb((p)->membase + RD_##r)
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#define WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r)
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/* register per port */
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#define RD_PORT_MRx 0x00
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#define RD_PORT_SR 0x04
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#define RD_PORT_RHR 0x0c
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#define WR_PORT_MRx 0x00
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#define WR_PORT_CSR 0x04
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#define WR_PORT_CR 0x08
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#define WR_PORT_THR 0x0c
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/* SR bits */
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#define SR_BREAK (1 << 7)
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#define SR_FRAME (1 << 6)
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#define SR_PARITY (1 << 5)
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#define SR_OVERRUN (1 << 4)
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#define SR_TXRDY (1 << 2)
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#define SR_RXRDY (1 << 0)
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#define CR_RES_MR (1 << 4)
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#define CR_RES_RX (2 << 4)
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#define CR_RES_TX (3 << 4)
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#define CR_STRT_BRK (6 << 4)
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#define CR_STOP_BRK (7 << 4)
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#define CR_DIS_TX (1 << 3)
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#define CR_ENA_TX (1 << 2)
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#define CR_DIS_RX (1 << 1)
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#define CR_ENA_RX (1 << 0)
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/* ISR bits */
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#define ISR_RXRDYB (1 << 5)
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#define ISR_TXRDYB (1 << 4)
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#define ISR_RXRDYA (1 << 1)
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#define ISR_TXRDYA (1 << 0)
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/* IMR bits */
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#define IMR_RXRDY (1 << 1)
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#define IMR_TXRDY (1 << 0)
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/* access port register */
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static inline u8 read_sc_port(struct uart_port *p, u8 reg)
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{
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return readb(p->membase + p->line * 0x20 + reg);
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}
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static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
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{
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writeb(val, p->membase + p->line * 0x20 + reg);
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}
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#define READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r)
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#define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)
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static void sc26xx_enable_irq(struct uart_port *port, int mask)
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{
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struct uart_sc26xx_port *up;
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int line = port->line;
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port -= line;
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up = container_of(port, struct uart_sc26xx_port, port[0]);
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up->imr |= mask << (line * 4);
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WRITE_SC(port, IMR, up->imr);
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}
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static void sc26xx_disable_irq(struct uart_port *port, int mask)
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{
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struct uart_sc26xx_port *up;
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int line = port->line;
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port -= line;
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up = container_of(port, struct uart_sc26xx_port, port[0]);
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up->imr &= ~(mask << (line * 4));
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WRITE_SC(port, IMR, up->imr);
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}
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static struct tty_struct *receive_chars(struct uart_port *port)
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{
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struct tty_struct *tty = NULL;
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int limit = 10000;
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unsigned char ch;
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char flag;
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u8 status;
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if (port->info != NULL) /* Unopened serial console */
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tty = port->info->tty;
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while (limit-- > 0) {
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status = READ_SC_PORT(port, SR);
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if (!(status & SR_RXRDY))
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break;
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ch = READ_SC_PORT(port, RHR);
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flag = TTY_NORMAL;
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port->icount.rx++;
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if (unlikely(status & (SR_BREAK | SR_FRAME |
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SR_PARITY | SR_OVERRUN))) {
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if (status & SR_BREAK) {
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status &= ~(SR_PARITY | SR_FRAME);
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port->icount.brk++;
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if (uart_handle_break(port))
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continue;
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} else if (status & SR_PARITY)
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port->icount.parity++;
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else if (status & SR_FRAME)
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port->icount.frame++;
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if (status & SR_OVERRUN)
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port->icount.overrun++;
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status &= port->read_status_mask;
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if (status & SR_BREAK)
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flag = TTY_BREAK;
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else if (status & SR_PARITY)
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flag = TTY_PARITY;
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else if (status & SR_FRAME)
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flag = TTY_FRAME;
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}
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if (uart_handle_sysrq_char(port, ch))
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continue;
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if (status & port->ignore_status_mask)
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continue;
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tty_insert_flip_char(tty, ch, flag);
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}
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return tty;
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}
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static void transmit_chars(struct uart_port *port)
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{
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struct circ_buf *xmit;
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if (!port->info)
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return;
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xmit = &port->info->xmit;
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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sc26xx_disable_irq(port, IMR_TXRDY);
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return;
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}
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while (!uart_circ_empty(xmit)) {
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if (!(READ_SC_PORT(port, SR) & SR_TXRDY))
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break;
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WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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static irqreturn_t sc26xx_interrupt(int irq, void *dev_id)
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{
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struct uart_sc26xx_port *up = dev_id;
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struct tty_struct *tty;
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unsigned long flags;
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u8 isr;
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spin_lock_irqsave(&up->port[0].lock, flags);
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tty = NULL;
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isr = READ_SC(&up->port[0], ISR);
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if (isr & ISR_TXRDYA)
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transmit_chars(&up->port[0]);
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if (isr & ISR_RXRDYA)
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tty = receive_chars(&up->port[0]);
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spin_unlock(&up->port[0].lock);
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if (tty)
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tty_flip_buffer_push(tty);
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spin_lock(&up->port[1].lock);
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tty = NULL;
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if (isr & ISR_TXRDYB)
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transmit_chars(&up->port[1]);
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if (isr & ISR_RXRDYB)
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tty = receive_chars(&up->port[1]);
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spin_unlock_irqrestore(&up->port[1].lock, flags);
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if (tty)
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tty_flip_buffer_push(tty);
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return IRQ_HANDLED;
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}
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/* port->lock is not held. */
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static unsigned int sc26xx_tx_empty(struct uart_port *port)
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{
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return (READ_SC_PORT(port, SR) & SR_TXRDY) ? TIOCSER_TEMT : 0;
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}
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/* port->lock held by caller. */
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static void sc26xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct uart_sc26xx_port *up;
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int line = port->line;
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port -= line;
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up = container_of(port, struct uart_sc26xx_port, port[0]);
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if (up->dtr_mask[line]) {
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if (mctrl & TIOCM_DTR)
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WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
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else
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WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
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}
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if (up->rts_mask[line]) {
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if (mctrl & TIOCM_RTS)
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WRITE_SC(port, OPR_SET, up->rts_mask[line]);
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else
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WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
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}
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}
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/* port->lock is held by caller and interrupts are disabled. */
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static unsigned int sc26xx_get_mctrl(struct uart_port *port)
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{
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struct uart_sc26xx_port *up;
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int line = port->line;
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unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
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u8 ipr;
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port -= line;
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up = container_of(port, struct uart_sc26xx_port, port[0]);
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ipr = READ_SC(port, IPR) ^ 0xff;
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if (up->dsr_mask[line]) {
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mctrl &= ~TIOCM_DSR;
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mctrl |= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
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}
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if (up->cts_mask[line]) {
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mctrl &= ~TIOCM_CTS;
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mctrl |= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
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}
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if (up->dcd_mask[line]) {
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mctrl &= ~TIOCM_CAR;
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mctrl |= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
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}
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if (up->ri_mask[line]) {
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mctrl &= ~TIOCM_RNG;
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mctrl |= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
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}
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return mctrl;
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}
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/* port->lock held by caller. */
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static void sc26xx_stop_tx(struct uart_port *port)
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{
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return;
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}
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/* port->lock held by caller. */
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static void sc26xx_start_tx(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->info->xmit;
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while (!uart_circ_empty(xmit)) {
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if (!(READ_SC_PORT(port, SR) & SR_TXRDY)) {
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sc26xx_enable_irq(port, IMR_TXRDY);
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break;
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}
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WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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}
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/* port->lock held by caller. */
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static void sc26xx_stop_rx(struct uart_port *port)
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{
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}
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/* port->lock held by caller. */
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static void sc26xx_enable_ms(struct uart_port *port)
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{
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}
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/* port->lock is not held. */
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static void sc26xx_break_ctl(struct uart_port *port, int break_state)
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{
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if (break_state == -1)
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WRITE_SC_PORT(port, CR, CR_STRT_BRK);
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else
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WRITE_SC_PORT(port, CR, CR_STOP_BRK);
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}
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/* port->lock is not held. */
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static int sc26xx_startup(struct uart_port *port)
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{
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sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
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WRITE_SC(port, OPCR, 0);
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/* reset tx and rx */
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WRITE_SC_PORT(port, CR, CR_RES_RX);
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WRITE_SC_PORT(port, CR, CR_RES_TX);
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/* start rx/tx */
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WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
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/* enable irqs */
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sc26xx_enable_irq(port, IMR_RXRDY);
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return 0;
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}
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/* port->lock is not held. */
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static void sc26xx_shutdown(struct uart_port *port)
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{
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/* disable interrupst */
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sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
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/* stop tx/rx */
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WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
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}
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/* port->lock is not held. */
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static void sc26xx_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
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unsigned int quot = uart_get_divisor(port, baud);
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unsigned int iflag, cflag;
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unsigned long flags;
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u8 mr1, mr2, csr;
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spin_lock_irqsave(&port->lock, flags);
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while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
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udelay(2);
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WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
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iflag = termios->c_iflag;
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cflag = termios->c_cflag;
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port->read_status_mask = SR_OVERRUN;
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if (iflag & INPCK)
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port->read_status_mask |= SR_PARITY | SR_FRAME;
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if (iflag & (BRKINT | PARMRK))
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port->read_status_mask |= SR_BREAK;
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port->ignore_status_mask = 0;
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if (iflag & IGNBRK)
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port->ignore_status_mask |= SR_BREAK;
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if ((cflag & CREAD) == 0)
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port->ignore_status_mask |= SR_BREAK | SR_FRAME |
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SR_PARITY | SR_OVERRUN;
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switch (cflag & CSIZE) {
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case CS5:
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mr1 = 0x00;
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break;
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case CS6:
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mr1 = 0x01;
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break;
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case CS7:
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mr1 = 0x02;
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break;
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default:
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case CS8:
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mr1 = 0x03;
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break;
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}
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mr2 = 0x07;
|
||||
if (cflag & CSTOPB)
|
||||
mr2 = 0x0f;
|
||||
if (cflag & PARENB) {
|
||||
if (cflag & PARODD)
|
||||
mr1 |= (1 << 2);
|
||||
} else
|
||||
mr1 |= (2 << 3);
|
||||
|
||||
switch (baud) {
|
||||
case 50:
|
||||
csr = 0x00;
|
||||
break;
|
||||
case 110:
|
||||
csr = 0x11;
|
||||
break;
|
||||
case 134:
|
||||
csr = 0x22;
|
||||
break;
|
||||
case 200:
|
||||
csr = 0x33;
|
||||
break;
|
||||
case 300:
|
||||
csr = 0x44;
|
||||
break;
|
||||
case 600:
|
||||
csr = 0x55;
|
||||
break;
|
||||
case 1200:
|
||||
csr = 0x66;
|
||||
break;
|
||||
case 2400:
|
||||
csr = 0x88;
|
||||
break;
|
||||
case 4800:
|
||||
csr = 0x99;
|
||||
break;
|
||||
default:
|
||||
case 9600:
|
||||
csr = 0xbb;
|
||||
break;
|
||||
case 19200:
|
||||
csr = 0xcc;
|
||||
break;
|
||||
}
|
||||
|
||||
WRITE_SC_PORT(port, CR, CR_RES_MR);
|
||||
WRITE_SC_PORT(port, MRx, mr1);
|
||||
WRITE_SC_PORT(port, MRx, mr2);
|
||||
|
||||
WRITE_SC(port, ACR, 0x80);
|
||||
WRITE_SC_PORT(port, CSR, csr);
|
||||
|
||||
/* reset tx and rx */
|
||||
WRITE_SC_PORT(port, CR, CR_RES_RX);
|
||||
WRITE_SC_PORT(port, CR, CR_RES_TX);
|
||||
|
||||
WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
|
||||
while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
|
||||
udelay(2);
|
||||
|
||||
/* XXX */
|
||||
uart_update_timeout(port, cflag,
|
||||
(port->uartclk / (16 * quot)));
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
static const char *sc26xx_type(struct uart_port *port)
|
||||
{
|
||||
return "SC26XX";
|
||||
}
|
||||
|
||||
static void sc26xx_release_port(struct uart_port *port)
|
||||
{
|
||||
}
|
||||
|
||||
static int sc26xx_request_port(struct uart_port *port)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sc26xx_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
}
|
||||
|
||||
static int sc26xx_verify_port(struct uart_port *port, struct serial_struct *ser)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct uart_ops sc26xx_ops = {
|
||||
.tx_empty = sc26xx_tx_empty,
|
||||
.set_mctrl = sc26xx_set_mctrl,
|
||||
.get_mctrl = sc26xx_get_mctrl,
|
||||
.stop_tx = sc26xx_stop_tx,
|
||||
.start_tx = sc26xx_start_tx,
|
||||
.stop_rx = sc26xx_stop_rx,
|
||||
.enable_ms = sc26xx_enable_ms,
|
||||
.break_ctl = sc26xx_break_ctl,
|
||||
.startup = sc26xx_startup,
|
||||
.shutdown = sc26xx_shutdown,
|
||||
.set_termios = sc26xx_set_termios,
|
||||
.type = sc26xx_type,
|
||||
.release_port = sc26xx_release_port,
|
||||
.request_port = sc26xx_request_port,
|
||||
.config_port = sc26xx_config_port,
|
||||
.verify_port = sc26xx_verify_port,
|
||||
};
|
||||
|
||||
static struct uart_port *sc26xx_port;
|
||||
|
||||
#ifdef CONFIG_SERIAL_SC26XX_CONSOLE
|
||||
static void sc26xx_console_putchar(struct uart_port *port, char c)
|
||||
{
|
||||
unsigned long flags;
|
||||
int limit = 1000000;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
while (limit-- > 0) {
|
||||
if (READ_SC_PORT(port, SR) & SR_TXRDY) {
|
||||
WRITE_SC_PORT(port, THR, c);
|
||||
break;
|
||||
}
|
||||
udelay(2);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
static void sc26xx_console_write(struct console *con, const char *s, unsigned n)
|
||||
{
|
||||
struct uart_port *port = sc26xx_port;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < n; i++) {
|
||||
if (*s == '\n')
|
||||
sc26xx_console_putchar(port, '\r');
|
||||
sc26xx_console_putchar(port, *s++);
|
||||
}
|
||||
}
|
||||
|
||||
static int __init sc26xx_console_setup(struct console *con, char *options)
|
||||
{
|
||||
struct uart_port *port = sc26xx_port;
|
||||
int baud = 9600;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
|
||||
if (port->type != PORT_SC26XX)
|
||||
return -1;
|
||||
|
||||
printk(KERN_INFO "Console: ttySC%d (SC26XX)\n", con->index);
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
||||
return uart_set_options(port, con, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct uart_driver sc26xx_reg;
|
||||
static struct console sc26xx_console = {
|
||||
.name = "ttySC",
|
||||
.write = sc26xx_console_write,
|
||||
.device = uart_console_device,
|
||||
.setup = sc26xx_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &sc26xx_reg,
|
||||
};
|
||||
#define SC26XX_CONSOLE &sc26xx_console
|
||||
#else
|
||||
#define SC26XX_CONSOLE NULL
|
||||
#endif
|
||||
|
||||
static struct uart_driver sc26xx_reg = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = "SC26xx",
|
||||
.dev_name = "ttySC",
|
||||
.major = SC26XX_MAJOR,
|
||||
.minor = SC26XX_MINOR_START,
|
||||
.nr = SC26XX_NR,
|
||||
.cons = SC26XX_CONSOLE,
|
||||
};
|
||||
|
||||
static u8 sc26xx_flags2mask(unsigned int flags, unsigned int bitpos)
|
||||
{
|
||||
unsigned int bit = (flags >> bitpos) & 15;
|
||||
|
||||
return bit ? (1 << (bit - 1)) : 0;
|
||||
}
|
||||
|
||||
static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
|
||||
int line, unsigned int data)
|
||||
{
|
||||
up->dtr_mask[line] = sc26xx_flags2mask(data, 0);
|
||||
up->rts_mask[line] = sc26xx_flags2mask(data, 4);
|
||||
up->dsr_mask[line] = sc26xx_flags2mask(data, 8);
|
||||
up->cts_mask[line] = sc26xx_flags2mask(data, 12);
|
||||
up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
|
||||
up->ri_mask[line] = sc26xx_flags2mask(data, 20);
|
||||
}
|
||||
|
||||
static int __devinit sc26xx_probe(struct platform_device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct uart_sc26xx_port *up;
|
||||
unsigned int *sc26xx_data = dev->dev.platform_data;
|
||||
int err;
|
||||
|
||||
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
|
||||
up = kzalloc(sizeof *up, GFP_KERNEL);
|
||||
if (unlikely(!up))
|
||||
return -ENOMEM;
|
||||
|
||||
up->port[0].line = 0;
|
||||
up->port[0].ops = &sc26xx_ops;
|
||||
up->port[0].type = PORT_SC26XX;
|
||||
up->port[0].uartclk = (29491200 / 16); /* arbitrary */
|
||||
|
||||
up->port[0].mapbase = res->start;
|
||||
up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
|
||||
up->port[0].iotype = UPIO_MEM;
|
||||
up->port[0].irq = platform_get_irq(dev, 0);
|
||||
|
||||
up->port[0].dev = &dev->dev;
|
||||
|
||||
sc26xx_init_masks(up, 0, sc26xx_data[0]);
|
||||
|
||||
sc26xx_port = &up->port[0];
|
||||
|
||||
up->port[1].line = 1;
|
||||
up->port[1].ops = &sc26xx_ops;
|
||||
up->port[1].type = PORT_SC26XX;
|
||||
up->port[1].uartclk = (29491200 / 16); /* arbitrary */
|
||||
|
||||
up->port[1].mapbase = up->port[0].mapbase;
|
||||
up->port[1].membase = up->port[0].membase;
|
||||
up->port[1].iotype = UPIO_MEM;
|
||||
up->port[1].irq = up->port[0].irq;
|
||||
|
||||
up->port[1].dev = &dev->dev;
|
||||
|
||||
sc26xx_init_masks(up, 1, sc26xx_data[1]);
|
||||
|
||||
err = uart_register_driver(&sc26xx_reg);
|
||||
if (err)
|
||||
goto out_free_port;
|
||||
|
||||
sc26xx_reg.tty_driver->name_base = sc26xx_reg.minor;
|
||||
|
||||
err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
|
||||
if (err)
|
||||
goto out_unregister_driver;
|
||||
|
||||
err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
|
||||
if (err)
|
||||
goto out_remove_port0;
|
||||
|
||||
err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
|
||||
if (err)
|
||||
goto out_remove_ports;
|
||||
|
||||
dev_set_drvdata(&dev->dev, up);
|
||||
return 0;
|
||||
|
||||
out_remove_ports:
|
||||
uart_remove_one_port(&sc26xx_reg, &up->port[1]);
|
||||
out_remove_port0:
|
||||
uart_remove_one_port(&sc26xx_reg, &up->port[0]);
|
||||
|
||||
out_unregister_driver:
|
||||
uart_unregister_driver(&sc26xx_reg);
|
||||
|
||||
out_free_port:
|
||||
kfree(up);
|
||||
sc26xx_port = NULL;
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
static int __exit sc26xx_driver_remove(struct platform_device *dev)
|
||||
{
|
||||
struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);
|
||||
|
||||
free_irq(up->port[0].irq, up);
|
||||
|
||||
uart_remove_one_port(&sc26xx_reg, &up->port[0]);
|
||||
uart_remove_one_port(&sc26xx_reg, &up->port[1]);
|
||||
|
||||
uart_unregister_driver(&sc26xx_reg);
|
||||
|
||||
kfree(up);
|
||||
sc26xx_port = NULL;
|
||||
|
||||
dev_set_drvdata(&dev->dev, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sc26xx_driver = {
|
||||
.probe = sc26xx_probe,
|
||||
.remove = __devexit_p(sc26xx_driver_remove),
|
||||
.driver = {
|
||||
.name = "SC26xx",
|
||||
},
|
||||
};
|
||||
|
||||
static int __init sc26xx_init(void)
|
||||
{
|
||||
return platform_driver_register(&sc26xx_driver);
|
||||
}
|
||||
|
||||
static void __exit sc26xx_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sc26xx_driver);
|
||||
}
|
||||
|
||||
module_init(sc26xx_init);
|
||||
module_exit(sc26xx_exit);
|
||||
|
||||
|
||||
MODULE_AUTHOR("Thomas Bogendörfer");
|
||||
MODULE_DESCRIPTION("SC681/SC2692 serial driver");
|
||||
MODULE_VERSION("1.0");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user