ge_kernel.h

/* Copyright (C) 2011, 2012 The uOFW team
   See the file COPYING for copying permission.
*/
 
#include "common_header.h"
#include "ge_user.h"
 
typedef enum
{
    SCE_GE_DL_STATE_NONE = 0,
    SCE_GE_DL_STATE_QUEUED, // 1
    SCE_GE_DL_STATE_RUNNING, // 2
    SCE_GE_DL_STATE_COMPLETED, // 3
    SCE_GE_DL_STATE_PAUSED // 4
} SceGeDisplayListState;
 
typedef enum
{
    SCE_GE_DL_SIGNAL_NONE = 0,
    SCE_GE_DL_SIGNAL_BREAK, // 1
    SCE_GE_DL_SIGNAL_PAUSE, // 2
    SCE_GE_DL_SIGNAL_SYNC // 3
} SceGeDisplayListSignal;
 
typedef struct SceGeDisplayList
{
    struct SceGeDisplayList *next; // 0
    struct SceGeDisplayList *prev; // 4
    u8 state; // SceGeDisplayListState / 8
    u8 signal; // SceGeDisplayListSignal / 9
    u8 isBusy;
    /* (padding) */
    char unused11;
    SceGeContext *ctx; // 12
    int execState;
    void *list; // 20
    void *stall; // 24
    int radr1; // 28
    int radr2; // 32
    int oadr; // 36
    int oadr1; // 40
    int oadr2; // 44
    int base; // 48
    short cbId; // 52
    u16 signalData;
    short numStacks; // 56
    u16 stackOff; // 58
    SceGeStack *stack; // 60
} SceGeDisplayList; // size: 64
 
typedef struct
{
    u32 exec; // 0
    u32 ladr; // 4
    u32 sadr; // 8
    u32 radr1; // 12
    u32 radr2; // 16
    u32 vadr; // 20
    u32 iadr; // 24
    u32 oadr; // 28
    u32 oadr1; // 32
    u32 oadr2; // 36
    u32 edramTransDisable; // 40
    u32 edramTransVal; // 44
    u32 edramRefresh1; // 48
    u32 edramRefresh2; // 52
    u32 edramRefresh3; // 56
    u32 edramUnk40; // 60
    u32 geometryClock; // 64
    u32 dl[495]; // 68
} _SceGeContext;
 
int sceGeInit();
 
int sceGeEnd();
 
typedef enum SceGeReg {
    SCE_GE_REG_RESET = 0,
    SCE_GE_REG_UNK004 = 1,
    SCE_GE_REG_EDRAM_HW_SIZE = 2,
    SCE_GE_REG_EXEC = 3,
    SCE_GE_REG_UNK104 = 4,
    SCE_GE_REG_LISTADDR = 5,
    SCE_GE_REG_STALLADDR = 6,
    SCE_GE_REG_RADR1 = 7,
    SCE_GE_REG_RADR2 = 8,
    SCE_GE_REG_VADR = 9,
    SCE_GE_REG_IADR = 10,
    SCE_GE_REG_OADR = 11,
    SCE_GE_REG_OADR1 = 12,
    SCE_GE_REG_OADR2 = 13,
    SCE_GE_REG_UNK300 = 14,
    SCE_GE_REG_INTERRUPT_TYPE1 = 15,
    SCE_GE_REG_INTERRUPT_TYPE2 = 16,
    SCE_GE_REG_INTERRUPT_TYPE3 = 17,
    SCE_GE_REG_INTERRUPT_TYPE4 = 18,
    SCE_GE_REG_EDRAM_ENABLED_SIZE = 19,
    SCE_GE_REG_GEOMETRY_CLOCK = 20,
    SCE_GE_REG_EDRAM_REFRESH_UNK1 = 21,
    SCE_GE_REG_EDRAM_UNK10 = 22,
    SCE_GE_REG_EDRAM_REFRESH_UNK2 = 23,
    SCE_GE_REG_EDRAM_REFRESH_UNK3 = 24,
    SCE_GE_REG_EDRAM_UNK40 = 25,
    SCE_GE_REG_EDRAM_UNK50 = 26,
    SCE_GE_REG_EDRAM_UNK60 = 27,
    SCE_GE_REG_EDRAM_ADDR_TRANS_DISABLE = 28,
    SCE_GE_REG_EDRAM_ADDR_TRANS_VALUE = 29,
    SCE_GE_REG_EDRAM_UNK90 = 30,
    SCE_GE_REG_EDRAM_UNKA0 = 31
} SceGeReg;
 
int sceGeGetReg(SceGeReg regId);
 
int sceGeSetReg(SceGeReg regId, u32 value);
 
int sceGeSetCmd(u32 cmdOff, u32 cmd);
 
int sceGeSetMtx(int id, int *mtx);
 
typedef enum SceGeLogType {
    SCE_GE_LOG_DL_ENQUEUED = 0,
    SCE_GE_LOG_DL_DEQUEUED = 1,
    SCE_GE_LOG_DL_SADR_UPDATE = 2,
    SCE_GE_LOG_DL_BREAK = 3,
    SCE_GE_LOG_DL_CONTINUE = 4,
    SCE_GE_LOG_DL_RUNNING = 5,
    SCE_GE_LOG_DL_END = 6,
    SCE_GE_LOG_DL_SIGNAL = 7,
} SceGeLogType;
 
typedef void (*SceGeLogHandler)(SceGeLogType logType, ...);
 
int sceGeRegisterLogHandler(SceGeLogHandler handler);
 
int sceGeSetGeometryClock(int opt);
 
int sceGeEdramInit();
 
int sceGeEdramSetRefreshParam(int arg0, int arg1, int arg2, int arg3);
 
int sceGeEdramSetSize(int size);
 
int sceGeEdramGetHwSize();
 
typedef struct SceGeBreakpoint {
    u32 bpAddr;
    int bpCount;
} SceGeBreakpoint;
 
int sceGePutBreakpoint(SceGeBreakpoint *bp, int size);
 
int sceGeGetBreakpoint(SceGeBreakpoint *bp, int size, int *arg2);
 
int sceGeGetListIdList(int *outPtr, int size, int *totalCountPtr);
 
int sceGeGetList(int dlId, SceGeDisplayList *outDl, int *outFlag);