mirror of
https://github.com/libretro/FBNeo.git
synced 2024-11-27 11:00:27 +00:00
add m377 series mcu for iq_132
This commit is contained in:
dinkc64
parent
f75fc5994d
commit
5784cc87a2
@ -1,7 +1,7 @@
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alldir = burn burn/devices burn/snd burn/drv burn/drv/atari burn/drv/capcom burn/drv/cave burn/drv/coleco burn/drv/cps3 burn/drv/dataeast \
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burn/drv/galaxian burn/drv/irem burn/drv/konami burn/drv/megadrive burn/drv/midway burn/drv/pce burn/drv/pst90s burn/drv/pre90s burn/drv/neogeo burn/drv/nes \
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burn/drv/pgm burn/drv/psikyo burn/drv/sega burn/drv/sg1000 burn/drv/sms burn/drv/msx burn/drv/spectrum burn/drv/taito \
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burn/drv/toaplan cpu cpu/a68k cpu/arm cpu/arm7 cpu/e132xs cpu/h6280 cpu/hd6309 cpu/i8039 cpu/i8x41 cpu/i8051 cpu/adsp2100 cpu/konami cpu/mips3 cpu/m68k \
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burn/drv/toaplan cpu cpu/a68k cpu/arm cpu/arm7 cpu/e132xs cpu/h6280 cpu/hd6309 cpu/i8039 cpu/i8x41 cpu/i8051 cpu/adsp2100 cpu/konami cpu/m377 cpu/mips3 cpu/m68k \
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cpu/m6502 cpu/m6800 cpu/m6805 cpu/m6809 cpu/nec cpu/pic16c5x cpu/s2650 cpu/tlcs90 cpu/tlcs900 cpu/sh2 cpu/tms32010 cpu/tms34 cpu/upd7725 cpu/upd7810 \
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cpu/v60 cpu/z80 cpu/z180
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@ -114,7 +114,7 @@ depobj = burn.o burn_bitmap.o burn_gun.o burn_led.o burn_shift.o burn_memory.o
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m68000_intf.o mips3_intf.o nec_intf.o pic16c5x_intf.o s2650_intf.o tlcs90_intf.o tms34010.o tms34_intf.o z80_intf.o \
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z180_intf.o \
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\
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arm.o arm7.o e132xs.o h6280.o hd6309.o i8039.o mcs48.o mcs51.o konami.o m6502.o m6800.o m6805.o m6809.o nec.o pic16c5x.o s2650.o sh2.o tms32010.o tlcs90.o tlcs900.o \
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arm.o arm7.o e132xs.o h6280.o hd6309.o i8039.o m37710.o mcs48.o mcs51.o konami.o m6502.o m6800.o m6805.o m6809.o nec.o pic16c5x.o s2650.o sh2.o tms32010.o tlcs90.o tlcs900.o \
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upd7725.o upd7810.o v25.o v60.o z80.o z80daisy.o z80ctc.o z80pio.o z180.o \
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\
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cop0.o cop1.o mips3.o \
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1382
src/cpu/m377/m37710.cpp
Normal file
1382
src/cpu/m377/m37710.cpp
Normal file
File diff suppressed because it is too large
Load Diff
87
src/cpu/m377/m37710.h
Normal file
87
src/cpu/m377/m37710.h
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@ -0,0 +1,87 @@
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#ifndef __M37710_H__
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#define __M37710_H__
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/* ======================================================================== */
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/* =============================== COPYRIGHT ============================== */
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/* ======================================================================== */
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/*
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M37710 CPU Emulator v0.1
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*/
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/* ======================================================================== */
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/* =============================== DEFINES ================================ */
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/* ======================================================================== */
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/*
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Input lines - used with cpunum_set_input_line() and the like.
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WARNING: these are in the same order as the vector table for simplicity.
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Do not alter this order!
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*/
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enum
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{
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// these interrupts are maskable
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M37710_LINE_ADC = 0,
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M37710_LINE_UART1XMIT,
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M37710_LINE_UART1RECV,
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M37710_LINE_UART0XMIT,
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M37710_LINE_UART0RECV,
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M37710_LINE_TIMERB2,
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M37710_LINE_TIMERB1,
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M37710_LINE_TIMERB0,
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M37710_LINE_TIMERA4,
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M37710_LINE_TIMERA3,
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M37710_LINE_TIMERA2,
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M37710_LINE_TIMERA1,
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M37710_LINE_TIMERA0,
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M37710_LINE_IRQ2,
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M37710_LINE_IRQ1,
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M37710_LINE_IRQ0,
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// these interrupts are non-maskable
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M37710_LINE_WATCHDOG,
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M37710_LINE_DEBUG,
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M37710_LINE_BRK,
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M37710_LINE_ZERODIV,
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M37710_LINE_RESET,
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// these are not interrupts, they're signals external hardware can send
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M37710_LINE_TIMERA0TICK,
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M37710_LINE_TIMERA1TICK,
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M37710_LINE_TIMERA2TICK,
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M37710_LINE_TIMERA3TICK,
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M37710_LINE_TIMERA4TICK,
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M37710_LINE_TIMERB0TICK,
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M37710_LINE_TIMERB1TICK,
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M37710_LINE_TIMERB2TICK,
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M37710_LINE_MAX
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};
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/* Registers - used by m37710_set_reg() and m37710_get_reg() */
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enum
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{
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M37710_PC=1, M37710_S, M37710_P, M37710_A, M37710_B, M37710_X, M37710_Y,
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M37710_PB, M37710_DB, M37710_D, M37710_E,
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M37710_NMI_STATE, M37710_IRQ_STATE, STATE_GENPCBASE
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};
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/* I/O ports */
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enum
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{
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M37710_PORT0 = 0,
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M37710_PORT1, M37710_PORT2, M37710_PORT3, M37710_PORT4,
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M37710_PORT5, M37710_PORT6, M37710_PORT7, M37710_PORT8,
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M37710_ADC0_L = 0x10, M37710_ADC0_H,
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M37710_ADC1_L, M37710_ADC1_H, M37710_ADC2_L, M37710_ADC2_H, M37710_ADC3_L, M37710_ADC3_H,
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M37710_ADC4_L, M37710_ADC4_H, M37710_ADC5_L, M37710_ADC5_H, M37710_ADC6_L, M37710_ADC6_H,
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M37710_ADC7_L, M37710_ADC7_H,
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M37710_SER0_REC = 0x20,
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M37710_SER0_XMIT, M37710_SER1_REC, M37710_SER1_XMIT
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};
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#endif /* __M37710_H__ */
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405
src/cpu/m377/m37710cm.h
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405
src/cpu/m377/m37710cm.h
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@ -0,0 +1,405 @@
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#pragma once
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#ifndef __M37710CM_H__
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#define __M37710CM_H__
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/* ======================================================================== */
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/* ================================ INCLUDES ============================== */
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/* ======================================================================== */
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#include <limits.h>
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#include "m37710.h"
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/* ======================================================================== */
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/* ================================= MAME ================================= */
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/* ======================================================================== */
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#define m37710_read_8(addr) program_read_byte_16le(addr)
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#define m37710_write_8(addr,data) program_write_byte_16le(addr,data)
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#define m37710_read_8_immediate(A) program_read_byte_16le(A)
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#define m37710_read_16(addr) program_read_word_16le(addr)
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#define m37710_write_16(addr,data) program_write_word_16le(addr,data)
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#define m37710_read_16_immediate(A) program_read_word_16le(A)
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/* ======================================================================== */
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/* ================================ GENERAL =============================== */
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/* ======================================================================== */
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#undef int8
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/* Allow for architectures that don't have 8-bit sizes */
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#if UCHAR_MAX == 0xff
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#define int8 char
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#define MAKE_INT_8(A) (int8)((A)&0xff)
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#else
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#define int8 int
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INLINE int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;}
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#endif /* UCHAR_MAX == 0xff */
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#define MAKE_UINT_8(A) ((A)&0xff)
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#define MAKE_UINT_16(A) ((A)&0xffff)
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#define MAKE_UINT_24(A) ((A)&0xffffff)
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/* Bits */
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#define BIT_0 0x01
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#define BIT_1 0x02
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#define BIT_2 0x04
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#define BIT_3 0x08
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#define BIT_4 0x10
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#define BIT_5 0x20
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#define BIT_6 0x40
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#define BIT_7 0x80
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/* ======================================================================== */
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/* ================================== CPU ================================= */
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/* ======================================================================== */
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#define REG_A m377.a /* Accumulator */
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#define REG_B m377.b /* Accumulator hi byte */
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#define REG_BA m377.ba /* Secondary Accumulator */
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#define REG_BB m377.bb /* Secondary Accumulator hi byte */
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#define REG_X m377.x /* Index X Register */
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#define REG_Y m377.y /* Index Y Register */
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#define REG_XH m377.xh /* X high byte */
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#define REG_YH m377.yh /* Y high byte */
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#define REG_S m377.s /* Stack Pointer */
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#define REG_PC m377.pc /* Program Counter */
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#define REG_PPC m377.ppc /* Previous Program Counter */
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#define REG_PB m377.pb /* Program Bank */
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#define REG_DB m377.db /* Data Bank */
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#define REG_D m377.d /* Direct Register */
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#define FLAG_M m377.flag_m /* Memory/Accumulator Select Flag */
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#define FLAG_X m377.flag_x /* Index Select Flag */
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#define FLAG_N m377.flag_n /* Negative Flag */
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#define FLAG_V m377.flag_v /* Overflow Flag */
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#define FLAG_D m377.flag_d /* Decimal Mode Flag */
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#define FLAG_I m377.flag_i /* Interrupt Mask Flag */
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#define FLAG_Z m377.flag_z /* Zero Flag (inverted) */
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#define FLAG_C m377.flag_c /* Carry Flag */
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#define LINE_IRQ m377.line_irq /* Status of the IRQ line */
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#define REG_IR m377.ir /* Instruction Register */
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#define REG_IM m377.im /* Immediate load value */
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#define REG_IM2 m377.im2 /* Immediate load target */
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#define REG_IM3 m377.im3 /* Immediate load target */
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#define REG_IM4 m377.im4 /* Immediate load target */
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#define INT_ACK m377.int_ack /* Interrupt Acknowledge function pointer */
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#define CLOCKS m377.ICount /* Clock cycles remaining */
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#define IRQ_DELAY m377.irq_delay /* Delay 1 instruction before checking IRQ */
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#define CPU_STOPPED m377.stopped /* Stopped status of the CPU */
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#define FTABLE_GET_REG m_get_reg
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#define FTABLE_SET_REG m_set_reg
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#define FTABLE_SET_LINE m_set_line
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#define SRC m377.source /* Source Operand */
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#define DST m377.destination /* Destination Operand */
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#define STOP_LEVEL_WAI 1
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#define STOP_LEVEL_STOP 2
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#define EXECUTION_MODE_M0X0 0
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#define EXECUTION_MODE_M0X1 1
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#define EXECUTION_MODE_M1X0 2
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#define EXECUTION_MODE_M1X1 3
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/* ======================================================================== */
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/* ================================= CLOCK ================================ */
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/* ======================================================================== */
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#define CLK_OP 1
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#define CLK_R8 1
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#define CLK_R16 2
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#define CLK_R24 3
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#define CLK_W8 1
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#define CLK_W16 2
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#define CLK_W24 3
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#define CLK_RMW8 3
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#define CLK_RMW16 5
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#define CLK_IMPLIED 1
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#define CLK_IMPLIED 1
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#define CLK_RELATIVE_8 1
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#define CLK_RELATIVE_16 2
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#define CLK_IMM 0
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#define CLK_AI 4
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#define CLK_AXI 4
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#define CLK_A 2
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#define CLK_AL 3
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#define CLK_ALX 3
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#define CLK_AX 2
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#define CLK_AY 2
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#define CLK_D 1
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#define CLK_DI 3
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#define CLK_DIY 3
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#define CLK_DLI 4
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#define CLK_DLIY 4
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#define CLK_DX 2
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#define CLK_DXI 4
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#define CLK_DY 2
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#define CLK_S 2
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#define CLK_SIY 5
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/* AX and AY addressing modes take 1 extra cycle when writing */
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#define CLK_W_IMM 0
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#define CLK_W_AI 4
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#define CLK_W_AXI 4
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#define CLK_W_A 2
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#define CLK_W_AL 3
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#define CLK_W_ALX 3
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#define CLK_W_AX 3
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#define CLK_W_AY 3
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#define CLK_W_D 1
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#define CLK_W_DI 3
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#define CLK_W_DIY 3
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#define CLK_W_DLI 4
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#define CLK_W_DLIY 4
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#define CLK_W_DX 2
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#define CLK_W_DXI 4
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#define CLK_W_DY 2
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#define CLK_W_S 2
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#define CLK_W_SIY 5
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#define CLK(A) do { CLOCKS -= (A); m37710_clock_timers(A); } while (0)
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#define USE_ALL_CLKS() do { m37710_clock_timers(CLOCKS); CLOCKS = 0; } while (0)
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/* ======================================================================== */
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/* ============================ STATUS REGISTER =========================== */
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/* ======================================================================== */
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/* Flag positions in Processor Status Register */
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/* common */
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#define FLAGPOS_N BIT_7 /* Negative */
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#define FLAGPOS_V BIT_6 /* Overflow */
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#define FLAGPOS_D BIT_3 /* Decimal Mode */
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#define FLAGPOS_I BIT_2 /* Interrupt Mask */
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#define FLAGPOS_Z BIT_1 /* Zero */
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#define FLAGPOS_C BIT_0 /* Carry */
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/* emulation */
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#define FLAGPOS_R BIT_5 /* Reserved */
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#define FLAGPOS_B BIT_4 /* BRK Instruction */
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/* native */
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#define FLAGPOS_M BIT_5 /* Mem/Reg Select */
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#define FLAGPOS_X BIT_4 /* Index Select */
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#define EFLAG_SET 1
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#define EFLAG_CLEAR 0
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#define MFLAG_SET FLAGPOS_M
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#define MFLAG_CLEAR 0
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#define XFLAG_SET FLAGPOS_X
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#define XFLAG_CLEAR 0
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#define NFLAG_SET 0x80
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#define NFLAG_CLEAR 0
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#define VFLAG_SET 0x80
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#define VFLAG_CLEAR 0
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#define DFLAG_SET FLAGPOS_D
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#define DFLAG_CLEAR 0
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#define IFLAG_SET FLAGPOS_I
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#define IFLAG_CLEAR 0
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#define BFLAG_SET FLAGPOS_B
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#define BFLAG_CLEAR 0
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#define ZFLAG_SET 0
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#define ZFLAG_CLEAR 1
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#define CFLAG_SET 0x100
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#define CFLAG_CLEAR 0
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/* Codition code tests */
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#define COND_CC() (!(FLAG_C&0x100)) /* Carry Clear */
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#define COND_CS() (FLAG_C&0x100) /* Carry Set */
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#define COND_EQ() (!FLAG_Z) /* Equal */
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#define COND_NE() FLAG_Z /* Not Equal */
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#define COND_MI() (FLAG_N&0x80) /* Minus */
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#define COND_PL() (!(FLAG_N&0x80)) /* Plus */
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#define COND_VC() (!(FLAG_V&0x80)) /* Overflow Clear */
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#define COND_VS() (FLAG_V&0x80) /* Overflow Set */
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/* Set Overflow flag in math operations */
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#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R))
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#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8)
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#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D))
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#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8)
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#define CFLAG_8(A) (A)
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#define CFLAG_16(A) ((A)>>8)
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#define NFLAG_8(A) (A)
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#define NFLAG_16(A) ((A)>>8)
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#define CFLAG_AS_1() ((FLAG_C>>8)&1)
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/* ======================================================================== */
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/* ========================== EFFECTIVE ADDRESSES ========================= */
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/* ======================================================================== */
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/* Effective-address based memory access macros */
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#define read_8_NORM(A) m37710i_read_8_normal(A)
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#define read_8_IMM(A) m37710i_read_8_immediate(A)
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#define read_8_D(A) m37710i_read_8_direct(A)
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#define read_8_A(A) m37710i_read_8_normal(A)
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#define read_8_AL(A) m37710i_read_8_normal(A)
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#define read_8_DX(A) m37710i_read_8_direct(A)
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#define read_8_DY(A) m37710i_read_8_direct(A)
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#define read_8_AX(A) m37710i_read_8_normal(A)
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#define read_8_ALX(A) m37710i_read_8_normal(A)
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#define read_8_AY(A) m37710i_read_8_normal(A)
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#define read_8_DI(A) m37710i_read_8_normal(A)
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#define read_8_DLI(A) m37710i_read_8_normal(A)
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#define read_8_AI(A) m37710i_read_8_normal(A)
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#define read_8_ALI(A) m37710i_read_8_normal(A)
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#define read_8_DXI(A) m37710i_read_8_normal(A)
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#define read_8_DIY(A) m37710i_read_8_normal(A)
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#define read_8_DLIY(A) m37710i_read_8_normal(A)
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#define read_8_AXI(A) m37710i_read_8_normal(A)
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#define read_8_S(A) m37710i_read_8_normal(A)
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#define read_8_SIY(A) m37710i_read_8_normal(A)
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#define read_16_NORM(A) m37710i_read_16_normal(A)
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#define read_16_IMM(A) m37710i_read_16_immediate(A)
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#define read_16_D(A) m37710i_read_16_direct(A)
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#define read_16_A(A) m37710i_read_16_normal(A)
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#define read_16_AL(A) m37710i_read_16_normal(A)
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#define read_16_DX(A) m37710i_read_16_direct(A)
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#define read_16_DY(A) m37710i_read_16_direct(A)
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#define read_16_AX(A) m37710i_read_16_normal(A)
|
||||
#define read_16_ALX(A) m37710i_read_16_normal(A)
|
||||
#define read_16_AY(A) m37710i_read_16_normal(A)
|
||||
#define read_16_DI(A) m37710i_read_16_normal(A)
|
||||
#define read_16_DLI(A) m37710i_read_16_normal(A)
|
||||
#define read_16_AI(A) m37710i_read_16_normal(A)
|
||||
#define read_16_ALI(A) m37710i_read_16_normal(A)
|
||||
#define read_16_DXI(A) m37710i_read_16_normal(A)
|
||||
#define read_16_DIY(A) m37710i_read_16_normal(A)
|
||||
#define read_16_DLIY(A) m37710i_read_16_normal(A)
|
||||
#define read_16_AXI(A) m37710i_read_16_normal(A)
|
||||
#define read_16_S(A) m37710i_read_16_normal(A)
|
||||
#define read_16_SIY(A) m37710i_read_16_normal(A)
|
||||
|
||||
#define read_24_NORM(A) m37710i_read_24_normal(A)
|
||||
#define read_24_IMM(A) m37710i_read_24_immediate(A)
|
||||
#define read_24_D(A) m37710i_read_24_direct(A)
|
||||
#define read_24_A(A) m37710i_read_24_normal(A)
|
||||
#define read_24_AL(A) m37710i_read_24_normal(A)
|
||||
#define read_24_DX(A) m37710i_read_24_direct(A)
|
||||
#define read_24_DY(A) m37710i_read_24_direct(A)
|
||||
#define read_24_AX(A) m37710i_read_24_normal(A)
|
||||
#define read_24_ALX(A) m37710i_read_24_normal(A)
|
||||
#define read_24_AY(A) m37710i_read_24_normal(A)
|
||||
#define read_24_DI(A) m37710i_read_24_normal(A)
|
||||
#define read_24_DLI(A) m37710i_read_24_normal(A)
|
||||
#define read_24_AI(A) m37710i_read_24_normal(A)
|
||||
#define read_24_ALI(A) m37710i_read_24_normal(A)
|
||||
#define read_24_DXI(A) m37710i_read_24_normal(A)
|
||||
#define read_24_DIY(A) m37710i_read_24_normal(A)
|
||||
#define read_24_DLIY(A) m37710i_read_24_normal(A)
|
||||
#define read_24_AXI(A) m37710i_read_24_normal(A)
|
||||
#define read_24_S(A) m37710i_read_24_normal(A)
|
||||
#define read_24_SIY(A) m37710i_read_24_normal(A)
|
||||
|
||||
#define write_8_NORM(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_D(A, V) m37710i_write_8_direct(A, V)
|
||||
#define write_8_A(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_AL(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_DX(A, V) m37710i_write_8_direct(A, V)
|
||||
#define write_8_DY(A, V) m37710i_write_8_direct(A, V)
|
||||
#define write_8_AX(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_ALX(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_AY(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_DI(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_DLI(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_AI(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_ALI(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_DXI(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_DIY(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_DLIY(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_AXI(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_S(A, V) m37710i_write_8_normal(A, V)
|
||||
#define write_8_SIY(A, V) m37710i_write_8_normal(A, V)
|
||||
|
||||
#define write_16_NORM(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_D(A, V) m37710i_write_16_direct(A, V)
|
||||
#define write_16_A(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_AL(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_DX(A, V) m37710i_write_16_direct(A, V)
|
||||
#define write_16_DY(A, V) m37710i_write_16_direct(A, V)
|
||||
#define write_16_AX(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_ALX(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_AY(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_DI(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_DLI(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_AI(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_ALI(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_DXI(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_DIY(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_DLIY(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_AXI(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_S(A, V) m37710i_write_16_normal(A, V)
|
||||
#define write_16_SIY(A, V) m37710i_write_16_normal(A, V)
|
||||
|
||||
|
||||
#define OPER_8_IMM() read_8_IMM(EA_IMM8())
|
||||
#define OPER_8_D() read_8_D(EA_D())
|
||||
#define OPER_8_A() read_8_A(EA_A())
|
||||
#define OPER_8_AL() read_8_AL(EA_AL())
|
||||
#define OPER_8_DX() read_8_DX(EA_DX())
|
||||
#define OPER_8_DY() read_8_DY(EA_DY())
|
||||
#define OPER_8_AX() read_8_AX(EA_AX())
|
||||
#define OPER_8_ALX() read_8_ALX(EA_ALX())
|
||||
#define OPER_8_AY() read_8_AY(EA_AY())
|
||||
#define OPER_8_DI() read_8_DI(EA_DI())
|
||||
#define OPER_8_DLI() read_8_DLI(EA_DLI())
|
||||
#define OPER_8_AI() read_8_AI(EA_AI())
|
||||
#define OPER_8_ALI() read_8_ALI(EA_ALI())
|
||||
#define OPER_8_DXI() read_8_DXI(EA_DXI())
|
||||
#define OPER_8_DIY() read_8_DIY(EA_DIY())
|
||||
#define OPER_8_DLIY() read_8_DLIY(EA_DLIY())
|
||||
#define OPER_8_AXI() read_8_AXI(EA_AXI())
|
||||
#define OPER_8_S() read_8_S(EA_S())
|
||||
#define OPER_8_SIY() read_8_SIY(EA_SIY())
|
||||
|
||||
#define OPER_16_IMM() read_16_IMM(EA_IMM16())
|
||||
#define OPER_16_D() read_16_D(EA_D())
|
||||
#define OPER_16_A() read_16_A(EA_A())
|
||||
#define OPER_16_AL() read_16_AL(EA_AL())
|
||||
#define OPER_16_DX() read_16_DX(EA_DX())
|
||||
#define OPER_16_DY() read_16_DY(EA_DY())
|
||||
#define OPER_16_AX() read_16_AX(EA_AX())
|
||||
#define OPER_16_ALX() read_16_ALX(EA_ALX())
|
||||
#define OPER_16_AY() read_16_AY(EA_AY())
|
||||
#define OPER_16_DI() read_16_DI(EA_DI())
|
||||
#define OPER_16_DLI() read_16_DLI(EA_DLI())
|
||||
#define OPER_16_AI() read_16_AI(EA_AI())
|
||||
#define OPER_16_ALI() read_16_ALI(EA_ALI())
|
||||
#define OPER_16_DXI() read_16_DXI(EA_DXI())
|
||||
#define OPER_16_DIY() read_16_DIY(EA_DIY())
|
||||
#define OPER_16_DLIY() read_16_DLIY(EA_DLIY())
|
||||
#define OPER_16_AXI() read_16_AXI(EA_AXI())
|
||||
#define OPER_16_S() read_16_S(EA_S())
|
||||
#define OPER_16_SIY() read_16_SIY(EA_SIY())
|
||||
|
||||
#define OPER_24_IMM() read_24_IMM(EA_IMM24())
|
||||
#define OPER_24_D() read_24_D(EA_D())
|
||||
#define OPER_24_A() read_24_A(EA_A())
|
||||
#define OPER_24_AL() read_24_AL(EA_AL())
|
||||
#define OPER_24_DX() read_24_DX(EA_DX())
|
||||
#define OPER_24_DY() read_24_DY(EA_DY())
|
||||
#define OPER_24_AX() read_24_AX(EA_AX())
|
||||
#define OPER_24_ALX() read_24_ALX(EA_ALX())
|
||||
#define OPER_24_AY() read_24_AY(EA_AY())
|
||||
#define OPER_24_DI() read_24_DI(EA_DI())
|
||||
#define OPER_24_DLI() read_24_DLI(EA_DLI())
|
||||
#define OPER_24_AI() read_24_AI(EA_AI())
|
||||
#define OPER_24_ALI() read_24_ALI(EA_ALI())
|
||||
#define OPER_24_DXI() read_24_DXI(EA_DXI())
|
||||
#define OPER_24_DIY() read_24_DIY(EA_DIY())
|
||||
#define OPER_24_DLIY() read_24_DLIY(EA_DLIY())
|
||||
#define OPER_24_AXI() read_24_AXI(EA_AXI())
|
||||
#define OPER_24_S() read_24_S(EA_S())
|
||||
#define OPER_24_SIY() read_24_SIY(EA_SIY())
|
||||
|
||||
/* ======================================================================== */
|
||||
/* ================================== CPU ================================= */
|
||||
/* ======================================================================== */
|
||||
#endif /* __M37710CM_H__ */
|
||||
206
src/cpu/m377/m37710il.h
Normal file
206
src/cpu/m377/m37710il.h
Normal file
@ -0,0 +1,206 @@
|
||||
#pragma once
|
||||
|
||||
#ifndef __M37710IL_H__
|
||||
#define __M37710IL_H__
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* ================================= MEMORY =============================== */
|
||||
/* ======================================================================== */
|
||||
|
||||
inline UINT32 m37710i_read_8_normal(UINT32 address)
|
||||
{
|
||||
return m37710_read_8(address);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_read_8_immediate(UINT32 address)
|
||||
{
|
||||
return m37710_read_8_immediate(address);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_read_8_direct(UINT32 address)
|
||||
{
|
||||
return m37710_read_8(address);
|
||||
}
|
||||
|
||||
inline void m37710i_write_8_normal(UINT32 address, UINT32 value)
|
||||
{
|
||||
m37710_write_8(address, value);
|
||||
}
|
||||
|
||||
inline void m37710i_write_8_direct(UINT32 address, UINT32 value)
|
||||
{
|
||||
m37710_write_8(address, value);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_read_16_normal(UINT32 address)
|
||||
{
|
||||
return m37710_read_16(address);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_read_16_immediate(UINT32 address)
|
||||
{
|
||||
if (address & 1)
|
||||
return m37710_read_8_immediate(address) | (m37710_read_8_immediate(address+1)<<8);
|
||||
else
|
||||
return m37710_read_16_immediate(address);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_read_16_direct(UINT32 address)
|
||||
{
|
||||
return m37710_read_16(address);
|
||||
}
|
||||
|
||||
inline void m37710i_write_16_normal(UINT32 address, UINT32 value)
|
||||
{
|
||||
m37710_write_16(address, value);
|
||||
}
|
||||
|
||||
inline void m37710i_write_16_direct(UINT32 address, UINT32 value)
|
||||
{
|
||||
m37710_write_16(address, value);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_read_24_normal(UINT32 address)
|
||||
{
|
||||
if (address & 1)
|
||||
return m37710_read_8(address) | (m37710_read_16(address+1)<<8);
|
||||
else
|
||||
return m37710_read_16(address) | (m37710_read_8(address+2)<<16);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_read_24_immediate(UINT32 address)
|
||||
{
|
||||
if (address & 1)
|
||||
return m37710_read_8_immediate(address) | (m37710_read_16_immediate(address+1)<<8);
|
||||
else
|
||||
return m37710_read_16_immediate(address) | (m37710_read_8_immediate(address+2)<<16);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_read_24_direct(UINT32 address)
|
||||
{
|
||||
if (address & 1)
|
||||
return m37710_read_8(address) | (m37710_read_16(address+1)<<8);
|
||||
else
|
||||
return m37710_read_16(address) | (m37710_read_8(address+2)<<16);
|
||||
}
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* ================================= STACK ================================ */
|
||||
/* ======================================================================== */
|
||||
|
||||
inline void m37710i_push_8(UINT32 value)
|
||||
{
|
||||
m37710_write_8(REG_S, value);
|
||||
REG_S = MAKE_UINT_16(REG_S-1);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_pull_8()
|
||||
{
|
||||
REG_S = MAKE_UINT_16(REG_S+1);
|
||||
return m37710_read_8(REG_S);
|
||||
}
|
||||
|
||||
inline void m37710i_push_16(UINT32 value)
|
||||
{
|
||||
m37710i_push_8(value>>8);
|
||||
m37710i_push_8(value);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_pull_16()
|
||||
{
|
||||
UINT32 res = m37710i_pull_8();
|
||||
return res | (m37710i_pull_8() << 8);
|
||||
}
|
||||
|
||||
inline void m37710i_push_24(UINT32 value)
|
||||
{
|
||||
m37710i_push_8(value>>16);
|
||||
m37710i_push_8((value>>8));
|
||||
m37710i_push_8(value);
|
||||
}
|
||||
|
||||
inline UINT32 m37710i_pull_24()
|
||||
{
|
||||
UINT32 res = m37710i_pull_8();
|
||||
res |= m37710i_pull_8() << 8;
|
||||
return res | (m37710i_pull_8() << 16);
|
||||
}
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* ============================ PROGRAM COUNTER =========================== */
|
||||
/* ======================================================================== */
|
||||
|
||||
inline void m37710i_jump_16(UINT32 address)
|
||||
{
|
||||
REG_PC = MAKE_UINT_16(address);
|
||||
}
|
||||
|
||||
inline void m37710i_jump_24(UINT32 address)
|
||||
{
|
||||
REG_PB = address&0xff0000;
|
||||
REG_PC = MAKE_UINT_16(address);
|
||||
}
|
||||
|
||||
inline void m37710i_branch_8(UINT32 offset)
|
||||
{
|
||||
REG_PC = MAKE_UINT_16(REG_PC + MAKE_INT_8(offset));
|
||||
}
|
||||
|
||||
inline void m37710i_branch_16(UINT32 offset)
|
||||
{
|
||||
REG_PC = MAKE_UINT_16(REG_PC + offset);
|
||||
}
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* ============================ STATUS REGISTER =========================== */
|
||||
/* ======================================================================== */
|
||||
|
||||
inline UINT32 m37710i_get_reg_p()
|
||||
{
|
||||
return (FLAG_N&0x80) |
|
||||
((FLAG_V>>1)&0x40) |
|
||||
FLAG_M |
|
||||
FLAG_X |
|
||||
FLAG_D |
|
||||
FLAG_I |
|
||||
((!FLAG_Z)<<1) |
|
||||
((FLAG_C>>8)&1);
|
||||
}
|
||||
|
||||
inline void m37710i_set_reg_ipl(UINT32 value)
|
||||
{
|
||||
m377.ipl = value & 7;
|
||||
}
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* ============================= ADDRESS MODES ============================ */
|
||||
/* ======================================================================== */
|
||||
|
||||
inline UINT32 EA_IMM8() {REG_PC += 1; return REG_PB | MAKE_UINT_16(REG_PC-1);}
|
||||
inline UINT32 EA_IMM16() {REG_PC += 2; return REG_PB | MAKE_UINT_16(REG_PC-2);}
|
||||
inline UINT32 EA_IMM24() {REG_PC += 3; return REG_PB | MAKE_UINT_16(REG_PC-3);}
|
||||
inline UINT32 EA_D() {if(MAKE_UINT_8(REG_D)) CLK(1); return MAKE_UINT_16(REG_D + OPER_8_IMM());}
|
||||
inline UINT32 EA_A() {return REG_DB | OPER_16_IMM();}
|
||||
inline UINT32 EA_AL() {return OPER_24_IMM();}
|
||||
inline UINT32 EA_DX() {return MAKE_UINT_16(REG_D + OPER_8_IMM() + REG_X);}
|
||||
inline UINT32 EA_DY() {return MAKE_UINT_16(REG_D + OPER_8_IMM() + REG_Y);}
|
||||
inline UINT32 EA_AX() {UINT32 tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_X;}
|
||||
inline UINT32 EA_ALX() {return EA_AL() + REG_X;}
|
||||
inline UINT32 EA_AY() {UINT32 tmp = EA_A(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
|
||||
inline UINT32 EA_DI() {return REG_DB | OPER_16_D();}
|
||||
inline UINT32 EA_DLI() {return OPER_24_D();}
|
||||
inline UINT32 EA_AI() {return read_16_A(OPER_16_IMM());}
|
||||
inline UINT32 EA_ALI() {return OPER_24_A();}
|
||||
inline UINT32 EA_DXI() {return REG_DB | OPER_16_DX();}
|
||||
inline UINT32 EA_DIY() {UINT32 tmp = REG_DB | OPER_16_D(); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
|
||||
inline UINT32 EA_DLIY() {return OPER_24_D() + REG_Y;}
|
||||
inline UINT32 EA_AXI() {return read_16_AXI(MAKE_UINT_16(OPER_16_IMM() + REG_X));}
|
||||
inline UINT32 EA_S() {return MAKE_UINT_16(REG_S + OPER_8_IMM());}
|
||||
inline UINT32 EA_SIY() {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM()) + REG_Y) | REG_DB;}
|
||||
|
||||
#endif /* __M37710IL_H__ */
|
||||
2609
src/cpu/m377/m37710op.h
Normal file
2609
src/cpu/m377/m37710op.h
Normal file
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user