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Address https://github.com/libretro/Genesis-Plus-GX/pull/237#issuecomment-788902307

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This commit is contained in:
ds22x 2021-03-02 18:08:04 +01:00
parent 02507311c4
commit 01cce8fc09
11 changed files with 49 additions and 50 deletions
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BIN
builds/genesis_plus_gx_libretro.dll
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2
core/cart_hw/sms_cart.c
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@ -2,7 +2,7 @@
* Genesis Plus
* SG-1000, Master System & Game Gear cartridge hardware support
*
* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX)
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
*
* Redistribution and use of this code or any derivative works are permitted
* provided that the following conditions are met:

16
core/cd_hw/cdd.c
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@ -201,10 +201,10 @@ void cdd_reset(void)
{
/* reset drive access latency */
cdd.latency = 0;
/* reset track index */
cdd.index = 0;
/* reset logical block address */
cdd.lba = 0;
@ -1090,7 +1090,6 @@ int cdd_load(char *filename, char *header)
fd = cdStreamOpen(fname);
}
/* Valid CD-ROM Mode 1 track found ? */
if (cdd.toc.tracks[0].type == TYPE_MODE1)
{
@ -1176,7 +1175,7 @@ int cdd_load(char *filename, char *header)
}
while (cdd.toc.last < 29);
}
else if (strstr(header + 0x180,"T-06201-01") != NULL)
else if (strstr(header + 0x180,"T-06201-01") != NULL)
{
/* Sewer Shark (USA) (REV1) */
/* no audio track */
@ -1888,7 +1887,7 @@ void cdd_process(void)
/* Process CDD command */
switch (scd.regs[0x42>>1].byte.h & 0x0f)
{
case 0x00: /* Drive Status */
case 0x00: /* Get Drive Status */
{
/* RS0-RS1 are normally unchanged unless reported drive status needs to be updated (i.e previous drive command has been processed) */
/* Note: this function is called one 75hz frame ahead of CDD update so latency counter is always one step ahead of upcoming status */
@ -2026,8 +2025,8 @@ void cdd_process(void)
scd.regs[0x40>>1].byte.h = track % 10; /* Track Number (low digit) */
break;
}
case 0x06: /* Latest Error Information */
case 0x06: /* Latest Error Information */
{
scd.regs[0x38>>1].w = (cdd.status << 8) | 0x06;
scd.regs[0x3a>>1].w = 0x0000; /* no error */
@ -2037,7 +2036,6 @@ void cdd_process(void)
break;
}
default:
{
#ifdef LOG_ERROR
@ -2336,7 +2334,7 @@ void cdd_process(void)
/* update status */
cdd.status = cdd.loaded ? CD_TOC : NO_DISC;
/* RS1-RS8 ignored, expects 0x0 (CD_STOP) in RS0 once */
/* RS1-RS8 ignored, expects CD_STOP in RS0 once */
scd.regs[0x38>>1].w = CD_STOP << 8;
scd.regs[0x3a>>1].w = 0x0000;
scd.regs[0x3c>>1].w = 0x0000;

31
core/cd_hw/scd.c
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@ -444,13 +444,13 @@ static void s68k_poll_sync(unsigned int reg_mask)
if (!m68k.stopped)
{
/* save current MAIN-CPU end cycle count (recursive execution is possible) */
/* save current MAIN-CPU end cycle count (recursive execution is possible) */
int end_cycle = m68k.cycle_end;
/* sync MAIN-CPU with SUB-CPU */
m68k_run(cycles);
/* restore MAIN-CPU end cycle count */
/* restore MAIN-CPU end cycle count */
m68k.cycle_end = end_cycle;
}
@ -671,14 +671,14 @@ static unsigned int scd_read_word(unsigned int address)
{
/* relative MAIN-CPU cycle counter */
unsigned int cycles = (s68k.cycles * MCYCLES_PER_LINE) / SCYCLES_PER_LINE;
/* save current MAIN-CPU end cycle count (recursive execution is possible) */
/* save current MAIN-CPU end cycle count (recursive execution is possible) */
int end_cycle = m68k.cycle_end;
/* sync MAIN-CPU with SUB-CPU (Mighty Morphin Power Rangers) */
m68k_run(cycles);
/* restore MAIN-CPU end cycle count */
/* restore MAIN-CPU end cycle count */
m68k.cycle_end = end_cycle;
}
@ -1267,8 +1267,8 @@ static void scd_write_word(unsigned int address, unsigned int data)
s68k_update_irq((scd.pending & data) >> 1);
return;
}
case 0x34: /* CD Fader */
case 0x34: /* CD Fader */
{
/* Wondermega hardware (CXD2554M digital filter) */
if (cdd.type == CD_TYPE_WONDERMEGA)
@ -1307,8 +1307,8 @@ static void scd_write_word(unsigned int address, unsigned int data)
return;
}
case 0x36: /* CDD control */
case 0x36: /* CDD control */
{
/* only bit 2 is writable (bits [1:0] forced to 0 by default) */
scd.regs[0x37>>1].byte.l = data & 0x04;
@ -1610,8 +1610,8 @@ void scd_reset(int hard)
s68k.cycles = 0;
s68k_pulse_reset();
s68k_pulse_halt();
/* Reset frame cycle counter */
/* Reset frame cycle counter */
scd.cycles = 0;
}
else
@ -1647,7 +1647,7 @@ void scd_reset(int hard)
/* Clear CPU polling detection */
memset(&m68k.poll, 0, sizeof(m68k.poll));
memset(&s68k.poll, 0, sizeof(s68k.poll));
/* reset CDD cycle counter */
cdd.cycles = (scd.cycles - s68k.cycles) * 3;
@ -1663,7 +1663,7 @@ void scd_update(unsigned int cycles)
int m68k_end_cycles;
int s68k_run_cycles;
int s68k_end_cycles = scd.cycles + SCYCLES_PER_LINE;
/* update CDC DMA transfer */
if (cdc.dma_w)
{
@ -1721,7 +1721,6 @@ void scd_update(unsigned int cycles)
}
}
/* Timer */
if (scd.timer)
{

4
core/loadrom.c
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@ -417,7 +417,7 @@ int load_bios(int system)
/* CD BOOTROM loaded ? */
if (size > 0)
{
/* auto-detect CD hardware model */
/* auto-detect CD hardware model */
if (!memcmp (&scd.bootrom[0x120], "WONDER-MEGA BOOT", 16))
{
/* Wondermega CD hardware */
@ -433,7 +433,7 @@ int load_bios(int system)
/* default CD hardware */
cdd.type = CD_TYPE_DEFAULT;
}
#ifdef LSB_FIRST
/* Byteswap ROM to optimize 16-bit access */
int i;

28
core/mem68k.c
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@ -275,8 +275,8 @@ static void m68k_poll_sync(unsigned int reg_mask)
/* sync SUB-CPU with MAIN-CPU */
s68k_run(cycles);
/* restore SUB-CPU end cycle count */
/* restore SUB-CPU end cycle count */
s68k.cycle_end = end_cycle;
}
@ -359,14 +359,14 @@ unsigned int ctrl_io_read_byte(unsigned int address)
{
/* relative SUB-CPU cycle counter */
unsigned int cycles = (m68k.cycles * SCYCLES_PER_LINE) / MCYCLES_PER_LINE;
/* save current SUB-CPU end cycle count (recursive execution is possible) */
/* save current SUB-CPU end cycle count (recursive execution is possible) */
int end_cycle = s68k.cycle_end;
/* sync SUB-CPU with MAIN-CPU (Dracula Unleashed w/ Sega CD Model 2 Boot ROM) */
s68k_run(cycles);
/* restore SUB-CPU end cycle count */
/* restore SUB-CPU end cycle count */
s68k.cycle_end = end_cycle;
}
@ -538,14 +538,14 @@ unsigned int ctrl_io_read_word(unsigned int address)
{
/* relative SUB-CPU cycle counter */
unsigned int cycles = (m68k.cycles * SCYCLES_PER_LINE) / MCYCLES_PER_LINE;
/* save current SUB-CPU end cycle count (recursive execution is possible) */
/* save current SUB-CPU end cycle count (recursive execution is possible) */
int end_cycle = s68k.cycle_end;
/* sync SUB-CPU with MAIN-CPU (Soul Star) */
s68k_run(cycles);
/* restore SUB-CPU end cycle count */
/* restore SUB-CPU end cycle count */
s68k.cycle_end = end_cycle;
}
@ -663,14 +663,14 @@ void ctrl_io_write_byte(unsigned int address, unsigned int data)
{
/* relative SUB-CPU cycle counter */
unsigned int cycles = (m68k.cycles * SCYCLES_PER_LINE) / MCYCLES_PER_LINE;
/* save current SUB-CPU end cycle count (recursive execution is possible) */
/* save current SUB-CPU end cycle count (recursive execution is possible) */
int end_cycle = s68k.cycle_end;
/* sync SUB-CPU with MAIN-CPU (Earnest Evans, Fhey Area) */
s68k_run(cycles);
/* restore SUB-CPU end cycle count */
/* restore SUB-CPU end cycle count */
s68k.cycle_end = end_cycle;
}

2
core/membnk.c
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@ -40,7 +40,7 @@
#include "shared.h"
T_ZBANK_MEMORY_MAP zbank_memory_map[256];
t_zbank_memory_map zbank_memory_map[256];
/*
Handlers for access to unused addresses and those which make the

4
core/membnk.h
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@ -53,8 +53,8 @@ typedef struct
{
unsigned int (*read)(unsigned int address);
void (*write)(unsigned int address, unsigned int data);
} T_ZBANK_MEMORY_MAP;
} t_zbank_memory_map;
extern T_ZBANK_MEMORY_MAP zbank_memory_map[256];
extern t_zbank_memory_map zbank_memory_map[256];
#endif /* _MEMBNK_H_ */

4
core/memz80.c
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@ -111,7 +111,7 @@ unsigned char z80_memory_r(unsigned int address)
{
if ((address >> 8) == 0x7F)
{
/* average Z80 wait-states when accessing 68k area */
/* average Z80 wait-states when accessing 68k area */
Z80.cycles += 3 * 15;
return (*zbank_memory_map[0xc0].read)(address);
}
@ -122,6 +122,7 @@ unsigned char z80_memory_r(unsigned int address)
{
/* average Z80 wait-states when accessing 68k area */
Z80.cycles += 3 * 15;
address = zbank | (address & 0x7FFF);
if (zbank_memory_map[address >> 16].read)
{
@ -180,6 +181,7 @@ void z80_memory_w(unsigned int address, unsigned char data)
{
/* average Z80 wait-states when accessing 68k area */
Z80.cycles += 3 * 15;
address = zbank | (address & 0x7FFF);
if (zbank_memory_map[address >> 16].write)
{

2
core/sound/sound.c
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@ -556,7 +556,7 @@ int sound_context_save(uint8 *state)
}
else
{
#ifdef HAVE_YM3438_CORE
#ifdef HAVE_OPLL_CORE
save_param(&config.opll, sizeof(config.opll));
if (config.opll)
{

6
core/vdp_ctrl.c
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@ -2250,7 +2250,7 @@ static void vdp_bus_w(unsigned int data)
remap_line(v_counter);
}
}
#ifdef HOOK_CPU
if (cpu_hook)
cpu_hook(HOOK_CRAM_W, 2, addr, data);
@ -2276,7 +2276,7 @@ static void vdp_bus_w(unsigned int data)
render_line(v_counter);
}
}
#ifdef HOOK_CPU
if (cpu_hook)
cpu_hook(HOOK_VSRAM_W, 2, addr, data);
@ -2485,7 +2485,7 @@ static unsigned int vdp_68k_data_r_m5(void)
{
/* read two bytes from VRAM */
data = *(uint16 *)&vram[addr & 0xFFFE];
#ifdef HOOK_CPU
if (cpu_hook)
cpu_hook(HOOK_VRAM_R, 2, addr, data);