diff --git a/packages/linux-firmware/brcmfmac_sdio-firmware/package.mk b/packages/linux-firmware/brcmfmac_sdio-firmware/package.mk index 8f2bc996b6..6b7a22c84e 100644 --- a/packages/linux-firmware/brcmfmac_sdio-firmware/package.mk +++ b/packages/linux-firmware/brcmfmac_sdio-firmware/package.mk @@ -2,8 +2,8 @@ # Copyright (C) 2019-present Team LibreELEC (https://libreelec.tv) PKG_NAME="brcmfmac_sdio-firmware" -PKG_VERSION="3d887490ab93ad956670040b5413a734e722a9fb" -PKG_SHA256="8f84cb00050f7c29ad9e3cf4c3b63b0e546adce098e667460862c84f021a2f09" +PKG_VERSION="79932201f7827ec06ec708a44bf583a772ae7522" +PKG_SHA256="b31665e3b0dfd595234241ef233e47f2e12312ce019c9b5c2e02919d0b2ddbc0" PKG_LICENSE="GPL" PKG_SITE="https://github.com/LibreELEC/brcmfmac_sdio-firmware" PKG_URL="https://github.com/LibreELEC/brcmfmac_sdio-firmware/archive/$PKG_VERSION.tar.gz" diff --git a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0002-Add-common-V4L2-request-API-code.patch b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0002-Add-common-V4L2-request-API-code.patch index 83d9fcac35..d0d66ff5cf 100644 --- a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0002-Add-common-V4L2-request-API-code.patch +++ b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0002-Add-common-V4L2-request-API-code.patch @@ -1,21 +1,21 @@ -From 4bd117a06e468ad2259f3011c95c182150f295ef Mon Sep 17 00:00:00 2001 +From 0ba3c868e1d828520b8facaa4ce36d9b80339cc6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Dec 2018 22:32:16 +0100 Subject: [PATCH 2/6] Add common V4L2 request API code Signed-off-by: Jonas Karlman --- - configure | 8 + + configure | 12 + libavcodec/Makefile | 1 + libavcodec/hwaccel.h | 2 + - libavcodec/v4l2_request.c | 885 ++++++++++++++++++++++++++++++++++++++ + libavcodec/v4l2_request.c | 888 ++++++++++++++++++++++++++++++++++++++ libavcodec/v4l2_request.h | 65 +++ - 5 files changed, 961 insertions(+) + 5 files changed, 968 insertions(+) create mode 100644 libavcodec/v4l2_request.c create mode 100644 libavcodec/v4l2_request.h diff --git a/configure b/configure -index 172611bb4a..ed587ec05e 100755 +index 172611bb4a..6401cae9e7 100755 --- a/configure +++ b/configure @@ -264,6 +264,7 @@ External library support: @@ -66,7 +66,18 @@ index 172611bb4a..ed587ec05e 100755 enabled libv4l2 && require_pkg_config libv4l2 libv4l2 libv4l2.h v4l2_ioctl enabled libvidstab && require_pkg_config libvidstab "vidstab >= 0.98" vid.stab/libvidstab.h vsMotionDetectInit enabled libvmaf && require_pkg_config libvmaf "libvmaf >= 0.6.2" libvmaf.h compute_vmaf -@@ -6230,6 +6236,8 @@ check_cc h264_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_H264;" +@@ -6153,6 +6159,10 @@ enabled rkmpp && { require_pkg_config rkmpp rockchip_mpp rockchip/r + { enabled libdrm || + die "ERROR: rkmpp requires --enable-libdrm"; } + } ++enabled v4l2_request && { enabled libdrm || ++ die "ERROR: v4l2-request requires --enable-libdrm"; } && ++ { enabled libudev || ++ die "ERROR: v4l2-request requires --enable-libudev"; } + + if enabled gcrypt; then + GCRYPT_CONFIG="${cross_prefix}libgcrypt-config" +@@ -6230,6 +6240,8 @@ check_cc h264_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_H264;" check_cc vp8_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP8;" check_cc vp9_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP9;" @@ -101,10 +112,10 @@ index 3aaa92571c..2eefc91e7e 100644 #endif /* AVCODEC_HWACCEL_H */ diff --git a/libavcodec/v4l2_request.c b/libavcodec/v4l2_request.c new file mode 100644 -index 0000000000..f66cba3ae8 +index 0000000000..4589209e60 --- /dev/null +++ b/libavcodec/v4l2_request.c -@@ -0,0 +1,885 @@ +@@ -0,0 +1,888 @@ +/* + * This file is part of FFmpeg. + * @@ -181,7 +192,7 @@ index 0000000000..f66cba3ae8 + .type = buf->buffer.type, + .memory = buf->buffer.memory, + .index = buf->index, -+ .timestamp.tv_usec = buf->index, ++ .timestamp.tv_usec = buf->index + 1, + .bytesused = buf->used, + .request_fd = request_fd, + .flags = (request_fd >= 0) ? V4L2_BUF_FLAG_REQUEST_FD : 0, @@ -282,6 +293,8 @@ index 0000000000..f66cba3ae8 + return -1; + } + ++ memset(req->output.addr + req->output.used, 0, AV_INPUT_BUFFER_PADDING_SIZE); ++ + ret = v4l2_request_queue_buffer(ctx, req->request_fd, &req->output); + if (ret < 0) { + av_log(avctx, AV_LOG_ERROR, "%s: queue output buffer %d failed for request %d, %s (%d)\n", __func__, req->output.index, req->request_fd, strerror(errno), errno); @@ -827,7 +840,6 @@ index 0000000000..f66cba3ae8 + buf->buffer.type = type; + buf->buffer.memory = V4L2_MEMORY_MMAP; + buf->buffer.index = buf->index; -+ buf->buffer.timestamp.tv_usec = buf->index; + + ret = ioctl(ctx->video_fd, VIDIOC_QUERYBUF, &buf->buffer); + if (ret < 0) { @@ -835,6 +847,8 @@ index 0000000000..f66cba3ae8 + return ret; + } + ++ buf->buffer.timestamp.tv_usec = buf->index + 1; ++ + if (V4L2_TYPE_IS_OUTPUT(type)) { + void *addr = mmap(NULL, buf->size, PROT_READ | PROT_WRITE, MAP_SHARED, ctx->video_fd, V4L2_TYPE_IS_MULTIPLANAR(type) ? buf->buffer.m.planes[0].m.mem_offset : buf->buffer.m.offset); + if (addr == MAP_FAILED) { diff --git a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0003-Add-V4L2-request-API-mpeg2-hwaccel.patch b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0003-Add-V4L2-request-API-mpeg2-hwaccel.patch index d7d46e9533..166243192e 100644 --- a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0003-Add-V4L2-request-API-mpeg2-hwaccel.patch +++ b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0003-Add-V4L2-request-API-mpeg2-hwaccel.patch @@ -1,4 +1,4 @@ -From de3bcf7557503e5d61b43cdc32d0844deab1c295 Mon Sep 17 00:00:00 2001 +From f4f6c74953b0bfaadec93b01d855a15f08c558a2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Dec 2018 22:32:16 +0100 Subject: [PATCH 3/6] Add V4L2 request API mpeg2 hwaccel @@ -14,7 +14,7 @@ Signed-off-by: Jonas Karlman create mode 100644 libavcodec/v4l2_request_mpeg2.c diff --git a/configure b/configure -index ed587ec05e..c93d67056d 100755 +index 6401cae9e7..b163ed8dbe 100755 --- a/configure +++ b/configure @@ -2846,6 +2846,8 @@ mpeg2_dxva2_hwaccel_deps="dxva2" @@ -26,7 +26,7 @@ index ed587ec05e..c93d67056d 100755 mpeg2_vaapi_hwaccel_deps="vaapi" mpeg2_vaapi_hwaccel_select="mpeg2video_decoder" mpeg2_vdpau_hwaccel_deps="vdpau" -@@ -6237,6 +6239,7 @@ check_cc vp8_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP8;" +@@ -6241,6 +6243,7 @@ check_cc vp8_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP8;" check_cc vp9_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP9;" check_func_headers "linux/media.h linux/videodev2.h" v4l2_timeval_to_ns diff --git a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0004-Add-V4L2-request-API-h264-hwaccel.patch b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0004-Add-V4L2-request-API-h264-hwaccel.patch index 829f7d45d8..3d9399156c 100644 --- a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0004-Add-V4L2-request-API-h264-hwaccel.patch +++ b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0004-Add-V4L2-request-API-h264-hwaccel.patch @@ -1,4 +1,4 @@ -From bc1ed76cbc2dad2ec308801552e2398fc2de0a07 Mon Sep 17 00:00:00 2001 +From 250fab0e761f4956c009a6333c6799f63440b091 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 Subject: [PATCH 4/6] Add V4L2 request API h264 hwaccel @@ -11,12 +11,12 @@ Signed-off-by: Jonas Karlman libavcodec/h264_slice.c | 4 + libavcodec/h264dec.c | 3 + libavcodec/hwaccels.h | 1 + - libavcodec/v4l2_request_h264.c | 368 +++++++++++++++++++++++++++++++++ - 6 files changed, 380 insertions(+) + libavcodec/v4l2_request_h264.c | 367 +++++++++++++++++++++++++++++++++ + 6 files changed, 379 insertions(+) create mode 100644 libavcodec/v4l2_request_h264.c diff --git a/configure b/configure -index c93d67056d..296ca78ce7 100755 +index b163ed8dbe..698a91d5dc 100755 --- a/configure +++ b/configure @@ -2804,6 +2804,8 @@ h264_dxva2_hwaccel_deps="dxva2" @@ -28,7 +28,7 @@ index c93d67056d..296ca78ce7 100755 h264_vaapi_hwaccel_deps="vaapi" h264_vaapi_hwaccel_select="h264_decoder" h264_vdpau_hwaccel_deps="vdpau" -@@ -6239,6 +6241,7 @@ check_cc vp8_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP8;" +@@ -6243,6 +6245,7 @@ check_cc vp8_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP8;" check_cc vp9_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP9;" check_func_headers "linux/media.h linux/videodev2.h" v4l2_timeval_to_ns @@ -98,10 +98,10 @@ index ef54de2a3b..003200edea 100644 extern const AVHWAccel ff_h264_videotoolbox_hwaccel; diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c new file mode 100644 -index 0000000000..a5c56d81c3 +index 0000000000..3687325fad --- /dev/null +++ b/libavcodec/v4l2_request_h264.c -@@ -0,0 +1,368 @@ +@@ -0,0 +1,367 @@ +/* + * This file is part of FFmpeg. + * @@ -164,8 +164,10 @@ index 0000000000..a5c56d81c3 + entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; + if (pic->long_ref) + entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM; -+ entry->top_field_order_cnt = pic->field_poc[0]; -+ entry->bottom_field_order_cnt = pic->field_poc[1]; ++ if (pic->field_poc[0] != INT_MAX) ++ entry->top_field_order_cnt = pic->field_poc[0]; ++ if (pic->field_poc[1] != INT_MAX) ++ entry->bottom_field_order_cnt = pic->field_poc[1]; +} + +static void fill_dpb(struct v4l2_ctrl_h264_decode_params *decode, const H264Context *h) @@ -174,7 +176,7 @@ index 0000000000..a5c56d81c3 + + for (int i = 0; i < h->short_ref_count; i++) { + const H264Picture *pic = h->short_ref[i]; -+ if (pic) ++ if (pic && (pic->field_poc[0] != INT_MAX || pic->field_poc[1] != INT_MAX)) + fill_dpb_entry(&decode->dpb[entries++], pic); + } + @@ -183,7 +185,7 @@ index 0000000000..a5c56d81c3 + + for (int i = 0; i < FF_ARRAY_ELEMS(h->long_ref); i++) { + const H264Picture *pic = h->long_ref[i]; -+ if (pic) ++ if (pic && (pic->field_poc[0] != INT_MAX || pic->field_poc[1] != INT_MAX)) + fill_dpb_entry(&decode->dpb[entries++], pic); + } +} @@ -299,11 +301,8 @@ index 0000000000..a5c56d81c3 + controls->decode_params = (struct v4l2_ctrl_h264_decode_params) { + .num_slices = 0, + .nal_ref_idc = h->nal_ref_idc, -+ //.ref_pic_list_p0[32] - not required? not set by libva-v4l2-request -+ //.ref_pic_list_b0[32] - not required? not set by libva-v4l2-request -+ //.ref_pic_list_b1[32] - not required? not set by libva-v4l2-request -+ .top_field_order_cnt = h->cur_pic_ptr->field_poc[0], -+ .bottom_field_order_cnt = h->cur_pic_ptr->field_poc[1], ++ .top_field_order_cnt = h->cur_pic_ptr->field_poc[0] != INT_MAX ? h->cur_pic_ptr->field_poc[0] : 0, ++ .bottom_field_order_cnt = h->cur_pic_ptr->field_poc[1] != INT_MAX ? h->cur_pic_ptr->field_poc[1] : 0, + }; + + if (h->picture_idr) diff --git a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0005-Add-V4L2-request-API-hevc-hwaccel.patch b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0005-Add-V4L2-request-API-hevc-hwaccel.patch index 7f88aefd26..68164154dc 100644 --- a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0005-Add-V4L2-request-API-hevc-hwaccel.patch +++ b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0005-Add-V4L2-request-API-hevc-hwaccel.patch @@ -1,4 +1,4 @@ -From 25065e4e219c6bd688e6b62e40be74f1cfa08e72 Mon Sep 17 00:00:00 2001 +From 55751072c14f2ef678489be3d527f34604bb5602 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 Subject: [PATCH 5/6] Add V4L2 request API hevc hwaccel @@ -15,7 +15,7 @@ Signed-off-by: Jonas Karlman create mode 100644 libavcodec/v4l2_request_hevc.c diff --git a/configure b/configure -index 296ca78ce7..9252ca5794 100755 +index 698a91d5dc..2d39cecbdf 100755 --- a/configure +++ b/configure @@ -2820,6 +2820,8 @@ hevc_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_HEVC" @@ -27,7 +27,7 @@ index 296ca78ce7..9252ca5794 100755 hevc_vaapi_hwaccel_deps="vaapi VAPictureParameterBufferHEVC" hevc_vaapi_hwaccel_select="hevc_decoder" hevc_vdpau_hwaccel_deps="vdpau VdpPictureInfoHEVC" -@@ -6242,6 +6244,7 @@ check_cc vp9_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP9;" +@@ -6246,6 +6248,7 @@ check_cc vp9_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP9;" check_func_headers "linux/media.h linux/videodev2.h" v4l2_timeval_to_ns check_cc h264_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_H264_SLICE_RAW;" @@ -103,7 +103,7 @@ index 003200edea..d183675abe 100644 extern const AVHWAccel ff_hevc_videotoolbox_hwaccel; diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c new file mode 100644 -index 0000000000..300c1866ce +index 0000000000..38969d77fb --- /dev/null +++ b/libavcodec/v4l2_request_hevc.c @@ -0,0 +1,391 @@ @@ -480,7 +480,7 @@ index 0000000000..300c1866ce + +static int v4l2_request_hevc_init(AVCodecContext *avctx) +{ -+ return ff_v4l2_request_init(avctx, V4L2_PIX_FMT_HEVC_SLICE, 2 * 1024 * 1024, NULL, 0); ++ return ff_v4l2_request_init(avctx, V4L2_PIX_FMT_HEVC_SLICE, 3 * 1024 * 1024, NULL, 0); +} + +const AVHWAccel ff_hevc_v4l2request_hwaccel = { diff --git a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0006-Add-and-use-private-linux-headers-for-V4L2-request-A.patch b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0006-Add-and-use-private-linux-headers-for-V4L2-request-A.patch index b9a4929287..c93892288f 100644 --- a/packages/multimedia/ffmpeg/patches/ffmpeg-95.0006-Add-and-use-private-linux-headers-for-V4L2-request-A.patch +++ b/packages/multimedia/ffmpeg/patches/ffmpeg-95.0006-Add-and-use-private-linux-headers-for-V4L2-request-A.patch @@ -1,27 +1,50 @@ -From 583677006f15ee59600f6f30f5e79aa5f81935b9 Mon Sep 17 00:00:00 2001 +From d80cbc949372d6f19dc8c3b5f97b336864bd259c Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 14 Feb 2019 23:20:05 +0100 Subject: [PATCH 6/6] Add and use private linux headers for V4L2 request API ctrls --- - libavcodec/h264-ctrls.h | 192 +++++++++++++++++++++++++++++++ - libavcodec/hevc-ctrls.h | 197 ++++++++++++++++++++++++++++++++ + configure | 4 +- + libavcodec/h264-ctrls.h | 197 +++++++++++++++++++++++++++++++ + libavcodec/hevc-ctrls.h | 203 ++++++++++++++++++++++++++++++++ libavcodec/mpeg2-ctrls.h | 82 +++++++++++++ libavcodec/v4l2_request_h264.c | 1 + libavcodec/v4l2_request_hevc.c | 1 + libavcodec/v4l2_request_mpeg2.c | 1 + - 6 files changed, 474 insertions(+) + 7 files changed, 487 insertions(+), 2 deletions(-) create mode 100644 libavcodec/h264-ctrls.h create mode 100644 libavcodec/hevc-ctrls.h create mode 100644 libavcodec/mpeg2-ctrls.h +diff --git a/configure b/configure +index 2d39cecbdf..23b1e57882 100755 +--- a/configure ++++ b/configure +@@ -2804,7 +2804,7 @@ h264_dxva2_hwaccel_deps="dxva2" + h264_dxva2_hwaccel_select="h264_decoder" + h264_nvdec_hwaccel_deps="nvdec" + h264_nvdec_hwaccel_select="h264_decoder" +-h264_v4l2request_hwaccel_deps="v4l2_request h264_v4l2_request" ++h264_v4l2request_hwaccel_deps="v4l2_request" + h264_v4l2request_hwaccel_select="h264_decoder" + h264_vaapi_hwaccel_deps="vaapi" + h264_vaapi_hwaccel_select="h264_decoder" +@@ -2820,7 +2820,7 @@ hevc_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_HEVC" + hevc_dxva2_hwaccel_select="hevc_decoder" + hevc_nvdec_hwaccel_deps="nvdec" + hevc_nvdec_hwaccel_select="hevc_decoder" +-hevc_v4l2request_hwaccel_deps="v4l2_request hevc_v4l2_request" ++hevc_v4l2request_hwaccel_deps="v4l2_request" + hevc_v4l2request_hwaccel_select="hevc_decoder" + hevc_vaapi_hwaccel_deps="vaapi VAPictureParameterBufferHEVC" + hevc_vaapi_hwaccel_select="hevc_decoder" diff --git a/libavcodec/h264-ctrls.h b/libavcodec/h264-ctrls.h new file mode 100644 -index 0000000000..e2f83b3cdb +index 0000000000..e1404d78d6 --- /dev/null +++ b/libavcodec/h264-ctrls.h -@@ -0,0 +1,192 @@ +@@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * These are the H.264 state controls for use with stateless H.264 @@ -35,6 +58,11 @@ index 0000000000..e2f83b3cdb +#ifndef _H264_CTRLS_H_ +#define _H264_CTRLS_H_ + ++#include ++ ++/* Our pixel format isn't stable at the moment */ ++#define V4L2_PIX_FMT_H264_SLICE_RAW v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ ++ +/* + * This is put insanely high to avoid conflicting with controls that + * would be added during the phase where those controls are not @@ -216,10 +244,10 @@ index 0000000000..e2f83b3cdb +#endif diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h new file mode 100644 -index 0000000000..c8c61079c6 +index 0000000000..eee4479c7a --- /dev/null +++ b/libavcodec/hevc-ctrls.h -@@ -0,0 +1,197 @@ +@@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * These are the HEVC state controls for use with stateless HEVC @@ -233,21 +261,27 @@ index 0000000000..c8c61079c6 +#ifndef _HEVC_CTRLS_H_ +#define _HEVC_CTRLS_H_ + -+#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 645) -+#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 646) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 647) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 648) ++#include ++ ++/* The pixel format isn't stable at the moment and will likely be renamed. */ ++#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ ++ ++#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) ++#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 1011) + +/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_HEVC_SPS 0x0115 -+#define V4L2_CTRL_TYPE_HEVC_PPS 0x0116 -+#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0117 -+#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0118 ++#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 ++#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 ++#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 ++#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 + +#define V4L2_HEVC_SLICE_TYPE_B 0 +#define V4L2_HEVC_SLICE_TYPE_P 1 +#define V4L2_HEVC_SLICE_TYPE_I 2 + ++/* The controls are not stable at the moment and will likely be reworked. */ +struct v4l2_ctrl_hevc_sps { + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + __u8 chroma_format_idc; @@ -506,7 +540,7 @@ index 0000000000..6601455b3d + +#endif diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c -index a5c56d81c3..a5dbc08a8d 100644 +index 3687325fad..2145a974eb 100644 --- a/libavcodec/v4l2_request_h264.c +++ b/libavcodec/v4l2_request_h264.c @@ -19,6 +19,7 @@ @@ -518,7 +552,7 @@ index a5c56d81c3..a5dbc08a8d 100644 typedef struct V4L2RequestControlsH264 { struct v4l2_ctrl_h264_sps sps; diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index 300c1866ce..7c7948cfbf 100644 +index 38969d77fb..b73eb2ab03 100644 --- a/libavcodec/v4l2_request_hevc.c +++ b/libavcodec/v4l2_request_hevc.c @@ -19,6 +19,7 @@ diff --git a/packages/tools/atf/patches/01-plat-allwinner-h6-add-wdt_quirk-to-use-r_wdt-instead.patch b/packages/tools/atf/patches/01-plat-allwinner-h6-add-wdt_quirk-to-use-r_wdt-instead.patch new file mode 100644 index 0000000000..51dbfc9610 --- /dev/null +++ b/packages/tools/atf/patches/01-plat-allwinner-h6-add-wdt_quirk-to-use-r_wdt-instead.patch @@ -0,0 +1,36 @@ +From 523ab5be1a84e9aa15fb62c3a15a6338b01d3961 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Tue, 9 Apr 2019 00:15:06 +0200 +Subject: [PATCH] plat: allwinner: common: use r_wdog instead of wdog +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some Allwinner H6 has a broken watchdog that doesn't +make the soc reboot. + +Use the R_WATCHDOG instead. + +Signed-off-by: Clément Péron +Change-Id: Ie95cc30a80ed517b60b30d6bc2e655a1b53f18ba +--- + plat/allwinner/common/sunxi_pm.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c +index 1d2dc93852..13e1353258 100644 +--- a/plat/allwinner/common/sunxi_pm.c ++++ b/plat/allwinner/common/sunxi_pm.c +@@ -20,9 +20,9 @@ + #include + #include + +-#define SUNXI_WDOG0_CTRL_REG (SUNXI_WDOG_BASE + 0x0010) +-#define SUNXI_WDOG0_CFG_REG (SUNXI_WDOG_BASE + 0x0014) +-#define SUNXI_WDOG0_MODE_REG (SUNXI_WDOG_BASE + 0x0018) ++#define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010) ++#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014) ++#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018) + + #define mpidr_is_valid(mpidr) ( \ + MPIDR_AFFLVL3_VAL(mpidr) == 0 && \ diff --git a/projects/Allwinner/devices/A64/patches/linux/03-opi-win-bt.patch b/projects/Allwinner/devices/A64/patches/linux/03-opi-win-bt.patch deleted file mode 100644 index dc6dc67d00..0000000000 --- a/projects/Allwinner/devices/A64/patches/linux/03-opi-win-bt.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 398a7c7ab82ab344d693a62ee633351f93046d91 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 11 Mar 2019 17:30:24 +0100 -Subject: [PATCH] orangepi win: wifi & bt - -Signed-off-by: Jernej Skrabec ---- - .../dts/allwinner/sun50i-a64-orangepi-win.dts | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -index 510f661229dc..5ef3c62c765e 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -@@ -109,6 +109,8 @@ - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; - }; - }; - -@@ -170,6 +172,14 @@ - bus-width = <4>; - non-removable; - status = "okay"; -+ -+ brcmf: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&r_pio>; -+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ -+ interrupt-names = "host-wake"; -+ }; - }; - - &ohci0 { -@@ -342,7 +352,20 @@ - &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; - status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ max-speed = <1500000>; -+ clocks = <&rtc 1>; -+ clock-names = "lpo"; -+ vbat-supply = <®_dldo2>; -+ vddio-supply = <®_dldo4>; -+ device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ -+ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ -+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ -+ }; - }; - - /* On Pi-2 connector, RTS/CTS optional */ --- -2.21.0 - diff --git a/projects/Allwinner/devices/H3/patches/linux/beelink_x2_wifi.patch b/projects/Allwinner/devices/H3/patches/linux/beelink_x2_wifi.patch deleted file mode 100644 index 08dc5f73a3..0000000000 --- a/projects/Allwinner/devices/H3/patches/linux/beelink_x2_wifi.patch +++ /dev/null @@ -1,24 +0,0 @@ -diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -index 6277f13f3eb3..6a0ac85b4616 100644 ---- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -@@ -89,7 +89,10 @@ - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; - }; - - sound_spdif { -@@ -155,6 +158,8 @@ - - &mmc1 { - vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; diff --git a/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch b/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch deleted file mode 100644 index a5a1bc9825..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch +++ /dev/null @@ -1,165 +0,0 @@ -From ed19ec00d4d62a74857ad9c2ea1dbf9671ac3580 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:36:54 +0100 -Subject: [PATCH 1/6] dt-bindings: media: cedrus: Add H6 compatible - -This adds a compatible for H6. H6 VPU supports 10-bit HEVC decoding and -additional AFBC output format for HEVC. - -Signed-off-by: Jernej Skrabec ---- - Documentation/devicetree/bindings/media/cedrus.txt | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt -index bce0705df953..20c82fb0c343 100644 ---- a/Documentation/devicetree/bindings/media/cedrus.txt -+++ b/Documentation/devicetree/bindings/media/cedrus.txt -@@ -13,6 +13,7 @@ Required properties: - - "allwinner,sun8i-h3-video-engine" - - "allwinner,sun50i-a64-video-engine" - - "allwinner,sun50i-h5-video-engine" -+ - "allwinner,sun50i-h6-video-engine" - - reg : register base and length of VE; - - clocks : list of clock specifiers, corresponding to entries in - the clock-names property; --- -2.20.1 - - -From bb6b00e1225a5b382b723d3c2190429e15a4c607 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:45:38 +0100 -Subject: [PATCH 2/6] media: cedrus: Add a quirk for not setting DMA offset - -H6 VPU doesn't work if DMA offset is set. - -Add a quirk for it. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/cedrus.h | 3 +++ - drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 3 ++- - 2 files changed, 5 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index 4aedd24a9848..c57c04b41d2e 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -28,6 +28,8 @@ - - #define CEDRUS_CAPABILITY_UNTILED BIT(0) - -+#define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) -+ - enum cedrus_codec { - CEDRUS_CODEC_MPEG2, - -@@ -91,6 +93,7 @@ struct cedrus_dec_ops { - - struct cedrus_variant { - unsigned int capabilities; -+ unsigned int quirks; - }; - - struct cedrus_dev { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index 0acf219a8c91..fbfff7c1c771 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -177,7 +177,8 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - */ - - #ifdef PHYS_PFN_OFFSET -- dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; -+ if (!(variant->quirks & CEDRUS_QUIRK_NO_DMA_OFFSET)) -+ dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; - #endif - - ret = of_reserved_mem_device_init(dev->dev); --- -2.20.1 - - -From 744c66f8c328ef40b6fb246f8b9f2daa9cce4d9d Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:47:33 +0100 -Subject: [PATCH 3/6] media: cedrus: Add support for H6 - -H6 has improved VPU. It supports 10-bit HEVC decoding and AFBC output -format for HEVC. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index ff11cbeba205..b98add3cdedd 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -396,6 +396,11 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, - }; - -+static const struct cedrus_variant sun50i_h6_cedrus_variant = { -+ .capabilities = CEDRUS_CAPABILITY_UNTILED | CEDRUS_CAPABILITY_H265_DEC, -+ .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, -+}; -+ - static const struct of_device_id cedrus_dt_match[] = { - { - .compatible = "allwinner,sun4i-a10-video-engine", -@@ -425,6 +430,10 @@ static const struct of_device_id cedrus_dt_match[] = { - .compatible = "allwinner,sun50i-h5-video-engine", - .data = &sun50i_h5_cedrus_variant, - }, -+ { -+ .compatible = "allwinner,sun50i-h6-video-engine", -+ .data = &sun50i_h6_cedrus_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, cedrus_dt_match); --- -2.20.1 - - -From c1b3128ac98c05c0afde4e6e065d6b1f2ae1dfa7 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:59:27 +0100 -Subject: [PATCH 6/6] arm64: dts: allwinner: h6: Add Video Engine node - -This adds the Video engine node for H6. It can use whole DRAM range so -there is no need for reserved memory node. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 247dc0a5ce89..de4b7a1f1012 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -146,6 +146,17 @@ - }; - }; - -+ video-codec@1c0e000 { -+ compatible = "allwinner,sun50i-h6-video-engine"; -+ reg = <0x01c0e000 0x2000>; -+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, -+ <&ccu CLK_MBUS_VE>; -+ clock-names = "ahb", "mod", "ram"; -+ resets = <&ccu RST_BUS_VE>; -+ interrupts = ; -+ allwinner,sram = <&ve_sram 1>; -+ }; -+ - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h6-system-control", - "allwinner,sun50i-a64-system-control"; --- -2.20.1 - diff --git a/projects/Allwinner/devices/H6/patches/linux/06-10-bit-HEVC-hack.patch b/projects/Allwinner/devices/H6/patches/linux/06-10-bit-HEVC-hack.patch new file mode 100644 index 0000000000..2068b70a1e --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/06-10-bit-HEVC-hack.patch @@ -0,0 +1,91 @@ +From d117460aed81ee5cd384045a1189c9de758d17c6 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 28 May 2019 21:05:34 +0200 +Subject: [PATCH] 10-bit HEVC hack + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 12 ++++++++++++ + drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 4 ++++ + drivers/staging/media/sunxi/cedrus/cedrus_video.c | 13 +++++++++++-- + 3 files changed, 27 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +index 8bbbe69ae51f..04ba7d60ebcd 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -453,6 +453,18 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + + cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg); + ++ if (sps->bit_depth_luma_minus8) { ++ unsigned int size; ++ ++ size = ALIGN(ctx->src_fmt.width, 16) * ALIGN(ctx->src_fmt.height, 16); ++ ++ reg = (size * 3) / 2; ++ cedrus_write(dev, VE_DEC_H265_OFFSET_ADDR_FIRST_OUT, reg); ++ ++ reg = DIV_ROUND_UP(ctx->src_fmt.width, 4); ++ cedrus_write(dev, VE_DEC_H265_10BIT_CONFIGURE, ALIGN(reg, 32)); ++ } ++ + reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | + VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) | + VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) | +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index d1f010ae49ef..dd69031a2779 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -505,6 +505,10 @@ + + #define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) + ++#define VE_DEC_H265_OFFSET_ADDR_FIRST_OUT (VE_ENGINE_DEC_H265 + 0x84) ++#define VE_DEC_H265_OFFSET_ADDR_SECOND_OUT (VE_ENGINE_DEC_H265 + 0x88) ++#define VE_DEC_H265_10BIT_CONFIGURE (VE_ENGINE_DEC_H265 + 0x8c) ++ + #define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \ + (((a) << 24) & GENMASK(31, 24)) + #define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \ +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index d27a9e82ff91..2c2288319c9d 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -372,6 +372,7 @@ static int cedrus_queue_setup(struct vb2_queue *vq, unsigned int *nbufs, + struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); + struct cedrus_dev *dev = ctx->dev; + struct v4l2_pix_format *pix_fmt; ++ unsigned int extra_size = 0; + u32 directions; + + if (V4L2_TYPE_IS_OUTPUT(vq->type)) { +@@ -380,6 +381,14 @@ static int cedrus_queue_setup(struct vb2_queue *vq, unsigned int *nbufs, + } else { + directions = CEDRUS_DECODE_DST; + pix_fmt = &ctx->dst_fmt; ++ ++ /* The HEVC decoder needs extra size on the output buffer. */ ++ if (ctx->src_fmt.pixelformat == V4L2_PIX_FMT_HEVC_SLICE) { ++ extra_size = DIV_ROUND_UP(pix_fmt->width, 4); ++ extra_size = ALIGN(extra_size, 32); ++ extra_size *= ALIGN(pix_fmt->height, 16) * 3; ++ extra_size /= 2; ++ } + } + + if (!cedrus_check_format(pix_fmt->pixelformat, directions, +@@ -387,8 +396,8 @@ static int cedrus_queue_setup(struct vb2_queue *vq, unsigned int *nbufs, + return -EINVAL; + + if (*nplanes) { +- if (sizes[0] < pix_fmt->sizeimage) +- return -EINVAL; ++ if (sizes[0] < (pix_fmt->sizeimage + extra_size)) ++ sizes[0] = pix_fmt->sizeimage + extra_size; + } else { + sizes[0] = pix_fmt->sizeimage; + *nplanes = 1; +-- +2.21.0 + diff --git a/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch b/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch deleted file mode 100644 index 7abb69bb99..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 18c9a269e2b744ee84f32de9d5c6c66857725ef8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 15 Dec 2018 12:56:53 +0100 -Subject: [PATCH 20/20] cedrus increase frequency - ---- - drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -index b43c77d54b95..70677571f3d3 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -@@ -16,7 +16,7 @@ - #ifndef _CEDRUS_HW_H_ - #define _CEDRUS_HW_H_ - --#define CEDRUS_CLOCK_RATE_DEFAULT 402000000 -+#define CEDRUS_CLOCK_RATE_DEFAULT 600000000 - - int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); - void cedrus_engine_disable(struct cedrus_dev *dev); --- -2.20.0 - diff --git a/projects/Allwinner/devices/H6/patches/linux/07-opi3.patch b/projects/Allwinner/devices/H6/patches/linux/07-opi3.patch new file mode 100644 index 0000000000..eaafd8aefa --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/07-opi3.patch @@ -0,0 +1,1568 @@ +From 9ea7a168e5cab7ad820439f1c595360e8c2415db Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 19 Feb 2019 21:54:24 +0100 +Subject: [PATCH 01/34] rtc: sun6i: Add support for H6 RTC + +It is mostly the same as on H5 and H3, but with slight differences +in features that are not yet supported by this driver, so we need +a different compatible, but we can re-use sun8i_h3_rtc_clk_init. + +Some differences are already stated in the comments in existing code. +One other difference is that H6 has extra bit in LOSC_CTRL_REG, called +EXT_LOSC_EN to enable/disable external low speed crystal oscillator. + +It also has bit EXT_LOSC_STA in LOSC_AUTO_SWT_STA_REG, to check whether +external low speed oscillator is working correctly. + +Signed-off-by: Ondrej Jirman +--- + drivers/rtc/rtc-sun6i.c | 47 +++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 45 insertions(+), 2 deletions(-) + +diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c +index 11f56de521791..b0fbaa1837dd5 100644 +--- a/drivers/rtc/rtc-sun6i.c ++++ b/drivers/rtc/rtc-sun6i.c +@@ -41,11 +41,15 @@ + /* Control register */ + #define SUN6I_LOSC_CTRL 0x0000 + #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) ++#define SUN6I_LOSC_CTRL_AUTO_SWT_EN BIT(14) ++#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) + #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) + #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) + #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) ++#define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) + #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) + #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) ++#define SUN6I_LOSC_CTRL_EXT_OSC_GSM 0x08 + + #define SUN6I_LOSC_CLK_PRESCAL 0x0008 + +@@ -137,6 +141,8 @@ struct sun6i_rtc_clk_data { + unsigned int has_prescaler : 1; + unsigned int has_out_clk : 1; + unsigned int export_iosc : 1; ++ unsigned int has_losc_en : 1; ++ unsigned int has_auto_swt : 1; + }; + + struct sun6i_rtc_dev { +@@ -199,6 +205,10 @@ static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) + val &= ~SUN6I_LOSC_CTRL_EXT_OSC; + val |= SUN6I_LOSC_CTRL_KEY; + val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; ++ if (rtc->data->has_losc_en) { ++ val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; ++ val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; ++ } + writel(val, rtc->base + SUN6I_LOSC_CTRL); + spin_unlock_irqrestore(&rtc->lock, flags); + +@@ -224,6 +234,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, + const char *iosc_name = "rtc-int-osc"; + const char *clkout_name = "osc32k-out"; + const char *parents[2]; ++ u32 reg; + + rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); + if (!rtc) +@@ -244,9 +255,23 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, + goto err; + } + ++ reg = SUN6I_LOSC_CTRL_KEY; ++ if (rtc->data->has_auto_swt) { ++ /* Bypass auto-switch to int osc, on ext losc failure */ ++ reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; ++ writel(reg, rtc->base + SUN6I_LOSC_CTRL); ++ } ++ + /* Switch to the external, more precise, oscillator */ +- writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC, +- rtc->base + SUN6I_LOSC_CTRL); ++ reg |= SUN6I_LOSC_CTRL_EXT_OSC; ++ if (rtc->data->has_losc_en) ++ reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; ++ writel(reg, rtc->base + SUN6I_LOSC_CTRL); ++ ++ /* Set GSM with some delay, after switching to ext losc. */ ++ udelay(10); ++ reg |= SUN6I_LOSC_CTRL_EXT_OSC_GSM; ++ writel(reg, rtc->base + SUN6I_LOSC_CTRL); + + /* Yes, I know, this is ugly. */ + sun6i_rtc = rtc; +@@ -354,6 +379,23 @@ CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", + CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", + sun8i_h3_rtc_clk_init); + ++static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { ++ .rc_osc_rate = 16000000, ++ .fixed_prescaler = 32, ++ .has_prescaler = 1, ++ .has_out_clk = 1, ++ .export_iosc = 1, ++ .has_losc_en = 1, ++ .has_auto_swt = 1, ++}; ++ ++static void __init sun50i_h6_rtc_clk_init(struct device_node *node) ++{ ++ sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); ++} ++CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", ++ sun50i_h6_rtc_clk_init); ++ + static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { + .rc_osc_rate = 32000, + .has_out_clk = 1, +@@ -683,6 +725,7 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = { + { .compatible = "allwinner,sun8i-h3-rtc" }, + { .compatible = "allwinner,sun8i-v3-rtc" }, + { .compatible = "allwinner,sun50i-h5-rtc" }, ++ { .compatible = "allwinner,sun50i-h6-rtc" }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); + +From 80472652eff72ba5198dc5d678612fb91e411ed1 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Fri, 12 Apr 2019 13:32:05 +0200 +Subject: [PATCH 02/34] arm64: dts: sun50i-h6: Add support for RTC and fix the + clock tree + +This patch adds RTC node and fixes the clock properties and nodes +to reflect the real clock tree. + +The device nodes for the internal oscillator and osc32k are removed, +as these clocks are now provided by the RTC device. Clock references +are fixed accordingly, too. + +Signed-off-by: Ondrej Jirman +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++++++--------- + 1 file changed, 16 insertions(+), 14 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index c9e861a50a633..ae7977f3f054c 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -56,14 +56,6 @@ + status = "disabled"; + }; + +- iosc: internal-osc-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16000000>; +- clock-accuracy = <300000000>; +- clock-output-names = "iosc"; +- }; +- + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; +@@ -71,11 +63,11 @@ + clock-output-names = "osc24M"; + }; + +- osc32k: osc32k_clk { ++ ext_osc32k: ext_osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; +- clock-output-names = "osc32k"; ++ clock-output-names = "ext_osc32k"; + }; + + psci { +@@ -186,7 +178,7 @@ + ccu: clock@3001000 { + compatible = "allwinner,sun50i-h6-ccu"; + reg = <0x03001000 0x1000>; +- clocks = <&osc24M>, <&osc32k>, <&iosc>; ++ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -199,7 +191,7 @@ + , + , + ; +- clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; ++ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; +@@ -583,10 +575,20 @@ + }; + }; + ++ rtc: rtc@7000000 { ++ compatible = "allwinner,sun50i-h6-rtc"; ++ reg = <0x07000000 0x400>; ++ interrupts = , ++ ; ++ clock-output-names = "osc32k", "osc32k-out", "iosc"; ++ clocks = <&ext_osc32k>; ++ #clock-cells = <1>; ++ }; ++ + r_ccu: clock@7010000 { + compatible = "allwinner,sun50i-h6-r-ccu"; + reg = <0x07010000 0x400>; +- clocks = <&osc24M>, <&osc32k>, <&iosc>, ++ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; +@@ -607,7 +609,7 @@ + reg = <0x07022000 0x400>; + interrupts = , + ; +- clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; ++ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + +From de4dc594bb3cb124d21fd7550ca0497c7fa22ff0 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Thu, 11 Apr 2019 11:20:54 +0200 +Subject: [PATCH 07/34] arm64: dts: h6: Make mmc0_pins the default for &mmc0 + +Signed-off-by: Ondrej Jirman +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index ae7977f3f054c..91623a8cd2a08 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -254,6 +254,8 @@ + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + +From 45bbbb485eb478df71079fd69f7ee8e48d0b0809 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Thu, 11 Apr 2019 11:11:21 +0200 +Subject: [PATCH 08/34] arm64: dts: allwinner: h6: Add Orange Pi 3 DTS + +Orange Pi 3 is a H6 based SBC made by Xulong, released in January 2019. It +has the following features: + +- Allwinner H6 quad-core 64-bit ARM Cortex-A53 +- GPU Mali-T720 +- 1GB or 2GB LPDDR3 RAM +- AXP805 PMIC +- AP6256 Wifi/BT 5.0 +- USB 2.0 host port (A) +- USB 2.0 micro usb, OTG +- USB 3.0 Host + 4 port USB hub (GL3510) +- Gigabit Ethernet (Realtek RTL8211E phy) +- HDMI 2.0 port +- soldered eMMC (optional) +- 3x LED (one is on the bottom) +- microphone +- audio jack +- PCIe + +Add basic support for the board. + +Signed-off-by: Ondrej Jirman +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../dts/allwinner/sun50i-h6-orangepi-3.dts | 215 ++++++++++++++++++ + 2 files changed, 216 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 0b09171110994..13a7e87bc35cc 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +new file mode 100644 +index 0000000000000..17d4969901086 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -0,0 +1,219 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2019 Ondřej Jirman ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h6.dtsi" ++ ++#include ++ ++/ { ++ model = "OrangePi 3"; ++ compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ power { ++ label = "orangepi:red:power"; ++ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ ++ default-state = "on"; ++ }; ++ ++ status { ++ label = "orangepi:green:status"; ++ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ ++ }; ++ }; ++ ++ reg_vcc5v: vcc5v { ++ /* board wide 5V supply directly from the DC jack */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <®_dcdcc>; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_cldo1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++}; ++ ++&r_i2c { ++ status = "okay"; ++ ++ axp805: pmic@36 { ++ compatible = "x-powers,axp805", "x-powers,axp806"; ++ reg = <0x36>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ x-powers,self-working-mode; ++ vina-supply = <®_vcc5v>; ++ vinb-supply = <®_vcc5v>; ++ vinc-supply = <®_vcc5v>; ++ vind-supply = <®_vcc5v>; ++ vine-supply = <®_vcc5v>; ++ aldoin-supply = <®_vcc5v>; ++ bldoin-supply = <®_vcc5v>; ++ cldoin-supply = <®_vcc5v>; ++ ++ regulators { ++ reg_aldo1: aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl-led-ir"; ++ }; ++ ++ reg_aldo2: aldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-audio-tv-ephy-mac"; ++ }; ++ ++ /* ALDO3 is shorted to CLDO1 */ ++ reg_aldo3: aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; ++ }; ++ ++ reg_bldo1: bldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc18-dram-bias-pll"; ++ }; ++ ++ reg_bldo2: bldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-efuse-pcie-hdmi-pc"; ++ }; ++ ++ bldo3 { ++ /* unused */ ++ }; ++ ++ bldo4 { ++ /* unused */ ++ }; ++ ++ reg_cldo1: cldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; ++ }; ++ ++ cldo2 { ++ /* unused */ ++ }; ++ ++ cldo3 { ++ /* unused */ ++ }; ++ ++ reg_dcdca: dcdca { ++ regulator-always-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1160000>; ++ regulator-name = "vdd-cpu"; ++ }; ++ ++ reg_dcdcc: dcdcc { ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <1080000>; ++ regulator-name = "vdd-gpu"; ++ }; ++ ++ reg_dcdcd: dcdcd { ++ regulator-always-on; ++ regulator-min-microvolt = <960000>; ++ regulator-max-microvolt = <960000>; ++ regulator-name = "vdd-sys"; ++ }; ++ ++ reg_dcdce: dcdce { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++ }; ++ ++ sw { ++ /* unused */ ++ }; ++ }; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++&usb2otg { ++ /* ++ * This board doesn't have a controllable VBUS even though it ++ * does have an ID pin. Using it as anything but a USB host is ++ * unsafe. ++ */ ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb2phy { ++ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ ++ usb0_vbus-supply = <®_vcc5v>; ++ usb3_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; + +From 2a87073bd0857fd9707de2ac96cb04d6d9e0e288 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 9 Jan 2018 23:58:12 +0800 +Subject: [PATCH 10/34] net: stmmac: sun8i: force select external PHY when no + internal one + +From e6d3f7e02d211522c7f1cc09df946292601b55b6 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Wed, 27 Mar 2019 13:21:06 +0100 +Subject: [PATCH 13/34] arm64: dts: allwinner: orange-pi-3: Enable ethernet + +Orange Pi 3 has two regulators that power the Realtek RTL8211E. According +to the phy datasheet, both regulators need to be enabled at the same time, +but we can only specify a single phy-supply in the DT. + +This can be achieved by making one regulator depedning on the other via +vin-supply. While it's not a technically correct description of the +hardware, it achieves the purpose. + +All values of RX/TX delay were tested exhaustively and a middle one of the +working values was chosen. + +Signed-off-by: Ondrej Jirman +--- + .../dts/allwinner/sun50i-h6-orangepi-3.dts | 44 +++++++++++++++++++ + 1 file changed, 44 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index 17d4969901086..6d6b1f66796d9 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -15,6 +15,7 @@ + + aliases { + serial0 = &uart0; ++ ethernet0 = &emac; + }; + + chosen { +@@ -44,6 +45,27 @@ + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ /* ++ * The board uses 2.5V RGMII signalling. Power sequence to enable ++ * the phy is to enable GMAC-2V5 and GMAC-3V3 (aldo2) power rails ++ * at the same time and to wait 100ms. ++ */ ++ reg_gmac_2v5: gmac-2v5 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-2v5"; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ ++ ++ /* The real parent of gmac-2v5 is reg_vcc5v, but we need to ++ * enable two regulators to power the phy. This is one way ++ * to achieve that. ++ */ ++ vin-supply = <®_aldo2>; /* GMAC-3V3 */ ++ }; + }; + + &cpu0 { +@@ -58,6 +80,28 @@ + status = "okay"; + }; + ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-supply = <®_gmac_2v5>; ++ allwinner,rx-delay-ps = <1500>; ++ allwinner,tx-delay-ps = <700>; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ ++ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ ++ reset-assert-us = <15000>; ++ reset-deassert-us = <40000>; ++ }; ++}; ++ + &mmc0 { + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + +From b641bc59468e93ab57fd016ad36b037f3890b994 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 26 Mar 2019 15:06:37 +0100 +Subject: [PATCH 15/34] drm: sun4i: Add support for enabling DDC I2C bus power + to dw_hdmi glue + +Orange Pi 3 board requires enabling DDC I2C bus via some GPIO connected +transistors, before the bus can be used. + +Model this as a power supply for DDC bus on the HDMI connector connected +to the output port (port 1) of the HDMI controller. + +Signed-off-by: Ondrej Jirman +--- + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 60 ++++++++++++++++++++++++++- + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 + + 2 files changed, 60 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +index 39d8509d96a0d..1b6ffba41177f 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +@@ -98,6 +98,30 @@ static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm, + return crtcs; + } + ++static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev, ++ struct platform_device **pdev_out) ++{ ++ struct platform_device* pdev; ++ struct device_node *remote; ++ ++ remote = of_graph_get_remote_node(dev->of_node, 1, -1); ++ if (!remote) ++ return -ENODEV; ++ ++ if (!of_device_is_compatible(remote, "hdmi-connector")) { ++ of_node_put(remote); ++ return -ENODEV; ++ } ++ ++ pdev = of_find_device_by_node(remote); ++ of_node_put(remote); ++ if (!pdev) ++ return -ENODEV; ++ ++ *pdev_out = pdev; ++ return 0; ++} ++ + static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, + void *data) + { +@@ -151,16 +175,34 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, + return PTR_ERR(hdmi->regulator); + } + ++ ret = sun8i_dw_hdmi_find_connector_pdev(dev, &hdmi->connector_pdev); ++ if (!ret) { ++ hdmi->ddc_regulator = regulator_get(&hdmi->connector_pdev->dev, "ddc"); ++ if (IS_ERR(hdmi->ddc_regulator)) { ++ platform_device_put(hdmi->connector_pdev); ++ dev_err(dev, "Couldn't get ddc regulator\n"); ++ return PTR_ERR(hdmi->ddc_regulator); ++ } ++ } ++ + ret = regulator_enable(hdmi->regulator); + if (ret) { + dev_err(dev, "Failed to enable regulator\n"); +- return ret; ++ goto err_unref_ddc_regulator; ++ } ++ ++ if (hdmi->ddc_regulator) { ++ ret = regulator_enable(hdmi->ddc_regulator); ++ if (ret) { ++ dev_err(dev, "Failed to enable ddc regulator\n"); ++ goto err_disable_regulator; ++ } + } + + ret = reset_control_deassert(hdmi->rst_ctrl); + if (ret) { + dev_err(dev, "Could not deassert ctrl reset control\n"); +- goto err_disable_regulator; ++ goto err_disable_ddc_regulator; + } + + ret = clk_prepare_enable(hdmi->clk_tmds); +@@ -213,8 +255,15 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, + clk_disable_unprepare(hdmi->clk_tmds); + err_assert_ctrl_reset: + reset_control_assert(hdmi->rst_ctrl); ++err_disable_ddc_regulator: ++ if (hdmi->ddc_regulator) ++ regulator_disable(hdmi->ddc_regulator); + err_disable_regulator: + regulator_disable(hdmi->regulator); ++err_unref_ddc_regulator: ++ if (hdmi->ddc_regulator) ++ regulator_put(hdmi->ddc_regulator); ++ platform_device_put(hdmi->connector_pdev); + + return ret; + } +@@ -229,6 +278,13 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master, + clk_disable_unprepare(hdmi->clk_tmds); + reset_control_assert(hdmi->rst_ctrl); + regulator_disable(hdmi->regulator); ++ ++ if (hdmi->ddc_regulator) { ++ regulator_disable(hdmi->ddc_regulator); ++ regulator_put(hdmi->ddc_regulator); ++ } ++ ++ platform_device_put(hdmi->connector_pdev); + } + + static const struct component_ops sun8i_dw_hdmi_ops = { +diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +index 720c5aa8adc14..60f5200aee73b 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +@@ -188,8 +188,10 @@ struct sun8i_dw_hdmi { + struct sun8i_hdmi_phy *phy; + struct dw_hdmi_plat_data plat_data; + struct regulator *regulator; ++ struct regulator *ddc_regulator; + const struct sun8i_dw_hdmi_quirks *quirks; + struct reset_control *rst_ctrl; ++ struct platform_device *connector_pdev; + }; + + static inline struct sun8i_dw_hdmi * + +From c1d7c7796ea7e76829c71b993c7531f23c0f5913 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 9 Apr 2019 01:41:58 +0200 +Subject: [PATCH 16/34] arm64: dts: allwinner: orange-pi-3: Enable HDMI output + +Orange Pi 3 has a DDC_CEC_EN signal connected to PH2, that enables the DDC +I2C bus voltage shifter. Before EDID can be read, we need to pull PH2 high. + +Signed-off-by: Ondrej Jirman +--- + .../dts/allwinner/sun50i-h6-orangepi-3.dts | 35 +++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index 6d6b1f66796d9..58a6635c909e3 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -22,6 +22,18 @@ + stdout-path = "serial0:115200n8"; + }; + ++ connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ddc-supply = <®_ddc>; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -37,6 +49,15 @@ + }; + }; + ++ reg_ddc: ddc-io { ++ compatible = "regulator-fixed"; ++ regulator-name = "ddc-io"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ ++ }; ++ + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC jack */ + compatible = "regulator-fixed"; +@@ -72,6 +93,10 @@ + cpu-supply = <®_dcdca>; + }; + ++&de { ++ status = "okay"; ++}; ++ + &ehci0 { + status = "okay"; + }; +@@ -91,6 +116,16 @@ + status = "okay"; + }; + ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + +From 756b0ba6d79844dbc04c6c4ea0fc25b52209721a Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Fri, 5 Apr 2019 22:21:00 +0200 +Subject: [PATCH 17/34] brcmfmac: Loading the correct firmware for brcm43456 + +SDIO based brcm43456 is currently misdetected as brcm43455 and the wrong +firmware name is used. Correct the detection and load the correct firmware +file. Chiprev for brcm43456 is "9". + +Signed-off-by: Ondrej Jirman +--- + drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c +index 4d104ab80fd8e..50e56fd056baa 100644 +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c +@@ -622,6 +622,7 @@ BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio"); + /* Note the names are not postfixed with a1 for backward compatibility */ + BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio"); + BRCMF_FW_DEF(43455, "brcmfmac43455-sdio"); ++BRCMF_FW_DEF(43456, "brcmfmac43456-sdio"); + BRCMF_FW_DEF(4354, "brcmfmac4354-sdio"); + BRCMF_FW_DEF(4356, "brcmfmac4356-sdio"); + BRCMF_FW_DEF(4373, "brcmfmac4373-sdio"); +@@ -642,7 +643,8 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { + BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), + BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0), + BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1), +- BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455), ++ BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456), ++ BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455), + BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354), + BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), + BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373), + +From 5bf634f86c57f59f5c4a4fade9ccfe582334464f Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Mon, 18 Feb 2019 13:53:18 +0100 +Subject: [PATCH 18/34] arm64: dts: allwinner: h6: Add MMC1 pins + +MMC1 is used on some H6 boards we want to support. Typical use is 4-bit +SDIO interface with a WiFi chip. Add pin definitions for this use case. + +As this is the only possible configration for mmc1, make it the default +one, too. + +Signed-off-by: Ondrej Jirman +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 91623a8cd2a08..c5c0608e67403 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -219,6 +219,15 @@ + bias-pull-up; + }; + ++ /omit-if-no-ref/ ++ mmc1_pins: mmc1-pins { ++ pins = "PG0", "PG1", "PG2", "PG3", ++ "PG4", "PG5"; ++ function = "mmc1"; ++ drive-strength = <30>; ++ bias-pull-up; ++ }; ++ + mmc2_pins: mmc2-pins { + pins = "PC1", "PC4", "PC5", "PC6", + "PC7", "PC8", "PC9", "PC10", +@@ -270,6 +279,8 @@ + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + +From 200cf18794214700f023440021cb7fd40dcc0f01 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 9 Apr 2019 00:16:35 +0200 +Subject: [PATCH 19/34] arm64: dts: allwinner: orange-pi-3: Enable WiFi + +Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is called +bcm43356 and can be used with the brcmfmac driver. The module is powered by +the two always on regulators (not AXP805). + +WiFi uses a PG port with 1.8V voltage level signals. SoC needs to be +configured so that it sets up an 1.8V input bias on this port. This is done +by the pio driver by reading the vcc-pg-supply voltage. + +You'll need a fw_bcm43456c5_ag.bin firmware file and nvram.txt +configuration that can be found in the Xulongs's repository for H6: + +https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 + +Mainline brcmfmac driver expects the firmware and nvram at the following +paths relative to the firmware directory: + + brcm/brcmfmac43456-sdio.bin + brcm/brcmfmac43456-sdio.txt + +Signed-off-by: Ondrej Jirman +--- + .../dts/allwinner/sun50i-h6-orangepi-3.dts | 48 +++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index 58a6635c909e3..f795362f5b77e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -67,6 +67,26 @@ + regulator-always-on; + }; + ++ reg_vcc33_wifi: vcc33-wifi { ++ /* Always on 3.3V regulator for WiFi and BT */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc33-wifi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_vcc_wifi_io: vcc-wifi-io { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-wifi-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_vcc33_wifi>; ++ }; ++ + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V3 (aldo2) power rails +@@ -87,6 +107,14 @@ + */ + vin-supply = <®_aldo2>; /* GMAC-3V3 */ + }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ ++ post-power-on-delay-ms = <200>; ++ }; + }; + + &cpu0 { +@@ -144,6 +172,25 @@ + status = "okay"; + }; + ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_vcc33_wifi>; ++ vqmmc-supply = <®_vcc_wifi_io>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcm: sdio-wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ + &ohci0 { + status = "okay"; + }; +@@ -155,6 +202,7 @@ + &pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_vcc_wifi_io>; + }; + + &r_i2c { + +From d996492e1f700a9f0a104c50b126a022dee77dd6 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Mon, 25 Dec 2017 12:04:02 +0800 +Subject: [PATCH 20/34] phy: allwinner: add phy driver for USB3 PHY on + Allwinner H6 SoC + +Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also +controlled). + +Add a driver for it. + +The register operations in this driver is mainly extracted from the BSP +USB3 driver. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Chen-Yu Tsai +--- + drivers/phy/allwinner/Kconfig | 12 ++ + drivers/phy/allwinner/Makefile | 1 + + drivers/phy/allwinner/phy-sun50i-usb3.c | 194 ++++++++++++++++++++++++ + 3 files changed, 207 insertions(+) + create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c + +diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig +index fb1204bcc4548..2c363db177f20 100644 +--- a/drivers/phy/allwinner/Kconfig ++++ b/drivers/phy/allwinner/Kconfig +@@ -41,3 +41,15 @@ config PHY_SUN9I_USB + sun9i SoCs. + + This driver controls each individual USB 2 host PHY. ++ ++config PHY_SUN50I_USB3 ++ tristate "Allwinner sun50i SoC USB3 PHY driver" ++ depends on ARCH_SUNXI && HAS_IOMEM && OF ++ depends on RESET_CONTROLLER ++ select USB_COMMON ++ select GENERIC_PHY ++ help ++ Enable this to support the USB3.0-capable transceiver that is ++ part of some Allwinner sun50i SoCs. ++ ++ This driver controls each individual USB 2+3 host PHY combo. +diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile +index 7d0053efbfaa6..59575a895779b 100644 +--- a/drivers/phy/allwinner/Makefile ++++ b/drivers/phy/allwinner/Makefile +@@ -1,3 +1,4 @@ + obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o + obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY) += phy-sun6i-mipi-dphy.o + obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o ++obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o +diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c +new file mode 100644 +index 0000000000000..226c99c2d664c +--- /dev/null ++++ b/drivers/phy/allwinner/phy-sun50i-usb3.c +@@ -0,0 +1,194 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Allwinner sun50i(H6) USB 3.0 phy driver ++ * ++ * Copyright (C) 2017 Icenowy Zheng ++ * ++ * Based on phy-sun9i-usb.c, which is: ++ * ++ * Copyright (C) 2014-2015 Chen-Yu Tsai ++ * ++ * Based on code from Allwinner BSP, which is: ++ * ++ * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Interface Status and Control Registers */ ++#define SUNXI_ISCR 0x00 ++#define SUNXI_PIPE_CLOCK_CONTROL 0x14 ++#define SUNXI_PHY_TUNE_LOW 0x18 ++#define SUNXI_PHY_TUNE_HIGH 0x1c ++#define SUNXI_PHY_EXTERNAL_CONTROL 0x20 ++ ++/* USB2.0 Interface Status and Control Register */ ++#define SUNXI_ISCR_FORCE_VBUS (3 << 12) ++ ++/* PIPE Clock Control Register */ ++#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6) ++ ++/* PHY External Control Register */ ++#define SUNXI_PEC_EXTERN_VBUS (3 << 1) ++#define SUNXI_PEC_SSC_EN (1 << 24) ++#define SUNXI_PEC_REF_SSP_EN (1 << 26) ++ ++/* PHY Tune High Register */ ++#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) ++#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19) ++#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) ++#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13) ++#define SUNXI_TX_SWING_FULL(n) ((n) << 6) ++#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6) ++#define SUNXI_LOS_BIAS(n) ((n) << 3) ++#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3) ++#define SUNXI_TXVBOOSTLVL(n) ((n) << 0) ++#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2) ++ ++struct sun50i_usb3_phy { ++ struct phy *phy; ++ void __iomem *regs; ++ struct reset_control *reset; ++ struct clk *clk; ++}; ++ ++static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy) ++{ ++ u32 val; ++ ++ val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); ++ val |= SUNXI_PEC_EXTERN_VBUS; ++ val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN; ++ writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); ++ ++ val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL); ++ val |= SUNXI_PCC_PIPE_CLK_OPEN; ++ writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL); ++ ++ val = readl(phy->regs + SUNXI_ISCR); ++ val |= SUNXI_ISCR_FORCE_VBUS; ++ writel(val, phy->regs + SUNXI_ISCR); ++ ++ /* ++ * All the magic numbers written to the PHY_TUNE_{LOW_HIGH} ++ * registers are directly taken from the BSP USB3 driver from ++ * Allwiner. ++ */ ++ writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW); ++ ++ val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH); ++ val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK | ++ SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK | ++ SUNXI_TX_DEEMPH_3P5DB_MASK); ++ val |= SUNXI_TXVBOOSTLVL(0x7); ++ val |= SUNXI_LOS_BIAS(0x7); ++ val |= SUNXI_TX_SWING_FULL(0x55); ++ val |= SUNXI_TX_DEEMPH_6DB(0x20); ++ val |= SUNXI_TX_DEEMPH_3P5DB(0x15); ++ writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH); ++} ++ ++static int sun50i_usb3_phy_init(struct phy *_phy) ++{ ++ struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); ++ int ret; ++ ++ ret = clk_prepare_enable(phy->clk); ++ if (ret) ++ goto err_clk; ++ ++ ret = reset_control_deassert(phy->reset); ++ if (ret) ++ goto err_reset; ++ ++ sun50i_usb3_phy_open(phy); ++ return 0; ++ ++err_reset: ++ clk_disable_unprepare(phy->clk); ++ ++err_clk: ++ return ret; ++} ++ ++static int sun50i_usb3_phy_exit(struct phy *_phy) ++{ ++ struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); ++ ++ reset_control_assert(phy->reset); ++ clk_disable_unprepare(phy->clk); ++ ++ return 0; ++} ++ ++static const struct phy_ops sun50i_usb3_phy_ops = { ++ .init = sun50i_usb3_phy_init, ++ .exit = sun50i_usb3_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static int sun50i_usb3_phy_probe(struct platform_device *pdev) ++{ ++ struct sun50i_usb3_phy *phy; ++ struct device *dev = &pdev->dev; ++ struct phy_provider *phy_provider; ++ struct resource *res; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(phy->clk)) { ++ dev_err(dev, "failed to get phy clock\n"); ++ return PTR_ERR(phy->clk); ++ } ++ ++ phy->reset = devm_reset_control_get(dev, NULL); ++ if (IS_ERR(phy->reset)) { ++ dev_err(dev, "failed to get reset control\n"); ++ return PTR_ERR(phy->reset); ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ phy->regs = devm_ioremap_resource(dev, res); ++ if (IS_ERR(phy->regs)) ++ return PTR_ERR(phy->regs); ++ ++ phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops); ++ if (IS_ERR(phy->phy)) { ++ dev_err(dev, "failed to create PHY\n"); ++ return PTR_ERR(phy->phy); ++ } ++ ++ phy_set_drvdata(phy->phy, phy); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id sun50i_usb3_phy_of_match[] = { ++ { .compatible = "allwinner,sun50i-h6-usb3-phy" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match); ++ ++static struct platform_driver sun50i_usb3_phy_driver = { ++ .probe = sun50i_usb3_phy_probe, ++ .driver = { ++ .of_match_table = sun50i_usb3_phy_of_match, ++ .name = "sun50i-usb3-phy", ++ } ++}; ++module_platform_driver(sun50i_usb3_phy_driver); ++ ++MODULE_DESCRIPTION("Allwinner sun50i USB 3.0 phy driver"); ++MODULE_AUTHOR("Icenowy Zheng "); ++MODULE_LICENSE("GPL"); + +From 5fd2d3bd956cc875d07433454f18dcbc14e120d5 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 26 Mar 2019 15:14:14 +0100 +Subject: [PATCH 24/34] bluetooth: bcm: Add support for loading firmware for + BCM4345C5 + +WIP + +Signed-off-by: Ondrej Jirman +--- + drivers/bluetooth/btbcm.c | 3 +++ + drivers/bluetooth/hci_bcm.c | 1 + + 2 files changed, 4 insertions(+) + +diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c +index d5d6e6e5da3bf..a58bf860bcbfc 100644 +--- a/drivers/bluetooth/btbcm.c ++++ b/drivers/bluetooth/btbcm.c +@@ -37,6 +37,7 @@ + #define BDADDR_BCM43430A0 (&(bdaddr_t) {{0xac, 0x1f, 0x12, 0xa0, 0x43, 0x43}}) + #define BDADDR_BCM4324B3 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb3, 0x24, 0x43}}) + #define BDADDR_BCM4330B1 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb1, 0x30, 0x43}}) ++#define BDADDR_BCM4345C5 (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0xc5, 0x45, 0x43}}) + + int btbcm_check_bdaddr(struct hci_dev *hdev) + { +@@ -82,6 +83,7 @@ int btbcm_check_bdaddr(struct hci_dev *hdev) + !bacmp(&bda->bdaddr, BDADDR_BCM20702A1) || + !bacmp(&bda->bdaddr, BDADDR_BCM4324B3) || + !bacmp(&bda->bdaddr, BDADDR_BCM4330B1) || ++ !bacmp(&bda->bdaddr, BDADDR_BCM4345C5) || + !bacmp(&bda->bdaddr, BDADDR_BCM43430A0)) { + bt_dev_info(hdev, "BCM: Using default device address (%pMR)", + &bda->bdaddr); +@@ -339,6 +341,7 @@ static const struct bcm_subver_table bcm_uart_subver_table[] = { + { 0x2122, "BCM4343A0" }, /* 001.001.034 */ + { 0x2209, "BCM43430A1" }, /* 001.002.009 */ + { 0x6119, "BCM4345C0" }, /* 003.001.025 */ ++ { 0x6606, "BCM4345C5" }, /* 003.006.006 */ + { 0x230f, "BCM4356A2" }, /* 001.003.015 */ + { 0x220e, "BCM20702A1" }, /* 001.002.014 */ + { 0x4217, "BCM4329B1" }, /* 002.002.023 */ +diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c +index ddbe518c3e5b8..d5d5ddc3cf1b8 100644 +--- a/drivers/bluetooth/hci_bcm.c ++++ b/drivers/bluetooth/hci_bcm.c +@@ -1419,6 +1419,7 @@ static void bcm_serdev_remove(struct serdev_device *serdev) + #ifdef CONFIG_OF + static const struct of_device_id bcm_bluetooth_of_match[] = { + { .compatible = "brcm,bcm20702a1" }, ++ { .compatible = "brcm,bcm4345c5" }, + { .compatible = "brcm,bcm4330-bt" }, + { .compatible = "brcm,bcm43438-bt" }, + { }, + +From d5626d424fbdc9dde5f8a2e525e88de33fc898cc Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Fri, 12 Apr 2019 13:24:26 +0200 +Subject: [PATCH 25/34] bluetooth: hci_bcm: Give more time to come out of reset + +Some devices need more time to come out of reset (eg. BCM4345). +Increase the post-reset delay. I don't have datasheet, so rather +be safe than to get intermittent failures during probe. + +Signed-off-by: Ondrej Jirman +--- + drivers/bluetooth/hci_bcm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c +index d5d5ddc3cf1b8..9eacaf8f72ec3 100644 +--- a/drivers/bluetooth/hci_bcm.c ++++ b/drivers/bluetooth/hci_bcm.c +@@ -263,7 +263,7 @@ static int bcm_gpio_set_power(struct bcm_device *dev, bool powered) + } + + /* wait for device to power on and come out of reset */ +- usleep_range(10000, 20000); ++ usleep_range(50000, 60000); + + dev->res_enabled = powered; + + +From 5141fbafc9bf5f1a7cbb6923bc719f595ce54dae Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Mon, 25 Dec 2017 12:10:06 +0800 +Subject: [PATCH 26/34] arm64: dts: allwinner: h6: add USB3 device nodes + +Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and +a custom PHY. + +Add device tree nodes for them. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Chen-Yu Tsai +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index c5c0608e67403..38784589558ca 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -420,6 +420,38 @@ + status = "disabled"; + }; + ++ dwc3: dwc3@5200000 { ++ compatible = "snps,dwc3"; ++ reg = <0x05200000 0x10000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_XHCI>, ++ <&ccu CLK_BUS_XHCI>, ++ <&rtc 0>; ++ clock-names = "ref", "bus_early", "suspend"; ++ resets = <&ccu RST_BUS_XHCI>; ++ /* ++ * The datasheet of the chip doesn't declare the ++ * peripheral function, and there's no boards known ++ * to have a USB Type-B port routed to the port. ++ * In addition, no one has tested the peripheral ++ * function yet. ++ * So set the dr_mode to "host" in the DTSI file. ++ */ ++ dr_mode = "host"; ++ phys = <&usb3phy>; ++ phy-names = "usb3-phy"; ++ status = "disabled"; ++ }; ++ ++ usb3phy: phy@5210000 { ++ compatible = "allwinner,sun50i-h6-usb3-phy"; ++ reg = <0x5210000 0x10000>; ++ clocks = <&ccu CLK_USB_PHY1>; ++ resets = <&ccu RST_USB_PHY1>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + ehci3: usb@5311000 { + compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; + reg = <0x05311000 0x100>; + +FFrom 19ed1005f6d1d2955c9e3e88c3fe037b46284ca8 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 26 Mar 2019 15:13:34 +0100 +Subject: [PATCH 32/34] arm64: dts: allwinner: h6: Add pin configs for uart1 + +Orange Pi 3 uses UART1 for bluetooth. Add pinconfigs so that +we can use them. + +Signed-off-by: Ondrej Jirman +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 5c5b1240c7790..dc785da9ce0a2 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -322,6 +322,16 @@ + pins = "PH0", "PH1"; + function = "uart0"; + }; ++ ++ uart1_pins: uart1-pins { ++ pins = "PG6", "PG7"; ++ function = "uart1"; ++ }; ++ ++ uart1_rts_cts_pins: uart1-rts-cts-pins { ++ pins = "PG8", "PG9"; ++ function = "uart1"; ++ }; + }; + + gic: interrupt-controller@3021000 { + +From 785248f1b1d89bbd8a25435f873bfa91c27fa123 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Wed, 27 Mar 2019 13:48:59 +0100 +Subject: [PATCH 33/34] arm64: dts: allwinner: orange-pi-3: Enable UART1 / + Bluetooth + +The board contains AP6256 WiFi/BT module that has its bluetooth +part connected to SoC's UART1 port. Enable this port, and add +node for the bluetooth device. + +Bluetooth part is named bcm4345c5. + +You'll need a BCM4345C5.hcd firmware file that can be found in +the Xulongs's repository for H6: + +https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 + +Mainline brcmbt driver expects the firmware at the following path +relative to the firmware directory: + + brcm/BCM4345C5.hcd + +Signed-off-by: Ondrej Jirman +--- + .../dts/allwinner/sun50i-h6-orangepi-3.dts | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index f795362f5b77e..d9e8610b5f83f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -15,6 +15,7 @@ + + aliases { + serial0 = &uart0; ++ serial1 = &uart1; + ethernet0 = &emac; + }; + +@@ -324,6 +325,24 @@ + status = "okay"; + }; + ++/* There's the BT part of the AP6256 connected to that UART */ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rtc 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ ++ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ ++ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ ++ max-speed = <1500000>; ++ }; ++}; ++ + &usb2otg { + /* + * This board doesn't have a controllable VBUS even though it + +From c74e4ba1e28d5808cda02b34eee59dc1a5f15a6d Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Wed, 27 Mar 2019 13:43:25 +0100 +Subject: [PATCH 34/34] arm64: dts: allwinner: orange-pi-3: Enable USB 3.0 host + support + +Enable Allwinner's USB 3.0 phy and the host controller. Orange Pi 3 +board has GL3510 USB 3.0 4-port hub connected to the SoC's USB 3.0 +port. All four ports are exposed via USB3-A connectors. The hub is +powered directly from DCIN/VCC-5V. + +Signed-off-by: Ondrej Jirman +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index d9e8610b5f83f..afee79fb88f18 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -126,6 +126,10 @@ + status = "okay"; + }; + ++&dwc3 { ++ status = "okay"; ++}; ++ + &ehci0 { + status = "okay"; + }; +@@ -359,3 +363,8 @@ + usb3_vbus-supply = <®_vcc5v>; + status = "okay"; + }; ++ ++&usb3phy { ++ phy-supply = <®_vcc5v>; ++ status = "okay"; ++}; diff --git a/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch b/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch deleted file mode 100644 index 68c1d5a8c8..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 9413130f5b213551519c97482462a6daea9a5343 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 2 Apr 2019 19:32:01 +0200 -Subject: [PATCH 1/2] clk: sunxi-ng: h6: Change CEC clock parent - -Signed-off-by: Jernej Skrabec ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -index daf78966555e..33980067b06e 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -@@ -656,6 +656,8 @@ static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; - static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { - { .index = 1, .div = 36621 }, - }; -+ -+#define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10 - static struct ccu_mux hdmi_cec_clk = { - .enable = BIT(31), - -@@ -1200,6 +1202,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) - val &= ~(GENMASK(21, 16) | BIT(0)); - writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); - -+ /* -+ * First clock parent (osc32K) is unusable for CEC. But since there -+ * is no good way to force parent switch (both run with same frequency), -+ * just set second clock parent here. -+ */ -+ val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG); -+ val |= BIT(24); -+ writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); -+ - return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc); - } - --- -2.21.0 - - -From eab64a1ccf6b7cda339fdfdbfa9e1973e4cc0c85 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 2 Apr 2019 21:15:45 +0200 -Subject: [PATCH 2/2] clk: sunxi-ng: h6: Allow video & vpu clocks to change - parent rate - -Video related clocks need to set rate as close as possible to the -requested one, so they should be able to change parent clock rate. - -VPU clock sometimes has to be set to higher than default parent clock -rate. This is requ - -Add CLK_SET_RATE_PARENT flag to tcon-lcd0, tcon-tv0 and ve. - -Signed-off-by: Jernej Skrabec ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -index 33980067b06e..3c32d7798f27 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -@@ -311,7 +311,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, - 0, 3, /* M */ - 24, 1, /* mux */ - BIT(31), /* gate */ -- 0); -+ CLK_SET_RATE_PARENT); - - static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", - 0x69c, BIT(0), 0); -@@ -691,7 +691,7 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", - tcon_lcd0_parents, 0xb60, - 24, 3, /* mux */ - BIT(31), /* gate */ -- 0); -+ CLK_SET_RATE_PARENT); - - static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", - 0xb7c, BIT(0), 0); -@@ -706,7 +706,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", - 8, 2, /* P */ - 24, 3, /* mux */ - BIT(31), /* gate */ -- 0); -+ CLK_SET_RATE_PARENT); - - static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", - 0xb9c, BIT(0), 0); --- -2.21.0 - diff --git a/projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch b/projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch new file mode 100644 index 0000000000..ce8c18bf06 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch @@ -0,0 +1,352 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 0e2ffdb87f..ad60ae0179 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -467,6 +467,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-orangepi-prime.dtb \ + sun50i-h5-orangepi-zero-plus2.dtb + dtb-$(CONFIG_MACH_SUN50I_H6) += \ ++ sun50i-h6-orangepi-3.dtb \ + sun50i-h6-orangepi-lite2.dtb \ + sun50i-h6-orangepi-one-plus.dtb \ + sun50i-h6-pine-h64.dtb +diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts +new file mode 100644 +index 0000000000..8070adc39b +--- /dev/null ++++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts +@@ -0,0 +1,316 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2019 Ondřej Jirman ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h6.dtsi" ++ ++#include ++ ++/ { ++ model = "OrangePi 3"; ++ compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ ethernet0 = &emac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ddc-supply = <®_ddc>; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ power { ++ label = "orangepi:red:power"; ++ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ ++ default-state = "on"; ++ }; ++ ++ status { ++ label = "orangepi:green:status"; ++ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ ++ }; ++ }; ++ ++ reg_ddc: ddc-io { ++ compatible = "regulator-fixed"; ++ regulator-name = "ddc-io"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ ++ }; ++ ++ reg_vcc5v: vcc5v { ++ /* board wide 5V supply directly from the DC jack */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_vcc33_wifi: vcc33-wifi { ++ /* Always on 3.3V regulator for WiFi and BT */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc33-wifi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_vcc_wifi_io: vcc-wifi-io { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-wifi-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_vcc33_wifi>; ++ }; ++ ++ /* ++ * The board uses 2.5V RGMII signalling. Power sequence to enable ++ * the phy is to enable GMAC-2V5 and GMAC-3V3 (aldo2) power rails ++ * at the same time and to wait 100ms. ++ */ ++ reg_gmac_2v5: gmac-2v5 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-2v5"; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ ++ ++ /* The real parent of gmac-2v5 is reg_vcc5v, but we need to ++ * enable two regulators to power the phy. This is one way ++ * to achieve that. ++ */ ++ vin-supply = <®_aldo2>; /* GMAC-3V3 */ ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-supply = <®_gmac_2v5>; ++ allwinner,rx-delay-ps = <1500>; ++ allwinner,tx-delay-ps = <700>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ ++ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ ++ reset-assert-us = <15000>; ++ reset-deassert-us = <40000>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_cldo1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_vcc_wifi_io>; ++}; ++ ++&r_i2c { ++ status = "okay"; ++ ++ axp805: pmic@36 { ++ compatible = "x-powers,axp805", "x-powers,axp806"; ++ reg = <0x36>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ x-powers,self-working-mode; ++ vina-supply = <®_vcc5v>; ++ vinb-supply = <®_vcc5v>; ++ vinc-supply = <®_vcc5v>; ++ vind-supply = <®_vcc5v>; ++ vine-supply = <®_vcc5v>; ++ aldoin-supply = <®_vcc5v>; ++ bldoin-supply = <®_vcc5v>; ++ cldoin-supply = <®_vcc5v>; ++ ++ regulators { ++ reg_aldo1: aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl-led-ir"; ++ }; ++ ++ reg_aldo2: aldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-audio-tv-ephy-mac"; ++ }; ++ ++ /* ALDO3 is shorted to CLDO1 */ ++ reg_aldo3: aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; ++ }; ++ ++ reg_bldo1: bldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc18-dram-bias-pll"; ++ }; ++ ++ reg_bldo2: bldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-efuse-pcie-hdmi-pc"; ++ }; ++ ++ bldo3 { ++ /* unused */ ++ }; ++ ++ bldo4 { ++ /* unused */ ++ }; ++ ++ reg_cldo1: cldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; ++ }; ++ ++ cldo2 { ++ /* unused */ ++ }; ++ ++ cldo3 { ++ /* unused */ ++ }; ++ ++ reg_dcdca: dcdca { ++ regulator-always-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1160000>; ++ regulator-name = "vdd-cpu"; ++ }; ++ ++ reg_dcdcc: dcdcc { ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <1080000>; ++ regulator-name = "vdd-gpu"; ++ }; ++ ++ reg_dcdcd: dcdcd { ++ regulator-always-on; ++ regulator-min-microvolt = <960000>; ++ regulator-max-microvolt = <960000>; ++ regulator-name = "vdd-sys"; ++ }; ++ ++ reg_dcdce: dcdce { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++ }; ++ ++ sw { ++ /* unused */ ++ }; ++ }; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++&usb2otg { ++ /* ++ * This board doesn't have a controllable VBUS even though it ++ * does have an ID pin. Using it as anything but a USB host is ++ * unsafe. ++ */ ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb2phy { ++ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ ++ usb0_vbus-supply = <®_vcc5v>; ++ usb3_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; +diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig +new file mode 100644 +index 0000000000..9a9cd28142 +--- /dev/null ++++ b/configs/orangepi_3_defconfig +@@ -0,0 +1,12 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I_H6=y ++CONFIG_MMC0_CD_PIN="PF6" ++# CONFIG_PSCI_RESET is not set ++CONFIG_NR_DRAM_BANKS=1 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3" diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index 7e23841e73..6c1e7b9f00 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1693,8 +1693,8 @@ CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y # CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_SUNXI=y -CONFIG_DWMAC_SUN8I=y +CONFIG_DWMAC_SUNXI=m +CONFIG_DWMAC_SUN8I=m CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_DWC_XLGMAC is not set CONFIG_NET_VENDOR_VIA=y @@ -2567,7 +2567,7 @@ CONFIG_ARM_SP805_WATCHDOG=y # CONFIG_ARM_SBSA_WATCHDOG is not set # CONFIG_CADENCE_WATCHDOG is not set # CONFIG_DW_WATCHDOG is not set -# CONFIG_SUNXI_WATCHDOG is not set +CONFIG_SUNXI_WATCHDOG=y # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_MAX77620_WATCHDOG is not set # CONFIG_MEN_A21_WDT is not set @@ -4856,6 +4856,7 @@ CONFIG_PHY_XGENE=y CONFIG_PHY_SUN4I_USB=y # CONFIG_PHY_SUN6I_MIPI_DPHY is not set # CONFIG_PHY_SUN9I_USB is not set +CONFIG_PHY_SUN50I_USB3=y # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_DP is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -5432,7 +5433,7 @@ CONFIG_DMA_CMA=y # # Default contiguous memory area size: # -CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_MBYTES=384 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set # CONFIG_CMA_SIZE_SEL_MIN is not set diff --git a/projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch b/projects/Allwinner/patches/linux/0002-backport-from-5.2.patch similarity index 62% rename from projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch rename to projects/Allwinner/patches/linux/0002-backport-from-5.2.patch index 738a3a4b50..fc35510d93 100644 --- a/projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch +++ b/projects/Allwinner/patches/linux/0002-backport-from-5.2.patch @@ -674,3 +674,370 @@ index b98add3cdedd..d0429c0e6b6b 100644 -- 2.21.0 +From ed19ec00d4d62a74857ad9c2ea1dbf9671ac3580 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:36:54 +0100 +Subject: [PATCH 1/6] dt-bindings: media: cedrus: Add H6 compatible + +This adds a compatible for H6. H6 VPU supports 10-bit HEVC decoding and +additional AFBC output format for HEVC. + +Signed-off-by: Jernej Skrabec +--- + Documentation/devicetree/bindings/media/cedrus.txt | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt +index bce0705df953..20c82fb0c343 100644 +--- a/Documentation/devicetree/bindings/media/cedrus.txt ++++ b/Documentation/devicetree/bindings/media/cedrus.txt +@@ -13,6 +13,7 @@ Required properties: + - "allwinner,sun8i-h3-video-engine" + - "allwinner,sun50i-a64-video-engine" + - "allwinner,sun50i-h5-video-engine" ++ - "allwinner,sun50i-h6-video-engine" + - reg : register base and length of VE; + - clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +-- +2.20.1 + + +From bb6b00e1225a5b382b723d3c2190429e15a4c607 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:45:38 +0100 +Subject: [PATCH 2/6] media: cedrus: Add a quirk for not setting DMA offset + +H6 VPU doesn't work if DMA offset is set. + +Add a quirk for it. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 3 +++ + drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 3 ++- + 2 files changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 4aedd24a9848..c57c04b41d2e 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -28,6 +28,8 @@ + + #define CEDRUS_CAPABILITY_UNTILED BIT(0) + ++#define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) ++ + enum cedrus_codec { + CEDRUS_CODEC_MPEG2, + +@@ -91,6 +93,7 @@ struct cedrus_dec_ops { + + struct cedrus_variant { + unsigned int capabilities; ++ unsigned int quirks; + }; + + struct cedrus_dev { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index 0acf219a8c91..fbfff7c1c771 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -177,7 +177,8 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + */ + + #ifdef PHYS_PFN_OFFSET +- dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; ++ if (!(variant->quirks & CEDRUS_QUIRK_NO_DMA_OFFSET)) ++ dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; + #endif + + ret = of_reserved_mem_device_init(dev->dev); +-- +2.20.1 + + +From 744c66f8c328ef40b6fb246f8b9f2daa9cce4d9d Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:47:33 +0100 +Subject: [PATCH 3/6] media: cedrus: Add support for H6 + +H6 has improved VPU. It supports 10-bit HEVC decoding and AFBC output +format for HEVC. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index ff11cbeba205..b98add3cdedd 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -396,6 +396,11 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, + }; + ++static const struct cedrus_variant sun50i_h6_cedrus_variant = { ++ .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, ++}; ++ + static const struct of_device_id cedrus_dt_match[] = { + { + .compatible = "allwinner,sun4i-a10-video-engine", +@@ -425,6 +430,10 @@ static const struct of_device_id cedrus_dt_match[] = { + .compatible = "allwinner,sun50i-h5-video-engine", + .data = &sun50i_h5_cedrus_variant, + }, ++ { ++ .compatible = "allwinner,sun50i-h6-video-engine", ++ .data = &sun50i_h6_cedrus_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, cedrus_dt_match); +-- +2.20.1 + + +From c1b3128ac98c05c0afde4e6e065d6b1f2ae1dfa7 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:59:27 +0100 +Subject: [PATCH 6/6] arm64: dts: allwinner: h6: Add Video Engine node + +This adds the Video engine node for H6. It can use whole DRAM range so +there is no need for reserved memory node. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 247dc0a5ce89..de4b7a1f1012 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -146,6 +146,17 @@ + }; + }; + ++ video-codec@1c0e000 { ++ compatible = "allwinner,sun50i-h6-video-engine"; ++ reg = <0x01c0e000 0x2000>; ++ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, ++ <&ccu CLK_MBUS_VE>; ++ clock-names = "ahb", "mod", "ram"; ++ resets = <&ccu RST_BUS_VE>; ++ interrupts = ; ++ allwinner,sram = <&ve_sram 1>; ++ }; ++ + syscon: syscon@3000000 { + compatible = "allwinner,sun50i-h6-system-control", + "allwinner,sun50i-a64-system-control"; +-- +2.20.1 + +From 87effaae9e90474546d441b9123bca824e670a0b Mon Sep 17 00:00:00 2001 +From: Fish Lin +Date: Thu, 28 Mar 2019 23:20:46 -0400 +Subject: [PATCH] media: v4l: add I / P frame min max QP definitions + +Add following V4L2 QP parameters for H.264: +* V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP +* V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP +* V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP +* V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP + +These controls will limit QP range for intra and inter frame, +provide more manual control to improve video encode quality. + +Signed-off-by: Fish Lin +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../media/uapi/v4l/ext-ctrls-codec.rst | 24 +++++++++++++++++++ + drivers/media/v4l2-core/v4l2-ctrls.c | 4 ++++ + include/uapi/linux/v4l2-controls.h | 4 ++++ + 3 files changed, 32 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +index 67a122339c0e..4a8446203085 100644 +--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst ++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +@@ -1055,6 +1055,30 @@ enum v4l2_mpeg_video_h264_entropy_mode - + Quantization parameter for an B frame for H264. Valid range: from 0 + to 51. + ++``V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP (integer)`` ++ Minimum quantization parameter for the H264 I frame to limit I frame ++ quality to a range. Valid range: from 0 to 51. If ++ V4L2_CID_MPEG_VIDEO_H264_MIN_QP is also set, the quantization parameter ++ should be chosen to meet both requirements. ++ ++``V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP (integer)`` ++ Maximum quantization parameter for the H264 I frame to limit I frame ++ quality to a range. Valid range: from 0 to 51. If ++ V4L2_CID_MPEG_VIDEO_H264_MAX_QP is also set, the quantization parameter ++ should be chosen to meet both requirements. ++ ++``V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP (integer)`` ++ Minimum quantization parameter for the H264 P frame to limit P frame ++ quality to a range. Valid range: from 0 to 51. If ++ V4L2_CID_MPEG_VIDEO_H264_MIN_QP is also set, the quantization parameter ++ should be chosen to meet both requirements. ++ ++``V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP (integer)`` ++ Maximum quantization parameter for the H264 P frame to limit P frame ++ quality to a range. Valid range: from 0 to 51. If ++ V4L2_CID_MPEG_VIDEO_H264_MAX_QP is also set, the quantization parameter ++ should be chosen to meet both requirements. ++ + ``V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (integer)`` + Quantization parameter for an I frame for MPEG4. Valid range: from 1 + to 31. +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index b1ae2e555c68..89a1fe564675 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -828,6 +828,10 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: + return "H264 Constrained Intra Pred"; + case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: return "H264 Chroma QP Index Offset"; ++ case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: return "H264 I-Frame Minimum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; +diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h +index 78816ec88751..37807f23231e 100644 +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -539,6 +539,10 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type { + #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) + #define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_MPEG_BASE+383) + #define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (V4L2_CID_MPEG_BASE+384) ++#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP (V4L2_CID_MPEG_BASE+385) ++#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP (V4L2_CID_MPEG_BASE+386) ++#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP (V4L2_CID_MPEG_BASE+387) ++#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP (V4L2_CID_MPEG_BASE+388) + #define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) + #define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) + #define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +-- +2.21.0 + +From 26fae7a41313506931c9be5f532c12d8d654f153 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 2 Apr 2019 23:06:22 +0200 +Subject: [PATCH] clk: sunxi-ng: h6: Preset hdmi-cec clock parent + +H6 manual and BSP clock driver both states that hdmi-cec clock has two +possible parents, osc32k and pll-periph0-2x with 36621 predivider. +Because pll-periph0-2x is always 1.2 GHz, both parents give same +hdmi-cec rate - 32768 Hz, which is exactly the rate needed for HDMI CEC +controller to operate correctly. + +However, for some reason, HDMI CEC controller doesn't work if default +parent (osc32k) is used. BSP HDMI driver also always use pll-periph0-2x +as hdmi-cec clock parent. + +In order to solve the issue, preset hdmi-cec clock parent to +pll-periph0-2x. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index daf78966555e..33980067b06e 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -656,6 +656,8 @@ static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; + static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { + { .index = 1, .div = 36621 }, + }; ++ ++#define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10 + static struct ccu_mux hdmi_cec_clk = { + .enable = BIT(31), + +@@ -1200,6 +1202,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) + val &= ~(GENMASK(21, 16) | BIT(0)); + writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); + ++ /* ++ * First clock parent (osc32K) is unusable for CEC. But since there ++ * is no good way to force parent switch (both run with same frequency), ++ * just set second clock parent here. ++ */ ++ val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG); ++ val |= BIT(24); ++ writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); ++ + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc); + } + +-- +2.21.0 + +From 6597ce3de9e443f0cab693496fc529f55ae6eb01 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Wed, 3 Apr 2019 17:14:03 +0200 +Subject: [PATCH] clk: sunxi-ng: h6: Allow video & vpu clocks to change parent + rate + +Video related clocks need to set rate as close as possible to the +requested one, so they should be able to change parent clock rate. + +When processing 4K video, VPU clock has to be set to higher rate than it +is default parent rate. Because of that, VPU clock should be able to +change parent clock rate. + +Add CLK_SET_RATE_PARENT flag to tcon-lcd0, tcon-tv0 and ve. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 33980067b06e..3c32d7798f27 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -311,7 +311,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, + 0, 3, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", + 0x69c, BIT(0), 0); +@@ -691,7 +691,7 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", + tcon_lcd0_parents, 0xb60, + 24, 3, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", + 0xb7c, BIT(0), 0); +@@ -706,7 +706,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", + 0xb9c, BIT(0), 0); +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0003-backport-from-5.3.patch b/projects/Allwinner/patches/linux/0003-backport-from-5.3.patch new file mode 100644 index 0000000000..b9e475980b --- /dev/null +++ b/projects/Allwinner/patches/linux/0003-backport-from-5.3.patch @@ -0,0 +1,2765 @@ +From 9bd1acf0cdd4dd78a130714ad42163eac20871a3 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 18 May 2019 18:24:04 +0200 +Subject: [PATCH] media: cedrus: Allow different mod clock rates + +Some VPU variants may run at higher clock speeds. They actually need +extra speed to be capable of decoding more complex codecs like HEVC or +bigger image sizes (4K). + +Expand variant structure with mod_rate information. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.c | 11 ++++++++--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 1 + + drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 2 +- + drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 -- + 4 files changed, 10 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index d0429c0e6b6b..9349a082a29c 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -369,36 +369,41 @@ static int cedrus_remove(struct platform_device *pdev) + } + + static const struct cedrus_variant sun4i_a10_cedrus_variant = { +- /* No particular capability. */ ++ .mod_rate = 320000000, + }; + + static const struct cedrus_variant sun5i_a13_cedrus_variant = { +- /* No particular capability. */ ++ .mod_rate = 320000000, + }; + + static const struct cedrus_variant sun7i_a20_cedrus_variant = { +- /* No particular capability. */ ++ .mod_rate = 320000000, + }; + + static const struct cedrus_variant sun8i_a33_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .mod_rate = 320000000, + }; + + static const struct cedrus_variant sun8i_h3_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .mod_rate = 402000000, + }; + + static const struct cedrus_variant sun50i_a64_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .mod_rate = 402000000, + }; + + static const struct cedrus_variant sun50i_h5_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .mod_rate = 402000000, + }; + + static const struct cedrus_variant sun50i_h6_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, + .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, ++ .mod_rate = 600000000, + }; + + static const struct of_device_id cedrus_dt_match[] = { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index c57c04b41d2e..25ee1f80f2c7 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -94,6 +94,7 @@ struct cedrus_dec_ops { + struct cedrus_variant { + unsigned int capabilities; + unsigned int quirks; ++ unsigned int mod_rate; + }; + + struct cedrus_dev { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index fbfff7c1c771..60406b2d4595 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -236,7 +236,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + goto err_sram; + } + +- ret = clk_set_rate(dev->mod_clk, CEDRUS_CLOCK_RATE_DEFAULT); ++ ret = clk_set_rate(dev->mod_clk, variant->mod_rate); + if (ret) { + dev_err(dev->dev, "Failed to set clock rate\n"); + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +index b43c77d54b95..27d0882397aa 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +@@ -16,8 +16,6 @@ + #ifndef _CEDRUS_HW_H_ + #define _CEDRUS_HW_H_ + +-#define CEDRUS_CLOCK_RATE_DEFAULT 320000000 +- + int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); + void cedrus_engine_disable(struct cedrus_dev *dev); + +-- +2.21.0 + +From 79084d4e9a6783688ce497b6d17e8ecf09950bf5 Mon Sep 17 00:00:00 2001 +From: Philipp Zabel +Date: Wed, 24 Apr 2019 12:43:47 +0200 +Subject: [PATCH] media: v4l2-ctrl: add MPEG-2 profile and level controls + +Add MPEG-2 CID definitions for profiles and levels defined in ITU-T Rec. +H.262. + +Signed-off-by: Philipp Zabel +Signed-off-by: Hans Verkuil +--- + .../media/uapi/v4l/ext-ctrls-codec.rst | 56 +++++++++++++++++++ + drivers/media/v4l2-core/v4l2-ctrls.c | 23 ++++++++ + include/uapi/linux/v4l2-controls.h | 18 ++++++ + 3 files changed, 97 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +index 4a8446203085..843c93e8e7bc 100644 +--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst ++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +@@ -759,6 +759,32 @@ enum v4l2_mpeg_video_h264_level - + + + ++.. _v4l2-mpeg-video-mpeg2-level: ++ ++``V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL`` ++ (enum) ++ ++enum v4l2_mpeg_video_mpeg2_level - ++ The level information for the MPEG2 elementary stream. Applicable to ++ MPEG2 codecs. Possible values are: ++ ++ ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ ++ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW`` ++ - Low Level (LL) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN`` ++ - Main Level (ML) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440`` ++ - High-1440 Level (H-14) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH`` ++ - High Level (HL) ++ ++ ++ + .. _v4l2-mpeg-video-mpeg4-level: + + ``V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL`` +@@ -845,6 +871,36 @@ enum v4l2_mpeg_video_h264_profile - + + + ++.. _v4l2-mpeg-video-mpeg2-profile: ++ ++``V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE`` ++ (enum) ++ ++enum v4l2_mpeg_video_mpeg2_profile - ++ The profile information for MPEG2. Applicable to MPEG2 codecs. ++ Possible values are: ++ ++ ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE`` ++ - Simple profile (SP) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN`` ++ - Main profile (MP) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SNR_SCALABLE`` ++ - SNR Scalable profile (SNR) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SPATIALLY_SCALABLE`` ++ - Spatially Scalable profile (Spt) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_HIGH`` ++ - High profile (HP) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_MULTIVIEW`` ++ - Multi-view profile (MVP) ++ ++ ++ + .. _v4l2-mpeg-video-mpeg4-profile: + + ``V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE`` +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 420e3fc237cd..3380accc24ed 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -406,6 +406,21 @@ const char * const *v4l2_ctrl_get_menu(u32 id) + "Explicit", + NULL, + }; ++ static const char * const mpeg_mpeg2_level[] = { ++ "Low", ++ "Main", ++ "High 1440", ++ "High", ++ NULL, ++ }; ++ static const char * const mpeg2_profile[] = { ++ "Simple", ++ "Main", ++ "SNR Scalable", ++ "Spatially Scalable", ++ "High", ++ NULL, ++ }; + static const char * const mpeg_mpeg4_level[] = { + "0", + "0b", +@@ -622,6 +637,10 @@ const char * const *v4l2_ctrl_get_menu(u32 id) + return h264_fp_arrangement_type; + case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: + return h264_fmo_map_type; ++ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: ++ return mpeg_mpeg2_level; ++ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: ++ return mpeg2_profile; + case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: + return mpeg_mpeg4_level; + case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE: +@@ -832,6 +851,8 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; ++ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; +@@ -1197,6 +1218,8 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC: + case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE: + case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: ++ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: ++ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: + case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: + case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE: + case V4L2_CID_JPEG_CHROMA_SUBSAMPLING: +diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h +index 37807f23231e..d9f2c76b71bb 100644 +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -404,6 +404,24 @@ enum v4l2_mpeg_video_multi_slice_mode { + #define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228) + #define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE+229) + ++/* CIDs for the MPEG-2 Part 2 (H.262) codec */ ++#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_BASE+270) ++enum v4l2_mpeg_video_mpeg2_level { ++ V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW = 0, ++ V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN = 1, ++ V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440 = 2, ++ V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH = 3, ++}; ++#define V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_BASE+271) ++enum v4l2_mpeg_video_mpeg2_profile { ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE = 0, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN = 1, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 2, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SPATIALLY_SCALABLE = 3, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_HIGH = 4, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_MULTIVIEW = 5, ++}; ++ + /* CIDs for the FWHT codec as used by the vicodec driver. */ + #define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_MPEG_BASE + 290) + #define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_MPEG_BASE + 291) +-- +2.21.0 + +From e5929e797865802d8124a20de14f202ec143cafd Mon Sep 17 00:00:00 2001 +From: Pawel Osciak +Date: Fri, 24 May 2019 11:20:28 +0200 +Subject: [PATCH 05/12] media: uapi: Add H264 low-level decoder API compound + controls. + +Stateless video codecs will require both the H264 metadata and slices in +order to be able to decode frames. + +This introduces the definitions for the structures used to pass the +metadata from the userspace to the kernel. + +Reviewed-by: Paul Kocialkowski +Reviewed-by: Tomasz Figa +Signed-off-by: Pawel Osciak +Signed-off-by: Guenter Roeck +Co-developed-by: Maxime Ripard +Signed-off-by: Maxime Ripard +Signed-off-by: Hans Verkuil +--- + Documentation/media/uapi/v4l/biblio.rst | 9 + + .../media/uapi/v4l/ext-ctrls-codec.rst | 569 ++++++++++++++++++ + .../media/uapi/v4l/vidioc-queryctrl.rst | 30 + + .../media/videodev2.h.rst.exceptions | 5 + + drivers/media/v4l2-core/v4l2-ctrls.c | 42 ++ + include/media/v4l2-ctrls.h | 13 +- + 6 files changed, 667 insertions(+), 1 deletion(-) + +diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst +index ec33768c055e..8f4eb8823d82 100644 +--- a/Documentation/media/uapi/v4l/biblio.rst ++++ b/Documentation/media/uapi/v4l/biblio.rst +@@ -122,6 +122,15 @@ ITU BT.1119 + + :author: International Telecommunication Union (http://www.itu.ch) + ++.. _h264: ++ ++ITU-T Rec. H.264 Specification (04/2017 Edition) ++================================================ ++ ++:title: ITU-T Recommendation H.264 "Advanced Video Coding for Generic Audiovisual Services" ++ ++:author: International Telecommunication Union (http://www.itu.ch) ++ + .. _jfif: + + JFIF +diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +index 843c93e8e7bc..b0c178f0ff9b 100644 +--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst ++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +@@ -1451,6 +1451,575 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - + - Layer number + + ++.. _v4l2-mpeg-h264: ++ ++``V4L2_CID_MPEG_VIDEO_H264_SPS (struct)`` ++ Specifies the sequence parameter set (as extracted from the ++ bitstream) for the associated H264 slice data. This includes the ++ necessary parameters for configuring a stateless hardware decoding ++ pipeline for H264. The bitstream parameters are defined according ++ to :ref:`h264`, section 7.4.2.1.1 "Sequence Parameter Set Data ++ Semantics". For further documentation, refer to the above ++ specification, unless there is an explicit comment stating ++ otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_h264_sps ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_sps ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``profile_idc`` ++ - ++ * - __u8 ++ - ``constraint_set_flags`` ++ - See :ref:`Sequence Parameter Set Constraints Set Flags ` ++ * - __u8 ++ - ``level_idc`` ++ - ++ * - __u8 ++ - ``seq_parameter_set_id`` ++ - ++ * - __u8 ++ - ``chroma_format_idc`` ++ - ++ * - __u8 ++ - ``bit_depth_luma_minus8`` ++ - ++ * - __u8 ++ - ``bit_depth_chroma_minus8`` ++ - ++ * - __u8 ++ - ``log2_max_frame_num_minus4`` ++ - ++ * - __u8 ++ - ``pic_order_cnt_type`` ++ - ++ * - __u8 ++ - ``log2_max_pic_order_cnt_lsb_minus4`` ++ - ++ * - __u8 ++ - ``max_num_ref_frames`` ++ - ++ * - __u8 ++ - ``num_ref_frames_in_pic_order_cnt_cycle`` ++ - ++ * - __s32 ++ - ``offset_for_ref_frame[255]`` ++ - ++ * - __s32 ++ - ``offset_for_non_ref_pic`` ++ - ++ * - __s32 ++ - ``offset_for_top_to_bottom_field`` ++ - ++ * - __u16 ++ - ``pic_width_in_mbs_minus1`` ++ - ++ * - __u16 ++ - ``pic_height_in_map_units_minus1`` ++ - ++ * - __u32 ++ - ``flags`` ++ - See :ref:`Sequence Parameter Set Flags ` ++ ++.. _h264_sps_constraints_set_flags: ++ ++``Sequence Parameter Set Constraints Set Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET0_FLAG`` ++ - 0x00000001 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET1_FLAG`` ++ - 0x00000002 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET2_FLAG`` ++ - 0x00000004 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET3_FLAG`` ++ - 0x00000008 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET4_FLAG`` ++ - 0x00000010 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET5_FLAG`` ++ - 0x00000020 ++ - ++ ++.. _h264_sps_flags: ++ ++``Sequence Parameter Set Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE`` ++ - 0x00000001 ++ - ++ * - ``V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS`` ++ - 0x00000002 ++ - ++ * - ``V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO`` ++ - 0x00000004 ++ - ++ * - ``V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED`` ++ - 0x00000008 ++ - ++ * - ``V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY`` ++ - 0x00000010 ++ - ++ * - ``V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD`` ++ - 0x00000020 ++ - ++ * - ``V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE`` ++ - 0x00000040 ++ - ++ ++``V4L2_CID_MPEG_VIDEO_H264_PPS (struct)`` ++ Specifies the picture parameter set (as extracted from the ++ bitstream) for the associated H264 slice data. This includes the ++ necessary parameters for configuring a stateless hardware decoding ++ pipeline for H264. The bitstream parameters are defined according ++ to :ref:`h264`, section 7.4.2.2 "Picture Parameter Set RBSP ++ Semantics". For further documentation, refer to the above ++ specification, unless there is an explicit comment stating ++ otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_h264_pps ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_pps ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``pic_parameter_set_id`` ++ - ++ * - __u8 ++ - ``seq_parameter_set_id`` ++ - ++ * - __u8 ++ - ``num_slice_groups_minus1`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l0_default_active_minus1`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l1_default_active_minus1`` ++ - ++ * - __u8 ++ - ``weighted_bipred_idc`` ++ - ++ * - __s8 ++ - ``pic_init_qp_minus26`` ++ - ++ * - __s8 ++ - ``pic_init_qs_minus26`` ++ - ++ * - __s8 ++ - ``chroma_qp_index_offset`` ++ - ++ * - __s8 ++ - ``second_chroma_qp_index_offset`` ++ - ++ * - __u16 ++ - ``flags`` ++ - See :ref:`Picture Parameter Set Flags ` ++ ++.. _h264_pps_flags: ++ ++``Picture Parameter Set Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE`` ++ - 0x00000001 ++ - ++ * - ``V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT`` ++ - 0x00000002 ++ - ++ * - ``V4L2_H264_PPS_FLAG_WEIGHTED_PRED`` ++ - 0x00000004 ++ - ++ * - ``V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT`` ++ - 0x00000008 ++ - ++ * - ``V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED`` ++ - 0x00000010 ++ - ++ * - ``V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT`` ++ - 0x00000020 ++ - ++ * - ``V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE`` ++ - 0x00000040 ++ - ++ * - ``V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT`` ++ - 0x00000080 ++ - ++ ++``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (struct)`` ++ Specifies the scaling matrix (as extracted from the bitstream) for ++ the associated H264 slice data. The bitstream parameters are ++ defined according to :ref:`h264`, section 7.4.2.1.1.1 "Scaling ++ List Semantics".For further documentation, refer to the above ++ specification, unless there is an explicit comment stating ++ otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_h264_scaling_matrix ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_scaling_matrix ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``scaling_list_4x4[6][16]`` ++ - ++ * - __u8 ++ - ``scaling_list_8x8[6][64]`` ++ - ++ ++``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (struct)`` ++ Specifies the slice parameters (as extracted from the bitstream) ++ for the associated H264 slice data. This includes the necessary ++ parameters for configuring a stateless hardware decoding pipeline ++ for H264. The bitstream parameters are defined according to ++ :ref:`h264`, section 7.4.3 "Slice Header Semantics". For further ++ documentation, refer to the above specification, unless there is ++ an explicit comment stating otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API ++ and it is expected to change. ++ ++ This structure is expected to be passed as an array, with one ++ entry for each slice included in the bitstream buffer. ++ ++.. c:type:: v4l2_ctrl_h264_slice_params ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_slice_params ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``size`` ++ - ++ * - __u32 ++ - ``header_bit_size`` ++ - ++ * - __u16 ++ - ``first_mb_in_slice`` ++ - ++ * - __u8 ++ - ``slice_type`` ++ - ++ * - __u8 ++ - ``pic_parameter_set_id`` ++ - ++ * - __u8 ++ - ``colour_plane_id`` ++ - ++ * - __u8 ++ - ``redundant_pic_cnt`` ++ - ++ * - __u16 ++ - ``frame_num`` ++ - ++ * - __u16 ++ - ``idr_pic_id`` ++ - ++ * - __u16 ++ - ``pic_order_cnt_lsb`` ++ - ++ * - __s32 ++ - ``delta_pic_order_cnt_bottom`` ++ - ++ * - __s32 ++ - ``delta_pic_order_cnt0`` ++ - ++ * - __s32 ++ - ``delta_pic_order_cnt1`` ++ - ++ * - struct :c:type:`v4l2_h264_pred_weight_table` ++ - ``pred_weight_table`` ++ - ++ * - __u32 ++ - ``dec_ref_pic_marking_bit_size`` ++ - ++ * - __u32 ++ - ``pic_order_cnt_bit_size`` ++ - ++ * - __u8 ++ - ``cabac_init_idc`` ++ - ++ * - __s8 ++ - ``slice_qp_delta`` ++ - ++ * - __s8 ++ - ``slice_qs_delta`` ++ - ++ * - __u8 ++ - ``disable_deblocking_filter_idc`` ++ - ++ * - __s8 ++ - ``slice_alpha_c0_offset_div2`` ++ - ++ * - __s8 ++ - ``slice_beta_offset_div2`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l0_active_minus1`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l1_active_minus1`` ++ - ++ * - __u32 ++ - ``slice_group_change_cycle`` ++ - ++ * - __u8 ++ - ``ref_pic_list0[32]`` ++ - Reference picture list after applying the per-slice modifications ++ * - __u8 ++ - ``ref_pic_list1[32]`` ++ - Reference picture list after applying the per-slice modifications ++ * - __u32 ++ - ``flags`` ++ - See :ref:`Slice Parameter Flags ` ++ ++.. _h264_slice_flags: ++ ++``Slice Parameter Set Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_SLICE_FLAG_FIELD_PIC`` ++ - 0x00000001 ++ - ++ * - ``V4L2_H264_SLICE_FLAG_BOTTOM_FIELD`` ++ - 0x00000002 ++ - ++ * - ``V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED`` ++ - 0x00000004 ++ - ++ * - ``V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH`` ++ - 0x00000008 ++ - ++ ++``Prediction Weight Table`` ++ ++ The bitstream parameters are defined according to :ref:`h264`, ++ section 7.4.3.2 "Prediction Weight Table Semantics". For further ++ documentation, refer to the above specification, unless there is ++ an explicit comment stating otherwise. ++ ++.. c:type:: v4l2_h264_pred_weight_table ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_h264_pred_weight_table ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u16 ++ - ``luma_log2_weight_denom`` ++ - ++ * - __u16 ++ - ``chroma_log2_weight_denom`` ++ - ++ * - struct :c:type:`v4l2_h264_weight_factors` ++ - ``weight_factors[2]`` ++ - The weight factors at index 0 are the weight factors for the reference ++ list 0, the one at index 1 for the reference list 1. ++ ++.. c:type:: v4l2_h264_weight_factors ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_h264_weight_factors ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __s16 ++ - ``luma_weight[32]`` ++ - ++ * - __s16 ++ - ``luma_offset[32]`` ++ - ++ * - __s16 ++ - ``chroma_weight[32][2]`` ++ - ++ * - __s16 ++ - ``chroma_offset[32][2]`` ++ - ++ ++``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (struct)`` ++ Specifies the decode parameters (as extracted from the bitstream) ++ for the associated H264 slice data. This includes the necessary ++ parameters for configuring a stateless hardware decoding pipeline ++ for H264. The bitstream parameters are defined according to ++ :ref:`h264`. For further documentation, refer to the above ++ specification, unless there is an explicit comment stating ++ otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_h264_decode_params ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_decode_params ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``num_slices`` ++ - Number of slices needed to decode the current frame ++ * - __u32 ++ - ``nal_ref_idc`` ++ - NAL reference ID value coming from the NAL Unit header ++ * - __u8 ++ - ``ref_pic_list_p0[32]`` ++ - Backward reference list used by P-frames in the original bitstream order ++ * - __u8 ++ - ``ref_pic_list_b0[32]`` ++ - Backward reference list used by B-frames in the original bitstream order ++ * - __u8 ++ - ``ref_pic_list_b1[32]`` ++ - Forward reference list used by B-frames in the original bitstream order ++ * - __s32 ++ - ``top_field_order_cnt`` ++ - Picture Order Count for the coded top field ++ * - __s32 ++ - ``bottom_field_order_cnt`` ++ - Picture Order Count for the coded bottom field ++ * - __u32 ++ - ``flags`` ++ - See :ref:`Decode Parameters Flags ` ++ * - struct :c:type:`v4l2_h264_dpb_entry` ++ - ``dpb[16]`` ++ - ++ ++.. _h264_decode_params_flags: ++ ++``Decode Parameters Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC`` ++ - 0x00000001 ++ - That picture is an IDR picture ++ ++.. c:type:: v4l2_h264_dpb_entry ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_h264_dpb_entry ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u64 ++ - ``reference_ts`` ++ - Timestamp of the V4L2 capture buffer to use as reference, used ++ with B-coded and P-coded frames. The timestamp refers to the ++ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the ++ :c:func:`v4l2_timeval_to_ns()` function to convert the struct ++ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. ++ * - __u16 ++ - ``frame_num`` ++ - ++ * - __u16 ++ - ``pic_num`` ++ - ++ * - __s32 ++ - ``top_field_order_cnt`` ++ - ++ * - __s32 ++ - ``bottom_field_order_cnt`` ++ - ++ * - __u32 ++ - ``flags`` ++ - See :ref:`DPB Entry Flags ` ++ ++.. _h264_dpb_flags: ++ ++``DPB Entries Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_DPB_ENTRY_FLAG_VALID`` ++ - 0x00000001 ++ - The DPB entry is valid and should be considered ++ * - ``V4L2_H264_DPB_ENTRY_FLAG_ACTIVE`` ++ - 0x00000002 ++ - The DPB entry is currently being used as a reference frame ++ * - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM`` ++ - 0x00000004 ++ - The DPB entry is a long term reference frame + + .. _v4l2-mpeg-mpeg2: + +diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +index f824162d0ea9..dc500632095d 100644 +--- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst ++++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +@@ -443,6 +443,36 @@ See also the examples in :ref:`control`. + - n/a + - A struct :c:type:`v4l2_ctrl_mpeg2_quantization`, containing MPEG-2 + quantization matrices for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SPS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_sps`, containing H264 ++ sequence parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_PPS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_pps`, containing H264 ++ picture parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SCALING_MATRIX`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_scaling_matrix`, containing H264 ++ scaling matrices for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SLICE_PARAMS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_slice_params`, containing H264 ++ slice parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_DECODE_PARAMS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 ++ decode parameters for stateless video decoders. + + .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| + +diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions +index 64d348e67df9..55cbe324b9fc 100644 +--- a/Documentation/media/videodev2.h.rst.exceptions ++++ b/Documentation/media/videodev2.h.rst.exceptions +@@ -136,6 +136,11 @@ replace symbol V4L2_CTRL_TYPE_U32 :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_U8 :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_MPEG2_QUANTIZATION :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SPS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` + + # V4L2 capability defines + replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 3380accc24ed..b72dc54ba638 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -851,6 +851,11 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_H264_SPS: return "H264 Sequence Parameter Set"; ++ case V4L2_CID_MPEG_VIDEO_H264_PPS: return "H264 Picture Parameter Set"; ++ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: return "H264 Scaling Matrix"; ++ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters"; ++ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters"; + case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; + case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; +@@ -1337,6 +1342,21 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: + *type = V4L2_CTRL_TYPE_FWHT_PARAMS; + break; ++ case V4L2_CID_MPEG_VIDEO_H264_SPS: ++ *type = V4L2_CTRL_TYPE_H264_SPS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_PPS: ++ *type = V4L2_CTRL_TYPE_H264_PPS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: ++ *type = V4L2_CTRL_TYPE_H264_SCALING_MATRIX; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: ++ *type = V4L2_CTRL_TYPE_H264_SLICE_PARAMS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: ++ *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; ++ break; + default: + *type = V4L2_CTRL_TYPE_INTEGER; + break; +@@ -1706,6 +1726,13 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, + case V4L2_CTRL_TYPE_FWHT_PARAMS: + return 0; + ++ case V4L2_CTRL_TYPE_H264_SPS: ++ case V4L2_CTRL_TYPE_H264_PPS: ++ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: ++ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: ++ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: ++ return 0; ++ + default: + return -EINVAL; + } +@@ -2289,6 +2316,21 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_FWHT_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_fwht_params); + break; ++ case V4L2_CTRL_TYPE_H264_SPS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_sps); ++ break; ++ case V4L2_CTRL_TYPE_H264_PPS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_pps); ++ break; ++ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: ++ elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix); ++ break; ++ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_slice_params); ++ break; ++ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); ++ break; + default: + if (type < V4L2_CTRL_COMPOUND_TYPES) + elem_size = sizeof(s32); +diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h +index ee026387f513..a8aede26491e 100644 +--- a/include/media/v4l2-ctrls.h ++++ b/include/media/v4l2-ctrls.h +@@ -23,11 +23,12 @@ + #include + + /* +- * Include the mpeg2 and fwht stateless codec compound control definitions. ++ * Include the stateless codec compound control definitions. + * This will move to the public headers once this API is fully stable. + */ + #include + #include ++#include + + /* forward references */ + struct file; +@@ -51,6 +52,11 @@ struct poll_table_struct; + * @p_mpeg2_slice_params: Pointer to a MPEG2 slice parameters structure. + * @p_mpeg2_quantization: Pointer to a MPEG2 quantization data structure. + * @p_fwht_params: Pointer to a FWHT stateless parameters structure. ++ * @p_h264_sps: Pointer to a struct v4l2_ctrl_h264_sps. ++ * @p_h264_pps: Pointer to a struct v4l2_ctrl_h264_pps. ++ * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. ++ * @p_h264_slice_params: Pointer to a struct v4l2_ctrl_h264_slice_params. ++ * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. + * @p: Pointer to a compound value. + */ + union v4l2_ctrl_ptr { +@@ -63,6 +69,11 @@ union v4l2_ctrl_ptr { + struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; + struct v4l2_ctrl_mpeg2_quantization *p_mpeg2_quantization; + struct v4l2_ctrl_fwht_params *p_fwht_params; ++ struct v4l2_ctrl_h264_sps *p_h264_sps; ++ struct v4l2_ctrl_h264_pps *p_h264_pps; ++ struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; ++ struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; ++ struct v4l2_ctrl_h264_decode_params *p_h264_decode_params; + void *p; + }; + +-- +2.21.0 + +From 973e931fe8eefc32616f8eadadd0a018cbd096b5 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 24 May 2019 11:20:29 +0200 +Subject: [PATCH 06/12] media: pixfmt: Add H264 Slice format + +The H264_SLICE_RAW format is meant to hold the parsed slice data without +the start code. This will be needed by stateless decoders. + +Signed-off-by: Maxime Ripard +Signed-off-by: Hans Verkuil +--- + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + + include/media/h264-ctrls.h | 197 +++++++++++++++++++++++++++ + 2 files changed, 198 insertions(+) + create mode 100644 include/media/h264-ctrls.h + +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index ac87c3e37280..f6e1254064d2 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1325,6 +1325,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + case V4L2_PIX_FMT_H264: descr = "H.264"; break; + case V4L2_PIX_FMT_H264_NO_SC: descr = "H.264 (No Start Codes)"; break; + case V4L2_PIX_FMT_H264_MVC: descr = "H.264 MVC"; break; ++ case V4L2_PIX_FMT_H264_SLICE_RAW: descr = "H.264 Parsed Slice Data"; break; + case V4L2_PIX_FMT_H263: descr = "H.263"; break; + case V4L2_PIX_FMT_MPEG1: descr = "MPEG-1 ES"; break; + case V4L2_PIX_FMT_MPEG2: descr = "MPEG-2 ES"; break; +diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h +new file mode 100644 +index 000000000000..e1404d78d6ff +--- /dev/null ++++ b/include/media/h264-ctrls.h +@@ -0,0 +1,197 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * These are the H.264 state controls for use with stateless H.264 ++ * codec drivers. ++ * ++ * It turns out that these structs are not stable yet and will undergo ++ * more changes. So keep them private until they are stable and ready to ++ * become part of the official public API. ++ */ ++ ++#ifndef _H264_CTRLS_H_ ++#define _H264_CTRLS_H_ ++ ++#include ++ ++/* Our pixel format isn't stable at the moment */ ++#define V4L2_PIX_FMT_H264_SLICE_RAW v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ ++ ++/* ++ * This is put insanely high to avoid conflicting with controls that ++ * would be added during the phase where those controls are not ++ * stable. It should be fixed eventually. ++ */ ++#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+1000) ++#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+1001) ++#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) ++#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) ++#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) ++ ++/* enum v4l2_ctrl_type type values */ ++#define V4L2_CTRL_TYPE_H264_SPS 0x0110 ++#define V4L2_CTRL_TYPE_H264_PPS 0x0111 ++#define V4L2_CTRL_TYPE_H264_SCALING_MATRIX 0x0112 ++#define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 ++#define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 ++ ++#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 ++#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 ++#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 ++#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 ++#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 ++#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 ++ ++#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 ++#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 ++#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 ++#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 ++#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 ++#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 ++#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 ++ ++struct v4l2_ctrl_h264_sps { ++ __u8 profile_idc; ++ __u8 constraint_set_flags; ++ __u8 level_idc; ++ __u8 seq_parameter_set_id; ++ __u8 chroma_format_idc; ++ __u8 bit_depth_luma_minus8; ++ __u8 bit_depth_chroma_minus8; ++ __u8 log2_max_frame_num_minus4; ++ __u8 pic_order_cnt_type; ++ __u8 log2_max_pic_order_cnt_lsb_minus4; ++ __u8 max_num_ref_frames; ++ __u8 num_ref_frames_in_pic_order_cnt_cycle; ++ __s32 offset_for_ref_frame[255]; ++ __s32 offset_for_non_ref_pic; ++ __s32 offset_for_top_to_bottom_field; ++ __u16 pic_width_in_mbs_minus1; ++ __u16 pic_height_in_map_units_minus1; ++ __u32 flags; ++}; ++ ++#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 ++#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 ++#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 ++#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 ++#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 ++#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 ++#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 ++#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 ++ ++struct v4l2_ctrl_h264_pps { ++ __u8 pic_parameter_set_id; ++ __u8 seq_parameter_set_id; ++ __u8 num_slice_groups_minus1; ++ __u8 num_ref_idx_l0_default_active_minus1; ++ __u8 num_ref_idx_l1_default_active_minus1; ++ __u8 weighted_bipred_idc; ++ __s8 pic_init_qp_minus26; ++ __s8 pic_init_qs_minus26; ++ __s8 chroma_qp_index_offset; ++ __s8 second_chroma_qp_index_offset; ++ __u16 flags; ++}; ++ ++struct v4l2_ctrl_h264_scaling_matrix { ++ __u8 scaling_list_4x4[6][16]; ++ __u8 scaling_list_8x8[6][64]; ++}; ++ ++struct v4l2_h264_weight_factors { ++ __s16 luma_weight[32]; ++ __s16 luma_offset[32]; ++ __s16 chroma_weight[32][2]; ++ __s16 chroma_offset[32][2]; ++}; ++ ++struct v4l2_h264_pred_weight_table { ++ __u16 luma_log2_weight_denom; ++ __u16 chroma_log2_weight_denom; ++ struct v4l2_h264_weight_factors weight_factors[2]; ++}; ++ ++#define V4L2_H264_SLICE_TYPE_P 0 ++#define V4L2_H264_SLICE_TYPE_B 1 ++#define V4L2_H264_SLICE_TYPE_I 2 ++#define V4L2_H264_SLICE_TYPE_SP 3 ++#define V4L2_H264_SLICE_TYPE_SI 4 ++ ++#define V4L2_H264_SLICE_FLAG_FIELD_PIC 0x01 ++#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD 0x02 ++#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 ++#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x08 ++ ++struct v4l2_ctrl_h264_slice_params { ++ /* Size in bytes, including header */ ++ __u32 size; ++ /* Offset in bits to slice_data() from the beginning of this slice. */ ++ __u32 header_bit_size; ++ ++ __u16 first_mb_in_slice; ++ __u8 slice_type; ++ __u8 pic_parameter_set_id; ++ __u8 colour_plane_id; ++ __u8 redundant_pic_cnt; ++ __u16 frame_num; ++ __u16 idr_pic_id; ++ __u16 pic_order_cnt_lsb; ++ __s32 delta_pic_order_cnt_bottom; ++ __s32 delta_pic_order_cnt0; ++ __s32 delta_pic_order_cnt1; ++ ++ struct v4l2_h264_pred_weight_table pred_weight_table; ++ /* Size in bits of dec_ref_pic_marking() syntax element. */ ++ __u32 dec_ref_pic_marking_bit_size; ++ /* Size in bits of pic order count syntax. */ ++ __u32 pic_order_cnt_bit_size; ++ ++ __u8 cabac_init_idc; ++ __s8 slice_qp_delta; ++ __s8 slice_qs_delta; ++ __u8 disable_deblocking_filter_idc; ++ __s8 slice_alpha_c0_offset_div2; ++ __s8 slice_beta_offset_div2; ++ __u8 num_ref_idx_l0_active_minus1; ++ __u8 num_ref_idx_l1_active_minus1; ++ __u32 slice_group_change_cycle; ++ ++ /* ++ * Entries on each list are indices into ++ * v4l2_ctrl_h264_decode_params.dpb[]. ++ */ ++ __u8 ref_pic_list0[32]; ++ __u8 ref_pic_list1[32]; ++ ++ __u32 flags; ++}; ++ ++#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 ++#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 ++#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 ++ ++struct v4l2_h264_dpb_entry { ++ __u64 reference_ts; ++ __u16 frame_num; ++ __u16 pic_num; ++ /* Note that field is indicated by v4l2_buffer.field */ ++ __s32 top_field_order_cnt; ++ __s32 bottom_field_order_cnt; ++ __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ ++}; ++ ++#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 ++ ++struct v4l2_ctrl_h264_decode_params { ++ struct v4l2_h264_dpb_entry dpb[16]; ++ __u16 num_slices; ++ __u16 nal_ref_idc; ++ __u8 ref_pic_list_p0[32]; ++ __u8 ref_pic_list_b0[32]; ++ __u8 ref_pic_list_b1[32]; ++ __s32 top_field_order_cnt; ++ __s32 bottom_field_order_cnt; ++ __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ ++}; ++ ++#endif +-- +2.21.0 + +From 129c7799b038de2a4fa90e6cff2bbb843187b06f Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 24 May 2019 11:20:30 +0200 +Subject: [PATCH 07/12] media: pixfmt: Add H264_SLICE_RAW format documentation + +The H264_SLICE_RAW format introduced before is meant for stateless +decoders that will need the H264 parsed slice data without the start code. + +Let's document it. + +Signed-off-by: Maxime Ripard +Signed-off-by: Hans Verkuil +--- + .../media/uapi/v4l/pixfmt-compressed.rst | 25 +++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +index 6c961cfb74da..4b701fc7653e 100644 +--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst ++++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +@@ -52,6 +52,31 @@ Compressed Formats + - ``V4L2_PIX_FMT_H264_MVC`` + - 'M264' + - H264 MVC video elementary stream. ++ * .. _V4L2-PIX-FMT-H264-SLICE-RAW: ++ ++ - ``V4L2_PIX_FMT_H264_SLICE_RAW`` ++ - 'S264' ++ - H264 parsed slice data, without the start code and as ++ extracted from the H264 bitstream. This format is adapted for ++ stateless video decoders that implement an H264 pipeline ++ (using the :ref:`mem2mem` and :ref:`media-request-api`). ++ Metadata associated with the frame to decode are required to ++ be passed through the ``V4L2_CID_MPEG_VIDEO_H264_SPS``, ++ ``V4L2_CID_MPEG_VIDEO_H264_PPS``, ++ ``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``, ++ ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS`` and ++ ``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS`` controls. See the ++ :ref:`associated Codec Control IDs `. Exactly ++ one output and one capture buffer must be provided for use ++ with this pixel format. The output buffer must contain the ++ appropriate number of macroblocks to decode a full ++ corresponding frame to the matching capture buffer. ++ ++ .. note:: ++ ++ This format is not yet part of the public kernel API and it ++ is expected to change. ++ + * .. _V4L2-PIX-FMT-H263: + + - ``V4L2_PIX_FMT_H263`` +-- +2.21.0 + +From 83b448edec51503daf61a823643a50db5e68cb15 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 24 May 2019 11:20:31 +0200 +Subject: [PATCH 08/12] media: cedrus: Add H264 decoding support + +Introduce some basic H264 decoding support in cedrus. So far, only the +baseline profile videos have been tested, and some more advanced features +used in higher profiles are not even implemented. + +Reviewed-by: Jernej Skrabec +Reviewed-by: Paul Kocialkowski +Signed-off-by: Maxime Ripard +Signed-off-by: Hans Verkuil +--- + drivers/staging/media/sunxi/cedrus/Makefile | 3 +- + drivers/staging/media/sunxi/cedrus/cedrus.c | 31 + + drivers/staging/media/sunxi/cedrus/cedrus.h | 38 +- + .../staging/media/sunxi/cedrus/cedrus_dec.c | 13 + + .../staging/media/sunxi/cedrus/cedrus_h264.c | 576 ++++++++++++++++++ + .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 + + .../staging/media/sunxi/cedrus/cedrus_regs.h | 91 +++ + .../staging/media/sunxi/cedrus/cedrus_video.c | 9 + + 8 files changed, 763 insertions(+), 2 deletions(-) + create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h264.c + +diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile +index 808842f0119e..c85ac6db0302 100644 +--- a/drivers/staging/media/sunxi/cedrus/Makefile ++++ b/drivers/staging/media/sunxi/cedrus/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o + +-sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o cedrus_mpeg2.o ++sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ ++ cedrus_mpeg2.o cedrus_h264.o +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index 9349a082a29c..370937edfc14 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -40,6 +40,36 @@ static const struct cedrus_control cedrus_controls[] = { + .codec = CEDRUS_CODEC_MPEG2, + .required = false, + }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_decode_params), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_slice_params), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_sps), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_pps), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, + }; + + #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) +@@ -278,6 +308,7 @@ static int cedrus_probe(struct platform_device *pdev) + } + + dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; ++ dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; + + mutex_init(&dev->dev_mutex); + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 25ee1f80f2c7..3f476d0fd981 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -32,7 +32,7 @@ + + enum cedrus_codec { + CEDRUS_CODEC_MPEG2, +- ++ CEDRUS_CODEC_H264, + CEDRUS_CODEC_LAST, + }; + +@@ -42,6 +42,12 @@ enum cedrus_irq_status { + CEDRUS_IRQ_OK, + }; + ++enum cedrus_h264_pic_type { ++ CEDRUS_H264_PIC_TYPE_FRAME = 0, ++ CEDRUS_H264_PIC_TYPE_FIELD, ++ CEDRUS_H264_PIC_TYPE_MBAFF, ++}; ++ + struct cedrus_control { + u32 id; + u32 elem_size; +@@ -49,6 +55,14 @@ struct cedrus_control { + unsigned char required:1; + }; + ++struct cedrus_h264_run { ++ const struct v4l2_ctrl_h264_decode_params *decode_params; ++ const struct v4l2_ctrl_h264_pps *pps; ++ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; ++ const struct v4l2_ctrl_h264_slice_params *slice_params; ++ const struct v4l2_ctrl_h264_sps *sps; ++}; ++ + struct cedrus_mpeg2_run { + const struct v4l2_ctrl_mpeg2_slice_params *slice_params; + const struct v4l2_ctrl_mpeg2_quantization *quantization; +@@ -59,12 +73,20 @@ struct cedrus_run { + struct vb2_v4l2_buffer *dst; + + union { ++ struct cedrus_h264_run h264; + struct cedrus_mpeg2_run mpeg2; + }; + }; + + struct cedrus_buffer { + struct v4l2_m2m_buffer m2m_buf; ++ ++ union { ++ struct { ++ unsigned int position; ++ enum cedrus_h264_pic_type pic_type; ++ } h264; ++ } codec; + }; + + struct cedrus_ctx { +@@ -79,6 +101,19 @@ struct cedrus_ctx { + struct v4l2_ctrl **ctrls; + + struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME]; ++ ++ union { ++ struct { ++ void *mv_col_buf; ++ dma_addr_t mv_col_buf_dma; ++ ssize_t mv_col_buf_field_size; ++ ssize_t mv_col_buf_size; ++ void *pic_info_buf; ++ dma_addr_t pic_info_buf_dma; ++ void *neighbor_info_buf; ++ dma_addr_t neighbor_info_buf_dma; ++ } h264; ++ } codec; + }; + + struct cedrus_dec_ops { +@@ -122,6 +157,7 @@ struct cedrus_dev { + }; + + extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; ++extern struct cedrus_dec_ops cedrus_dec_ops_h264; + + static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) + { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +index 4d6d602cdde6..bdad87eb9d79 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +@@ -46,6 +46,19 @@ void cedrus_device_run(void *priv) + V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); + break; + ++ case V4L2_PIX_FMT_H264_SLICE_RAW: ++ run.h264.decode_params = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); ++ run.h264.pps = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_PPS); ++ run.h264.scaling_matrix = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX); ++ run.h264.slice_params = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); ++ run.h264.sps = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SPS); ++ break; ++ + default: + break; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +new file mode 100644 +index 000000000000..a30bb283f69f +--- /dev/null ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -0,0 +1,576 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Cedrus VPU driver ++ * ++ * Copyright (c) 2013 Jens Kuske ++ * Copyright (c) 2018 Bootlin ++ */ ++ ++#include ++ ++#include ++ ++#include "cedrus.h" ++#include "cedrus_hw.h" ++#include "cedrus_regs.h" ++ ++enum cedrus_h264_sram_off { ++ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE = 0x000, ++ CEDRUS_SRAM_H264_FRAMEBUFFER_LIST = 0x100, ++ CEDRUS_SRAM_H264_REF_LIST_0 = 0x190, ++ CEDRUS_SRAM_H264_REF_LIST_1 = 0x199, ++ CEDRUS_SRAM_H264_SCALING_LIST_8x8_0 = 0x200, ++ CEDRUS_SRAM_H264_SCALING_LIST_8x8_1 = 0x210, ++ CEDRUS_SRAM_H264_SCALING_LIST_4x4 = 0x220, ++}; ++ ++struct cedrus_h264_sram_ref_pic { ++ __le32 top_field_order_cnt; ++ __le32 bottom_field_order_cnt; ++ __le32 frame_info; ++ __le32 luma_ptr; ++ __le32 chroma_ptr; ++ __le32 mv_col_top_ptr; ++ __le32 mv_col_bot_ptr; ++ __le32 reserved; ++} __packed; ++ ++#define CEDRUS_H264_FRAME_NUM 18 ++ ++#define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) ++#define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) ++ ++static void cedrus_h264_write_sram(struct cedrus_dev *dev, ++ enum cedrus_h264_sram_off off, ++ const void *data, size_t len) ++{ ++ const u32 *buffer = data; ++ size_t count = DIV_ROUND_UP(len, 4); ++ ++ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, off << 2); ++ ++ while (count--) ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, *buffer++); ++} ++ ++static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, ++ unsigned int position, ++ unsigned int field) ++{ ++ dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; ++ ++ /* Adjust for the position */ ++ addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; ++ ++ /* Adjust for the field */ ++ addr += field * ctx->codec.h264.mv_col_buf_field_size; ++ ++ return addr; ++} ++ ++static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, ++ struct cedrus_buffer *buf, ++ unsigned int top_field_order_cnt, ++ unsigned int bottom_field_order_cnt, ++ struct cedrus_h264_sram_ref_pic *pic) ++{ ++ struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; ++ unsigned int position = buf->codec.h264.position; ++ ++ pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt); ++ pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt); ++ pic->frame_info = cpu_to_le32(buf->codec.h264.pic_type << 8); ++ ++ pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0)); ++ pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1)); ++ pic->mv_col_top_ptr = ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0)); ++ pic->mv_col_bot_ptr = ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1)); ++} ++ ++static void cedrus_write_frame_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ struct cedrus_h264_sram_ref_pic pic_list[CEDRUS_H264_FRAME_NUM]; ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; ++ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; ++ struct cedrus_buffer *output_buf; ++ struct cedrus_dev *dev = ctx->dev; ++ unsigned long used_dpbs = 0; ++ unsigned int position; ++ unsigned int output = 0; ++ unsigned int i; ++ ++ memset(pic_list, 0, sizeof(pic_list)); ++ ++ for (i = 0; i < ARRAY_SIZE(decode->dpb); i++) { ++ const struct v4l2_h264_dpb_entry *dpb = &decode->dpb[i]; ++ struct cedrus_buffer *cedrus_buf; ++ int buf_idx; ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) ++ continue; ++ ++ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); ++ if (buf_idx < 0) ++ continue; ++ ++ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[buf_idx]); ++ position = cedrus_buf->codec.h264.position; ++ used_dpbs |= BIT(position); ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ continue; ++ ++ cedrus_fill_ref_pic(ctx, cedrus_buf, ++ dpb->top_field_order_cnt, ++ dpb->bottom_field_order_cnt, ++ &pic_list[position]); ++ ++ output = max(position, output); ++ } ++ ++ position = find_next_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM, ++ output); ++ if (position >= CEDRUS_H264_FRAME_NUM) ++ position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); ++ ++ output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); ++ output_buf->codec.h264.position = position; ++ ++ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; ++ else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_MBAFF; ++ else ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FRAME; ++ ++ cedrus_fill_ref_pic(ctx, output_buf, ++ decode->top_field_order_cnt, ++ decode->bottom_field_order_cnt, ++ &pic_list[position]); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_FRAMEBUFFER_LIST, ++ pic_list, sizeof(pic_list)); ++ ++ cedrus_write(dev, VE_H264_OUTPUT_FRAME_IDX, position); ++} ++ ++#define CEDRUS_MAX_REF_IDX 32 ++ ++static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run, ++ const u8 *ref_list, u8 num_ref, ++ enum cedrus_h264_sram_off sram) ++{ ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; ++ struct cedrus_dev *dev = ctx->dev; ++ u8 sram_array[CEDRUS_MAX_REF_IDX]; ++ unsigned int i; ++ size_t size; ++ ++ memset(sram_array, 0, sizeof(sram_array)); ++ ++ for (i = 0; i < num_ref; i++) { ++ const struct v4l2_h264_dpb_entry *dpb; ++ const struct cedrus_buffer *cedrus_buf; ++ const struct vb2_v4l2_buffer *ref_buf; ++ unsigned int position; ++ int buf_idx; ++ u8 dpb_idx; ++ ++ dpb_idx = ref_list[i]; ++ dpb = &decode->dpb[dpb_idx]; ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ continue; ++ ++ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); ++ if (buf_idx < 0) ++ continue; ++ ++ ref_buf = to_vb2_v4l2_buffer(ctx->dst_bufs[buf_idx]); ++ cedrus_buf = vb2_v4l2_to_cedrus_buffer(ref_buf); ++ position = cedrus_buf->codec.h264.position; ++ ++ sram_array[i] |= position << 1; ++ if (ref_buf->field == V4L2_FIELD_BOTTOM) ++ sram_array[i] |= BIT(0); ++ } ++ ++ size = min_t(size_t, ALIGN(num_ref, 4), sizeof(sram_array)); ++ cedrus_h264_write_sram(dev, sram, &sram_array, size); ++} ++ ++static void cedrus_write_ref_list0(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ ++ _cedrus_write_ref_list(ctx, run, ++ slice->ref_pic_list0, ++ slice->num_ref_idx_l0_active_minus1 + 1, ++ CEDRUS_SRAM_H264_REF_LIST_0); ++} ++ ++static void cedrus_write_ref_list1(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ ++ _cedrus_write_ref_list(ctx, run, ++ slice->ref_pic_list1, ++ slice->num_ref_idx_l1_active_minus1 + 1, ++ CEDRUS_SRAM_H264_REF_LIST_1); ++} ++ ++static void cedrus_write_scaling_lists(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_scaling_matrix *scaling = ++ run->h264.scaling_matrix; ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_0, ++ scaling->scaling_list_8x8[0], ++ sizeof(scaling->scaling_list_8x8[0])); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_1, ++ scaling->scaling_list_8x8[3], ++ sizeof(scaling->scaling_list_8x8[3])); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_4x4, ++ scaling->scaling_list_4x4, ++ sizeof(scaling->scaling_list_4x4)); ++} ++ ++static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = ++ run->h264.slice_params; ++ const struct v4l2_h264_pred_weight_table *pred_weight = ++ &slice->pred_weight_table; ++ struct cedrus_dev *dev = ctx->dev; ++ int i, j, k; ++ ++ cedrus_write(dev, VE_H264_SHS_WP, ++ ((pred_weight->chroma_log2_weight_denom & 0x7) << 4) | ++ ((pred_weight->luma_log2_weight_denom & 0x7) << 0)); ++ ++ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, ++ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE << 2); ++ ++ for (i = 0; i < ARRAY_SIZE(pred_weight->weight_factors); i++) { ++ const struct v4l2_h264_weight_factors *factors = ++ &pred_weight->weight_factors[i]; ++ ++ for (j = 0; j < ARRAY_SIZE(factors->luma_weight); j++) { ++ u32 val; ++ ++ val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | ++ (factors->luma_weight[j] & 0x1ff); ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); ++ } ++ ++ for (j = 0; j < ARRAY_SIZE(factors->chroma_weight); j++) { ++ for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { ++ u32 val; ++ ++ val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | ++ (factors->chroma_weight[j][k] & 0x1ff); ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); ++ } ++ } ++ } ++} ++ ++static void cedrus_set_params(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; ++ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; ++ struct vb2_buffer *src_buf = &run->src->vb2_buf; ++ struct cedrus_dev *dev = ctx->dev; ++ dma_addr_t src_buf_addr; ++ u32 offset = slice->header_bit_size; ++ u32 len = (slice->size * 8) - offset; ++ u32 reg; ++ ++ cedrus_write(dev, VE_H264_VLD_LEN, len); ++ cedrus_write(dev, VE_H264_VLD_OFFSET, offset); ++ ++ src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); ++ cedrus_write(dev, VE_H264_VLD_END, ++ src_buf_addr + vb2_get_plane_payload(src_buf, 0)); ++ cedrus_write(dev, VE_H264_VLD_ADDR, ++ VE_H264_VLD_ADDR_VAL(src_buf_addr) | ++ VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | ++ VE_H264_VLD_ADDR_LAST); ++ ++ /* ++ * FIXME: Since the bitstream parsing is done in software, and ++ * in userspace, this shouldn't be needed anymore. But it ++ * turns out that removing it breaks the decoding process, ++ * without any clear indication why. ++ */ ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, ++ VE_H264_TRIGGER_TYPE_INIT_SWDEC); ++ ++ if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_P || ++ slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || ++ (pps->weighted_bipred_idc == 1 && ++ slice->slice_type == V4L2_H264_SLICE_TYPE_B)) ++ cedrus_write_pred_weight_table(ctx, run); ++ ++ if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_SP) || ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_B)) ++ cedrus_write_ref_list0(ctx, run); ++ ++ if (slice->slice_type == V4L2_H264_SLICE_TYPE_B) ++ cedrus_write_ref_list1(ctx, run); ++ ++ // picture parameters ++ reg = 0; ++ /* ++ * FIXME: the kernel headers are allowing the default value to ++ * be passed, but the libva doesn't give us that. ++ */ ++ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; ++ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; ++ reg |= (pps->weighted_bipred_idc & 0x3) << 2; ++ if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) ++ reg |= VE_H264_PPS_ENTROPY_CODING_MODE; ++ if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) ++ reg |= VE_H264_PPS_WEIGHTED_PRED; ++ if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) ++ reg |= VE_H264_PPS_CONSTRAINED_INTRA_PRED; ++ if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) ++ reg |= VE_H264_PPS_TRANSFORM_8X8_MODE; ++ cedrus_write(dev, VE_H264_PPS, reg); ++ ++ // sequence parameters ++ reg = 0; ++ reg |= (sps->chroma_format_idc & 0x7) << 19; ++ reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; ++ reg |= sps->pic_height_in_map_units_minus1 & 0xff; ++ if (sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) ++ reg |= VE_H264_SPS_MBS_ONLY; ++ if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) ++ reg |= VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD; ++ if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) ++ reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; ++ cedrus_write(dev, VE_H264_SPS, reg); ++ ++ // slice parameters ++ reg = 0; ++ reg |= decode->nal_ref_idc ? BIT(12) : 0; ++ reg |= (slice->slice_type & 0xf) << 8; ++ reg |= slice->cabac_init_idc & 0x3; ++ reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) ++ reg |= VE_H264_SHS_FIELD_PIC; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ++ reg |= VE_H264_SHS_BOTTOM_FIELD; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED) ++ reg |= VE_H264_SHS_DIRECT_SPATIAL_MV_PRED; ++ cedrus_write(dev, VE_H264_SHS, reg); ++ ++ reg = 0; ++ reg |= VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD; ++ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 24; ++ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 16; ++ reg |= (slice->disable_deblocking_filter_idc & 0x3) << 8; ++ reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; ++ reg |= slice->slice_beta_offset_div2 & 0xf; ++ cedrus_write(dev, VE_H264_SHS2, reg); ++ ++ reg = 0; ++ reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; ++ reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; ++ reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; ++ cedrus_write(dev, VE_H264_SHS_QP, reg); ++ ++ // clear status flags ++ cedrus_write(dev, VE_H264_STATUS, cedrus_read(dev, VE_H264_STATUS)); ++ ++ // enable int ++ cedrus_write(dev, VE_H264_CTRL, ++ VE_H264_CTRL_SLICE_DECODE_INT | ++ VE_H264_CTRL_DECODE_ERR_INT | ++ VE_H264_CTRL_VLD_DATA_REQ_INT); ++} ++ ++static enum cedrus_irq_status ++cedrus_h264_irq_status(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ u32 reg = cedrus_read(dev, VE_H264_STATUS); ++ ++ if (reg & (VE_H264_STATUS_DECODE_ERR_INT | ++ VE_H264_STATUS_VLD_DATA_REQ_INT)) ++ return CEDRUS_IRQ_ERROR; ++ ++ if (reg & VE_H264_CTRL_SLICE_DECODE_INT) ++ return CEDRUS_IRQ_OK; ++ ++ return CEDRUS_IRQ_NONE; ++} ++ ++static void cedrus_h264_irq_clear(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_write(dev, VE_H264_STATUS, ++ VE_H264_STATUS_INT_MASK); ++} ++ ++static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ u32 reg = cedrus_read(dev, VE_H264_CTRL); ++ ++ cedrus_write(dev, VE_H264_CTRL, ++ reg & ~VE_H264_CTRL_INT_MASK); ++} ++ ++static void cedrus_h264_setup(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_engine_enable(dev, CEDRUS_CODEC_H264); ++ ++ cedrus_write(dev, VE_H264_SDROT_CTRL, 0); ++ cedrus_write(dev, VE_H264_EXTRA_BUFFER1, ++ ctx->codec.h264.pic_info_buf_dma); ++ cedrus_write(dev, VE_H264_EXTRA_BUFFER2, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ ++ cedrus_write_scaling_lists(ctx, run); ++ cedrus_write_frame_list(ctx, run); ++ ++ cedrus_set_params(ctx, run); ++} ++ ++static int cedrus_h264_start(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ unsigned int field_size; ++ unsigned int mv_col_size; ++ int ret; ++ ++ /* ++ * FIXME: It seems that the H6 cedarX code is using a formula ++ * here based on the size of the frame, while all the older ++ * code is using a fixed size, so that might need to be ++ * changed at some point. ++ */ ++ ctx->codec.h264.pic_info_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ &ctx->codec.h264.pic_info_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.pic_info_buf) ++ return -ENOMEM; ++ ++ /* ++ * That buffer is supposed to be 16kiB in size, and be aligned ++ * on 16kiB as well. However, dma_alloc_coherent provides the ++ * guarantee that we'll have a CPU and DMA address aligned on ++ * the smallest page order that is greater to the requested ++ * size, so we don't have to overallocate. ++ */ ++ ctx->codec.h264.neighbor_info_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ &ctx->codec.h264.neighbor_info_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.neighbor_info_buf) { ++ ret = -ENOMEM; ++ goto err_pic_buf; ++ } ++ ++ field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * ++ DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; ++ ++ /* ++ * FIXME: This is actually conditional to ++ * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we ++ * might have to rework this if memory efficiency ever is ++ * something we need to work on. ++ */ ++ field_size = field_size * 2; ++ ++ /* ++ * FIXME: This is actually conditional to ++ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might ++ * have to rework this if memory efficiency ever is something ++ * we need to work on. ++ */ ++ field_size = field_size * 2; ++ ctx->codec.h264.mv_col_buf_field_size = field_size; ++ ++ mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; ++ ctx->codec.h264.mv_col_buf_size = mv_col_size; ++ ctx->codec.h264.mv_col_buf = dma_alloc_coherent(dev->dev, ++ ctx->codec.h264.mv_col_buf_size, ++ &ctx->codec.h264.mv_col_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.mv_col_buf) { ++ ret = -ENOMEM; ++ goto err_neighbor_buf; ++ } ++ ++ return 0; ++ ++err_neighbor_buf: ++ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h264.neighbor_info_buf, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ ++err_pic_buf: ++ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ ctx->codec.h264.pic_info_buf, ++ ctx->codec.h264.pic_info_buf_dma); ++ return ret; ++} ++ ++static void cedrus_h264_stop(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, ++ ctx->codec.h264.mv_col_buf, ++ ctx->codec.h264.mv_col_buf_dma); ++ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h264.neighbor_info_buf, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ ctx->codec.h264.pic_info_buf, ++ ctx->codec.h264.pic_info_buf_dma); ++} ++ ++static void cedrus_h264_trigger(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, ++ VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE); ++} ++ ++struct cedrus_dec_ops cedrus_dec_ops_h264 = { ++ .irq_clear = cedrus_h264_irq_clear, ++ .irq_disable = cedrus_h264_irq_disable, ++ .irq_status = cedrus_h264_irq_status, ++ .setup = cedrus_h264_setup, ++ .start = cedrus_h264_start, ++ .stop = cedrus_h264_stop, ++ .trigger = cedrus_h264_trigger, ++}; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index 60406b2d4595..c34aec7c6e40 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -46,6 +46,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) + reg |= VE_MODE_DEC_MPEG; + break; + ++ case CEDRUS_CODEC_H264: ++ reg |= VE_MODE_DEC_H264; ++ break; ++ + default: + return -EINVAL; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index de2d6b6f64bf..3e9931416e45 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -232,4 +232,95 @@ + #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) + #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) + ++#define VE_H264_SPS 0x200 ++#define VE_H264_SPS_MBS_ONLY BIT(18) ++#define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) ++#define VE_H264_SPS_DIRECT_8X8_INFERENCE BIT(16) ++ ++#define VE_H264_PPS 0x204 ++#define VE_H264_PPS_ENTROPY_CODING_MODE BIT(15) ++#define VE_H264_PPS_WEIGHTED_PRED BIT(4) ++#define VE_H264_PPS_CONSTRAINED_INTRA_PRED BIT(1) ++#define VE_H264_PPS_TRANSFORM_8X8_MODE BIT(0) ++ ++#define VE_H264_SHS 0x208 ++#define VE_H264_SHS_FIRST_SLICE_IN_PIC BIT(5) ++#define VE_H264_SHS_FIELD_PIC BIT(4) ++#define VE_H264_SHS_BOTTOM_FIELD BIT(3) ++#define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED BIT(2) ++ ++#define VE_H264_SHS2 0x20c ++#define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD BIT(12) ++ ++#define VE_H264_SHS_WP 0x210 ++ ++#define VE_H264_SHS_QP 0x21c ++#define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) ++ ++#define VE_H264_CTRL 0x220 ++#define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) ++#define VE_H264_CTRL_DECODE_ERR_INT BIT(1) ++#define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) ++ ++#define VE_H264_CTRL_INT_MASK (VE_H264_CTRL_VLD_DATA_REQ_INT | \ ++ VE_H264_CTRL_DECODE_ERR_INT | \ ++ VE_H264_CTRL_SLICE_DECODE_INT) ++ ++#define VE_H264_TRIGGER_TYPE 0x224 ++#define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) ++#define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) ++ ++#define VE_H264_STATUS 0x228 ++#define VE_H264_STATUS_VLD_DATA_REQ_INT VE_H264_CTRL_VLD_DATA_REQ_INT ++#define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT ++#define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT ++ ++#define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK ++ ++#define VE_H264_CUR_MB_NUM 0x22c ++ ++#define VE_H264_VLD_ADDR 0x230 ++#define VE_H264_VLD_ADDR_FIRST BIT(30) ++#define VE_H264_VLD_ADDR_LAST BIT(29) ++#define VE_H264_VLD_ADDR_VALID BIT(28) ++#define VE_H264_VLD_ADDR_VAL(x) (((x) & 0x0ffffff0) | ((x) >> 28)) ++ ++#define VE_H264_VLD_OFFSET 0x234 ++#define VE_H264_VLD_LEN 0x238 ++#define VE_H264_VLD_END 0x23c ++#define VE_H264_SDROT_CTRL 0x240 ++#define VE_H264_OUTPUT_FRAME_IDX 0x24c ++#define VE_H264_EXTRA_BUFFER1 0x250 ++#define VE_H264_EXTRA_BUFFER2 0x254 ++#define VE_H264_BASIC_BITS 0x2dc ++#define VE_AVC_SRAM_PORT_OFFSET 0x2e0 ++#define VE_AVC_SRAM_PORT_DATA 0x2e4 ++ ++#define VE_ISP_INPUT_SIZE 0xa00 ++#define VE_ISP_INPUT_STRIDE 0xa04 ++#define VE_ISP_CTRL 0xa08 ++#define VE_ISP_INPUT_LUMA 0xa78 ++#define VE_ISP_INPUT_CHROMA 0xa7c ++ ++#define VE_AVC_PARAM 0xb04 ++#define VE_AVC_QP 0xb08 ++#define VE_AVC_MOTION_EST 0xb10 ++#define VE_AVC_CTRL 0xb14 ++#define VE_AVC_TRIGGER 0xb18 ++#define VE_AVC_STATUS 0xb1c ++#define VE_AVC_BASIC_BITS 0xb20 ++#define VE_AVC_UNK_BUF 0xb60 ++#define VE_AVC_VLE_ADDR 0xb80 ++#define VE_AVC_VLE_END 0xb84 ++#define VE_AVC_VLE_OFFSET 0xb88 ++#define VE_AVC_VLE_MAX 0xb8c ++#define VE_AVC_VLE_LENGTH 0xb90 ++#define VE_AVC_REF_LUMA 0xba0 ++#define VE_AVC_REF_CHROMA 0xba4 ++#define VE_AVC_REC_LUMA 0xbb0 ++#define VE_AVC_REC_CHROMA 0xbb4 ++#define VE_AVC_REF_SLUMA 0xbb8 ++#define VE_AVC_REC_SLUMA 0xbbc ++#define VE_AVC_MB_INFO 0xbc0 ++ + #endif +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index 9673874ece10..e2b530b1a956 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -37,6 +37,10 @@ static struct cedrus_format cedrus_formats[] = { + .pixelformat = V4L2_PIX_FMT_MPEG2_SLICE, + .directions = CEDRUS_DECODE_SRC, + }, ++ { ++ .pixelformat = V4L2_PIX_FMT_H264_SLICE_RAW, ++ .directions = CEDRUS_DECODE_SRC, ++ }, + { + .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, + .directions = CEDRUS_DECODE_DST, +@@ -100,6 +104,7 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) + + switch (pix_fmt->pixelformat) { + case V4L2_PIX_FMT_MPEG2_SLICE: ++ case V4L2_PIX_FMT_H264_SLICE_RAW: + /* Zero bytes per line for encoded source. */ + bytesperline = 0; + +@@ -464,6 +469,10 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) + ctx->current_codec = CEDRUS_CODEC_MPEG2; + break; + ++ case V4L2_PIX_FMT_H264_SLICE_RAW: ++ ctx->current_codec = CEDRUS_CODEC_H264; ++ break; ++ + default: + return -EINVAL; + } +-- +2.21.0 + +From ca0961011db57e39880df0b5708df8aa3339dc6f Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 18 May 2019 17:40:14 +0200 +Subject: [PATCH] ARM: dts: sun8i-h3: Fix wifi in Beelink X2 DT + +mmc1 node where wifi module is connected doesn't have properly defined +power supplies so wifi module is never powered up. Fix that by +specifying additional power supplies. + +Additionally, this STB may have either Realtek or Broadcom based wifi +module. One based on Broadcom module also needs external clock to work +properly. Fix that by adding clock property to wifi_pwrseq node. + +Fixes: e582b47a9252 ("ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB") +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +index 6277f13f3eb3..ac9e26b1d906 100644 +--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts ++++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +@@ -90,6 +90,8 @@ + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; + }; + + sound_spdif { +@@ -155,6 +157,8 @@ + + &mmc1 { + vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +-- +2.21.0 + +From 85c6fadd185e495a3ef9cd8a60bb70b82b72d941 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 14 May 2019 22:54:45 +0200 +Subject: [PATCH] arm64: dts: allwinner: a64: orangepi-win: Add wifi and + bluetooth nodes + +The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side +identifies as BCM43430, while the Bluetooth side identifies as BCM43438. + +WiFi is connected to mmc1 and the Bluetooth side is connected to UART1 +in a 4 wire configuration. Same as the WiFi side, due to being the same +chip and package, DLDO2 provides overall power via VBAT, and DLDO4 +provides I/O power via VDDIO. The RTC clock output provides the LPO low +power clock at 32.768 kHz. + +This patch enables WiFi and Bluetooth on OrangePi Win boards and adds +missing LPO clock on the WiFi side. PCM connection also exists for +Bluetooth audio, but it's not used here. + +Bluetooth UART speed is set to 1.5 MBaud in order to be able transmit +audio. While module supports even higher speeds, currently sunxi clock +driver doesn't support higher speed. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + .../dts/allwinner/sun50i-a64-orangepi-win.dts | 23 +++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +index 510f661229dc..5ef3c62c765e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +@@ -109,6 +109,8 @@ + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; + }; + }; + +@@ -170,6 +172,14 @@ + bus-width = <4>; + non-removable; + status = "okay"; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ ++ interrupt-names = "host-wake"; ++ }; + }; + + &ohci0 { +@@ -342,7 +352,20 @@ + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; + status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <1500000>; ++ clocks = <&rtc 1>; ++ clock-names = "lpo"; ++ vbat-supply = <®_dldo2>; ++ vddio-supply = <®_dldo4>; ++ device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ ++ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ ++ }; + }; + + /* On Pi-2 connector, RTS/CTS optional */ +-- +2.21.0 + +From ae3ceed0a399fa0cc83410ce7bbf3a1675b733a9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Thu, 23 May 2019 17:10:49 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: add r_watchog node +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Allwinner H6 has a r_watchdog similar to A64. + +Declare it in the device-tree. + +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 13e70aebddbe..b9a7dc8d2a40 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -631,6 +631,13 @@ + #reset-cells = <1>; + }; + ++ r_watchdog: watchdog@7020400 { ++ compatible = "allwinner,sun50i-h6-wdt", ++ "allwinner,sun6i-a31-wdt"; ++ reg = <0x07020400 0x20>; ++ interrupts = ; ++ }; ++ + r_intc: interrupt-controller@7021000 { + compatible = "allwinner,sun50i-h6-r-intc", + "allwinner,sun6i-a31-r-intc"; +-- +2.21.0 + +From f7275345728a0ff18a0607dd3706f2ca25dc53e0 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sat, 13 Apr 2019 18:54:12 +0200 +Subject: [PATCH] pinctrl: sunxi: Prepare for alternative bias voltage setting + methods + +H6 has a different I/O voltage bias setting method than A80. Prepare +existing code for using alternative bias voltage setting methods. + +Signed-off-by: Ondrej Jirman +Acked-by: Maxime Ripard +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 2 +- + drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 +- + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 47 ++++++++++++--------- + drivers/pinctrl/sunxi/pinctrl-sunxi.h | 11 ++++- + 4 files changed, 39 insertions(+), 23 deletions(-) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +index e05dd9a5551d..a191a65217ac 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +@@ -153,7 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = { + .pin_base = PL_BASE, + .irq_banks = 2, + .disable_strict_mode = true, +- .has_io_bias_cfg = true, ++ .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, + }; + + static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +index da37d594a13d..0633a03d5e13 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +@@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { + .npins = ARRAY_SIZE(sun9i_a80_pins), + .irq_banks = 5, + .disable_strict_mode = true, +- .has_io_bias_cfg = true, ++ .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, + }; + + static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +index be04223591d4..98c4de5f4019 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -617,7 +617,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, + u32 val, reg; + int uV; + +- if (!pctl->desc->has_io_bias_cfg) ++ if (!pctl->desc->io_bias_cfg_variant) + return 0; + + uV = regulator_get_voltage(supply); +@@ -628,25 +628,32 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, + if (uV == 0) + return 0; + +- /* Configured value must be equal or greater to actual voltage */ +- if (uV <= 1800000) +- val = 0x0; /* 1.8V */ +- else if (uV <= 2500000) +- val = 0x6; /* 2.5V */ +- else if (uV <= 2800000) +- val = 0x9; /* 2.8V */ +- else if (uV <= 3000000) +- val = 0xA; /* 3.0V */ +- else +- val = 0xD; /* 3.3V */ +- +- pin -= pctl->desc->pin_base; +- +- reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); +- reg &= ~IO_BIAS_MASK; +- writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); +- +- return 0; ++ switch (pctl->desc->io_bias_cfg_variant) { ++ case BIAS_VOLTAGE_GRP_CONFIG: ++ /* ++ * Configured value must be equal or greater to actual ++ * voltage. ++ */ ++ if (uV <= 1800000) ++ val = 0x0; /* 1.8V */ ++ else if (uV <= 2500000) ++ val = 0x6; /* 2.5V */ ++ else if (uV <= 2800000) ++ val = 0x9; /* 2.8V */ ++ else if (uV <= 3000000) ++ val = 0xA; /* 3.0V */ ++ else ++ val = 0xD; /* 3.3V */ ++ ++ pin -= pctl->desc->pin_base; ++ ++ reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); ++ reg &= ~IO_BIAS_MASK; ++ writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); ++ return 0; ++ default: ++ return -EINVAL; ++ } + } + + static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h +index ee15ab067b5f..a62b81357136 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h +@@ -95,6 +95,15 @@ + #define PINCTRL_SUN7I_A20 BIT(7) + #define PINCTRL_SUN8I_R40 BIT(8) + ++enum sunxi_desc_bias_voltage { ++ BIAS_VOLTAGE_NONE, ++ /* ++ * Bias voltage configuration is done through ++ * Pn_GRP_CONFIG registers, as seen on A80 SoC. ++ */ ++ BIAS_VOLTAGE_GRP_CONFIG, ++}; ++ + struct sunxi_desc_function { + unsigned long variant; + const char *name; +@@ -117,7 +126,7 @@ struct sunxi_pinctrl_desc { + const unsigned int *irq_bank_map; + bool irq_read_needs_mux; + bool disable_strict_mode; +- bool has_io_bias_cfg; ++ enum sunxi_desc_bias_voltage io_bias_cfg_variant; + }; + + struct sunxi_pinctrl_function { +-- +2.21.0 + +From cc62383fcebe7f03c274462790fd912f4346304b Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sat, 13 Apr 2019 18:54:13 +0200 +Subject: [PATCH] pinctrl: sunxi: Support I/O bias voltage setting on H6 + +H6 SoC has a "pio group withstand voltage mode" register (datasheet +description), that needs to be used to select either 1.8V or 3.3V I/O mode, +based on what voltage is powering the respective pin banks and is thus used +for I/O signals. + +Add support for configuring this register according to the voltage of the +pin bank regulator (if enabled). + +This is similar to the support for I/O bias voltage setting patch for A80 +and the same concerns apply. See: + + commit 402bfb3c1352 ("Support I/O bias voltage setting on A80") + +Signed-off-by: Ondrej Jirman +Acked-by: Maxime Ripard +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 + + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 11 +++++++++++ + drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 +++++++ + 3 files changed, 19 insertions(+) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +index ef4268cc6227..3cc1121589c9 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +@@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = { + .irq_banks = 4, + .irq_bank_map = h6_irq_bank_map, + .irq_read_needs_mux = true, ++ .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + }; + + static int h6_pinctrl_probe(struct platform_device *pdev) +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +index 98c4de5f4019..0cbca30b75dc 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -614,6 +614,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, + unsigned pin, + struct regulator *supply) + { ++ unsigned short bank = pin / PINS_PER_BANK; ++ unsigned long flags; + u32 val, reg; + int uV; + +@@ -651,6 +653,15 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, + reg &= ~IO_BIAS_MASK; + writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + return 0; ++ case BIAS_VOLTAGE_PIO_POW_MODE_SEL: ++ val = uV <= 1800000 ? 1 : 0; ++ ++ raw_spin_lock_irqsave(&pctl->lock, flags); ++ reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); ++ reg &= ~(1 << bank); ++ writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); ++ raw_spin_unlock_irqrestore(&pctl->lock, flags); ++ return 0; + default: + return -EINVAL; + } +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h +index a62b81357136..44e30deeee38 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h +@@ -95,6 +95,8 @@ + #define PINCTRL_SUN7I_A20 BIT(7) + #define PINCTRL_SUN8I_R40 BIT(8) + ++#define PIO_POW_MOD_SEL_REG 0x340 ++ + enum sunxi_desc_bias_voltage { + BIAS_VOLTAGE_NONE, + /* +@@ -102,6 +104,11 @@ enum sunxi_desc_bias_voltage { + * Pn_GRP_CONFIG registers, as seen on A80 SoC. + */ + BIAS_VOLTAGE_GRP_CONFIG, ++ /* ++ * Bias voltage is set through PIO_POW_MOD_SEL_REG ++ * register, as seen on H6 SoC, for example. ++ */ ++ BIAS_VOLTAGE_PIO_POW_MODE_SEL, + }; + + struct sunxi_desc_function { +-- +2.21.0 + +From 22538576beb671038bd21be4094432fa8070ad81 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Fri, 3 May 2019 17:47:20 +0800 +Subject: [PATCH] arm64: dts: allwinner: h6: add PIO VCC bank supplies for Pine + H64 + +The Allwinner H6 SoC features tweakable VCC for PC, PD, PG, PL and PM +banks. + +This patch adds supplies for these banks except PL bank. PL bank is +where PMIC is attached, and currently if a PMIC regulator is added +for it a dependency loop will happen. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +index 4802902e128f..9e464d40cbff 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +@@ -127,6 +127,12 @@ + status = "okay"; + }; + ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_aldo1>; ++}; ++ + &r_i2c { + status = "okay"; + +@@ -247,6 +253,10 @@ + }; + }; + ++&r_pio { ++ vcc-pm-supply = <®_aldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch b/projects/Allwinner/patches/linux/0004-cedrus-hevc.patch similarity index 74% rename from projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch rename to projects/Allwinner/patches/linux/0004-cedrus-hevc.patch index dd5aac6690..a5184d98a5 100644 --- a/projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch +++ b/projects/Allwinner/patches/linux/0004-cedrus-hevc.patch @@ -1,80 +1,16 @@ -From patchwork Thu Feb 14 09:53:08 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Paul Kocialkowski -X-Patchwork-Id: 10812217 -Return-Path: -Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org - [172.30.200.125]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E14113B4 - for ; - Thu, 14 Feb 2019 09:55:00 +0000 (UTC) -Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED4C528703 - for ; - Thu, 14 Feb 2019 09:54:59 +0000 (UTC) -Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) - id E062E28758; Thu, 14 Feb 2019 09:54:59 +0000 (UTC) -X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on - pdx-wl-mail.web.codeaurora.org -X-Spam-Level: -X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, - RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 -Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 388EF28703 - for ; - Thu, 14 Feb 2019 09:54:57 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S2392986AbfBNJyo (ORCPT - ); - Thu, 14 Feb 2019 04:54:44 -0500 -Received: from relay8-d.mail.gandi.net ([217.70.183.201]:58429 "EHLO - relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S2392838AbfBNJyn (ORCPT - ); - Thu, 14 Feb 2019 04:54:43 -0500 -X-Originating-IP: 90.88.30.68 -Received: from localhost.localdomain - (aaubervilliers-681-1-89-68.w90-88.abo.wanadoo.fr [90.88.30.68]) - (Authenticated sender: paul.kocialkowski@bootlin.com) - by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 7E9C61BF20B; - Thu, 14 Feb 2019 09:54:37 +0000 (UTC) +From 2a7c76208e46bd164d7e968d063d870fcb1e9314 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski -To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, - devel@driverdev.osuosl.org, linux-arm-kernel@lists.infradead.org, - linux-sunxi@googlegroups.com -Cc: Mauro Carvalho Chehab , - Maxime Ripard , - Paul Kocialkowski , - Greg Kroah-Hartman , - Chen-Yu Tsai , - Thomas Petazzoni , - Hans Verkuil , - Sakari Ailus , - Randy Li , - Ezequiel Garcia , - Tomasz Figa , - Alexandre Courbot -Subject: [PATCH v3 1/2] media: v4l: Add definitions for the HEVC slice format - and controls -Date: Thu, 14 Feb 2019 10:53:08 +0100 -Message-Id: <20190214095309.19594-2-paul.kocialkowski@bootlin.com> -X-Mailer: git-send-email 2.20.1 -In-Reply-To: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> -References: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> -MIME-Version: 1.0 -Sender: linux-media-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-media@vger.kernel.org -X-Virus-Scanned: ClamAV using ClamSMTP +Date: Fri, 24 May 2019 11:36:32 +0200 +Subject: [PATCH 09/12] media: v4l: Add definitions for the HEVC slice controls This introduces the required definitions for HEVC decoding support with stateless VPUs. The controls associated to the HEVC slice format provide the required meta-data for decoding slices extracted from the bitstream. -This interface comes with the following limitations: +They are not exported to the public V4L2 API since reworking this API +will be needed for covering various use-cases and new hardware. + +The interface comes with the following limitations: * No custom quantization matrices (scaling lists); * Support for a single temporal layer only; * No slice entry point offsets support; @@ -83,25 +19,24 @@ This interface comes with the following limitations: * No support for SPS extensions: range, multilayer, 3d, scc, 4 bits; * No support for PPS extensions: range, multilayer, 3d, scc, 4 bits. -Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil --- Documentation/media/uapi/v4l/biblio.rst | 9 + - .../media/uapi/v4l/pixfmt-compressed.rst | 15 + + .../media/uapi/v4l/ext-ctrls-codec.rst | 429 +++++++++++++++++- .../media/uapi/v4l/vidioc-queryctrl.rst | 18 + .../media/videodev2.h.rst.exceptions | 3 + drivers/media/v4l2-core/v4l2-ctrls.c | 26 ++ drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/hevc-ctrls.h | 181 ++++++++ + include/media/hevc-ctrls.h | 182 ++++++++ include/media/v4l2-ctrls.h | 7 + - include/uapi/linux/videodev2.h | 1 + - 10 files changed, 679 insertions(+) + 8 files changed, 672 insertions(+), 3 deletions(-) create mode 100644 include/media/hevc-ctrls.h diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst -index 3fc3f7ff338a..b4b3fcec55dd 100644 +index 8f4eb8823d82..e38ef5ee4209 100644 --- a/Documentation/media/uapi/v4l/biblio.rst +++ b/Documentation/media/uapi/v4l/biblio.rst -@@ -131,6 +131,15 @@ ITU H.264 +@@ -131,6 +131,15 @@ ITU-T Rec. H.264 Specification (04/2017 Edition) :author: International Telecommunication Union (http://www.itu.ch) @@ -117,39 +52,457 @@ index 3fc3f7ff338a..b4b3fcec55dd 100644 .. _jfif: JFIF -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index b6f857ac1a8e..ee82526cdc00 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -138,6 +138,21 @@ Compressed Formats - - ``V4L2_PIX_FMT_HEVC`` - - 'HEVC' - - HEVC/H.265 video elementary stream. -+ * .. _V4L2-PIX-FMT-HEVC-SLICE: +diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +index b0c178f0ff9b..19e5bfba888b 100644 +--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst ++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +@@ -1981,9 +1981,9 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - + - ``reference_ts`` + - Timestamp of the V4L2 capture buffer to use as reference, used + with B-coded and P-coded frames. The timestamp refers to the +- ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the +- :c:func:`v4l2_timeval_to_ns()` function to convert the struct +- :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. ++ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the ++ :c:func:`v4l2_timeval_to_ns()` function to convert the struct ++ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. + * - __u16 + - ``frame_num`` + - +@@ -3291,3 +3291,426 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + Indicates whether to generate SPS and PPS at every IDR. Setting it to 0 + disables generating SPS and PPS at every IDR. Setting it to one enables + generating SPS and PPS at every IDR. + -+ - ``V4L2_PIX_FMT_HEVC_SLICE`` -+ - 'S265' -+ - HEVC parsed slice data, as extracted from the HEVC bitstream. -+ This format is adapted for stateless video decoders that implement a -+ HEVC pipeline (using the :ref:`codec` and :ref:`media-request-api`). -+ Metadata associated with the frame to decode is required to be passed -+ through the following controls : -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` -+ See the :ref:`associated Codec Control IDs `. -+ Buffers associated with this pixel format must contain the appropriate -+ number of macroblocks to decode a full corresponding frame. - * .. _V4L2-PIX-FMT-FWHT: - - - ``V4L2_PIX_FMT_FWHT`` ++.. _v4l2-mpeg-hevc: ++ ++``V4L2_CID_MPEG_VIDEO_HEVC_SPS (struct)`` ++ Specifies the Sequence Parameter Set fields (as extracted from the ++ bitstream) for the associated HEVC slice data. ++ These bitstream parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.3.2 "Sequence parameter set RBSP ++ semantics" of the specification. ++ ++.. c:type:: v4l2_ctrl_hevc_sps ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_hevc_sps ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``chroma_format_idc`` ++ - ++ * - __u8 ++ - ``separate_colour_plane_flag`` ++ - ++ * - __u16 ++ - ``pic_width_in_luma_samples`` ++ - ++ * - __u16 ++ - ``pic_height_in_luma_samples`` ++ - ++ * - __u8 ++ - ``bit_depth_luma_minus8`` ++ - ++ * - __u8 ++ - ``bit_depth_chroma_minus8`` ++ - ++ * - __u8 ++ - ``log2_max_pic_order_cnt_lsb_minus4`` ++ - ++ * - __u8 ++ - ``sps_max_dec_pic_buffering_minus1`` ++ - ++ * - __u8 ++ - ``sps_max_num_reorder_pics`` ++ - ++ * - __u8 ++ - ``sps_max_latency_increase_plus1`` ++ - ++ * - __u8 ++ - ``log2_min_luma_coding_block_size_minus3`` ++ - ++ * - __u8 ++ - ``log2_diff_max_min_luma_coding_block_size`` ++ - ++ * - __u8 ++ - ``log2_min_luma_transform_block_size_minus2`` ++ - ++ * - __u8 ++ - ``log2_diff_max_min_luma_transform_block_size`` ++ - ++ * - __u8 ++ - ``max_transform_hierarchy_depth_inter`` ++ - ++ * - __u8 ++ - ``max_transform_hierarchy_depth_intra`` ++ - ++ * - __u8 ++ - ``scaling_list_enabled_flag`` ++ - ++ * - __u8 ++ - ``amp_enabled_flag`` ++ - ++ * - __u8 ++ - ``sample_adaptive_offset_enabled_flag`` ++ - ++ * - __u8 ++ - ``pcm_enabled_flag`` ++ - ++ * - __u8 ++ - ``pcm_sample_bit_depth_luma_minus1`` ++ - ++ * - __u8 ++ - ``pcm_sample_bit_depth_chroma_minus1`` ++ - ++ * - __u8 ++ - ``log2_min_pcm_luma_coding_block_size_minus3`` ++ - ++ * - __u8 ++ - ``log2_diff_max_min_pcm_luma_coding_block_size`` ++ - ++ * - __u8 ++ - ``pcm_loop_filter_disabled_flag`` ++ - ++ * - __u8 ++ - ``num_short_term_ref_pic_sets`` ++ - ++ * - __u8 ++ - ``long_term_ref_pics_present_flag`` ++ - ++ * - __u8 ++ - ``num_long_term_ref_pics_sps`` ++ - ++ * - __u8 ++ - ``sps_temporal_mvp_enabled_flag`` ++ - ++ * - __u8 ++ - ``strong_intra_smoothing_enabled_flag`` ++ - ++ ++``V4L2_CID_MPEG_VIDEO_HEVC_PPS (struct)`` ++ Specifies the Picture Parameter Set fields (as extracted from the ++ bitstream) for the associated HEVC slice data. ++ These bitstream parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.3.3 "Picture parameter set RBSP ++ semantics" of the specification. ++ ++.. c:type:: v4l2_ctrl_hevc_pps ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_hevc_pps ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``dependent_slice_segment_flag`` ++ - ++ * - __u8 ++ - ``output_flag_present_flag`` ++ - ++ * - __u8 ++ - ``num_extra_slice_header_bits`` ++ - ++ * - __u8 ++ - ``sign_data_hiding_enabled_flag`` ++ - ++ * - __u8 ++ - ``cabac_init_present_flag`` ++ - ++ * - __s8 ++ - ``init_qp_minus26`` ++ - ++ * - __u8 ++ - ``constrained_intra_pred_flag`` ++ - ++ * - __u8 ++ - ``transform_skip_enabled_flag`` ++ - ++ * - __u8 ++ - ``cu_qp_delta_enabled_flag`` ++ - ++ * - __u8 ++ - ``diff_cu_qp_delta_depth`` ++ - ++ * - __s8 ++ - ``pps_cb_qp_offset`` ++ - ++ * - __s8 ++ - ``pps_cr_qp_offset`` ++ - ++ * - __u8 ++ - ``pps_slice_chroma_qp_offsets_present_flag`` ++ - ++ * - __u8 ++ - ``weighted_pred_flag`` ++ - ++ * - __u8 ++ - ``weighted_bipred_flag`` ++ - ++ * - __u8 ++ - ``transquant_bypass_enabled_flag`` ++ - ++ * - __u8 ++ - ``tiles_enabled_flag`` ++ - ++ * - __u8 ++ - ``entropy_coding_sync_enabled_flag`` ++ - ++ * - __u8 ++ - ``num_tile_columns_minus1`` ++ - ++ * - __u8 ++ - ``num_tile_rows_minus1`` ++ - ++ * - __u8 ++ - ``column_width_minus1[20]`` ++ - ++ * - __u8 ++ - ``row_height_minus1[22]`` ++ - ++ * - __u8 ++ - ``loop_filter_across_tiles_enabled_flag`` ++ - ++ * - __u8 ++ - ``pps_loop_filter_across_slices_enabled_flag`` ++ - ++ * - __u8 ++ - ``deblocking_filter_override_enabled_flag`` ++ - ++ * - __u8 ++ - ``pps_disable_deblocking_filter_flag`` ++ - ++ * - __s8 ++ - ``pps_beta_offset_div2`` ++ - ++ * - __s8 ++ - ``pps_tc_offset_div2`` ++ - ++ * - __u8 ++ - ``lists_modification_present_flag`` ++ - ++ * - __u8 ++ - ``log2_parallel_merge_level_minus2`` ++ - ++ * - __u8 ++ - ``slice_segment_header_extension_present_flag`` ++ - ++ ++``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (struct)`` ++ Specifies various slice-specific parameters, especially from the NAL unit ++ header, general slice segment header and weighted prediction parameter ++ parts of the bitstream. ++ These bitstream parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.7 "General slice segment header ++ semantics" of the specification. ++ ++.. c:type:: v4l2_ctrl_hevc_slice_params ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_hevc_slice_params ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``bit_size`` ++ - Size (in bits) of the current slice data. ++ * - __u32 ++ - ``data_bit_offset`` ++ - Offset (in bits) to the video data in the current slice data. ++ * - __u8 ++ - ``nal_unit_type`` ++ - ++ * - __u8 ++ - ``nuh_temporal_id_plus1`` ++ - ++ * - __u8 ++ - ``slice_type`` ++ - ++ (V4L2_HEVC_SLICE_TYPE_I, V4L2_HEVC_SLICE_TYPE_P or ++ V4L2_HEVC_SLICE_TYPE_B). ++ * - __u8 ++ - ``colour_plane_id`` ++ - ++ * - __u16 ++ - ``slice_pic_order_cnt`` ++ - ++ * - __u8 ++ - ``slice_sao_luma_flag`` ++ - ++ * - __u8 ++ - ``slice_sao_chroma_flag`` ++ - ++ * - __u8 ++ - ``slice_temporal_mvp_enabled_flag`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l0_active_minus1`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l1_active_minus1`` ++ - ++ * - __u8 ++ - ``mvd_l1_zero_flag`` ++ - ++ * - __u8 ++ - ``cabac_init_flag`` ++ - ++ * - __u8 ++ - ``collocated_from_l0_flag`` ++ - ++ * - __u8 ++ - ``collocated_ref_idx`` ++ - ++ * - __u8 ++ - ``five_minus_max_num_merge_cand`` ++ - ++ * - __u8 ++ - ``use_integer_mv_flag`` ++ - ++ * - __s8 ++ - ``slice_qp_delta`` ++ - ++ * - __s8 ++ - ``slice_cb_qp_offset`` ++ - ++ * - __s8 ++ - ``slice_cr_qp_offset`` ++ - ++ * - __s8 ++ - ``slice_act_y_qp_offset`` ++ - ++ * - __s8 ++ - ``slice_act_cb_qp_offset`` ++ - ++ * - __s8 ++ - ``slice_act_cr_qp_offset`` ++ - ++ * - __u8 ++ - ``slice_deblocking_filter_disabled_flag`` ++ - ++ * - __s8 ++ - ``slice_beta_offset_div2`` ++ - ++ * - __s8 ++ - ``slice_tc_offset_div2`` ++ - ++ * - __u8 ++ - ``slice_loop_filter_across_slices_enabled_flag`` ++ - ++ * - __u8 ++ - ``pic_struct`` ++ - ++ * - struct :c:type:`v4l2_hevc_dpb_entry` ++ - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - The decoded picture buffer, for meta-data about reference frames. ++ * - __u8 ++ - ``num_active_dpb_entries`` ++ - The number of entries in ``dpb``. ++ * - __u8 ++ - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - The list of L0 reference elements as indices in the DPB. ++ * - __u8 ++ - ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - The list of L1 reference elements as indices in the DPB. ++ * - __u8 ++ - ``num_rps_poc_st_curr_before`` ++ - The number of reference pictures in the short-term set that come before ++ the current frame. ++ * - __u8 ++ - ``num_rps_poc_st_curr_after`` ++ - The number of reference pictures in the short-term set that come after ++ the current frame. ++ * - __u8 ++ - ``num_rps_poc_lt_curr`` ++ - The number of reference pictures in the long-term set. ++ * - struct :c:type:`v4l2_hevc_pred_weight_table` ++ - ``pred_weight_table`` ++ - The prediction weight coefficients for inter-picture prediction. ++ ++.. c:type:: v4l2_hevc_dpb_entry ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_hevc_dpb_entry ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u64 ++ - ``timestamp`` ++ - Timestamp of the V4L2 capture buffer to use as reference, used ++ with B-coded and P-coded frames. The timestamp refers to the ++ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the ++ :c:func:`v4l2_timeval_to_ns()` function to convert the struct ++ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. ++ * - __u8 ++ - ``rps`` ++ - The reference set for the reference frame ++ (V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE, ++ V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER or ++ V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) ++ * - __u8 ++ - ``field_pic`` ++ - Whether the reference is a field picture or a frame. ++ * - __u16 ++ - ``pic_order_cnt[2]`` ++ - The picture order count of the reference. Only the first element of the ++ array is used for frame pictures, while the first element identifies the ++ top field and the second the bottom field in field-coded pictures. ++ ++.. c:type:: v4l2_hevc_pred_weight_table ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_hevc_pred_weight_table ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``luma_log2_weight_denom`` ++ - ++ * - __s8 ++ - ``delta_chroma_log2_weight_denom`` ++ - ++ * - __s8 ++ - ``delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - ++ * - __s8 ++ - ``luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - ++ * - __s8 ++ - ``delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` ++ - ++ * - __s8 ++ - ``chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` ++ - ++ * - __s8 ++ - ``delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - ++ * - __s8 ++ - ``luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - ++ * - __s8 ++ - ``delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` ++ - ++ * - __s8 ++ - ``chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` ++ - diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -index bf29dc5b9758..f37cb377e258 100644 +index dc500632095d..e090ef33231c 100644 --- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst @@ -473,6 +473,24 @@ See also the examples in :ref:`control`. - n/a - - A struct :c:type:`v4l2_ctrl_h264_decode_param`, containing H264 + - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 decode parameters for stateless video decoders. + * - ``V4L2_CTRL_TYPE_HEVC_SPS`` + - n/a @@ -187,10 +540,10 @@ index 55cbe324b9fc..afba7d71971a 100644 # V4L2 capability defines replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 366200d31bc0..106c80ec9312 100644 +index b72dc54ba638..d93717697402 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -916,6 +916,9 @@ const char *v4l2_ctrl_get_name(u32 id) +@@ -944,6 +944,9 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD: return "HEVC Size of Length Field"; case V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES: return "Reference Frames for a P-Frame"; case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: return "Prepend SPS and PPS to IDR"; @@ -200,7 +553,7 @@ index 366200d31bc0..106c80ec9312 100644 /* CAMERA controls */ /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1323,6 +1326,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, +@@ -1357,6 +1360,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; break; @@ -216,7 +569,7 @@ index 366200d31bc0..106c80ec9312 100644 default: *type = V4L2_CTRL_TYPE_INTEGER; break; -@@ -1696,6 +1708,11 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, +@@ -1733,6 +1745,11 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: return 0; @@ -228,9 +581,9 @@ index 366200d31bc0..106c80ec9312 100644 default: return -EINVAL; } -@@ -2291,6 +2308,15 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, +@@ -2331,6 +2348,15 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_h264_decode_param); + elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); break; + case V4L2_CTRL_TYPE_HEVC_SPS: + elem_size = sizeof(struct v4l2_ctrl_hevc_sps); @@ -245,23 +598,23 @@ index 366200d31bc0..106c80ec9312 100644 if (type < V4L2_CTRL_COMPOUND_TYPES) elem_size = sizeof(s32); diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 8aa7de17ecfa..e792fc97e263 100644 +index f6e1254064d2..0960f719da5d 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1331,6 +1331,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) +@@ -1337,6 +1337,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_VP8: descr = "VP8"; break; case V4L2_PIX_FMT_VP9: descr = "VP9"; break; case V4L2_PIX_FMT_HEVC: descr = "HEVC"; break; /* aka H.265 */ + case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ + case V4L2_PIX_FMT_FWHT_STATELESS: descr = "FWHT Stateless"; break; /* used in vicodec */ case V4L2_PIX_FMT_CPIA1: descr = "GSPCA CPiA YUV"; break; - case V4L2_PIX_FMT_WNVA: descr = "WNVA"; break; diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h new file mode 100644 -index 000000000000..005c71c67163 +index 000000000000..9ea013c88afc --- /dev/null +++ b/include/media/hevc-ctrls.h -@@ -0,0 +1,181 @@ +@@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * These are the HEVC state controls for use with stateless HEVC @@ -275,19 +628,20 @@ index 000000000000..005c71c67163 +#ifndef _HEVC_CTRLS_H_ +#define _HEVC_CTRLS_H_ + -+#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 645) -+#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 646) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 647) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) ++#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) + +/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_HEVC_SPS 0x0115 -+#define V4L2_CTRL_TYPE_HEVC_PPS 0x0116 -+#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0117 ++#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 ++#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 ++#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 + +#define V4L2_HEVC_SLICE_TYPE_B 0 +#define V4L2_HEVC_SLICE_TYPE_P 1 +#define V4L2_HEVC_SLICE_TYPE_I 2 + ++/* The controls are not stable at the moment and will likely be reworked. */ +struct v4l2_ctrl_hevc_sps { + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + __u8 chroma_format_idc; @@ -444,120 +798,137 @@ index 000000000000..005c71c67163 + +#endif diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index 22b6d09c4764..f24a835e5920 100644 +index a8aede26491e..630083e1936d 100644 --- a/include/media/v4l2-ctrls.h +++ b/include/media/v4l2-ctrls.h -@@ -28,6 +28,7 @@ - */ +@@ -29,6 +29,7 @@ #include + #include #include +#include /* forward references */ struct file; -@@ -55,6 +56,9 @@ struct poll_table_struct; +@@ -57,6 +58,9 @@ struct poll_table_struct; * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. - * @p_h264_slice_param: Pointer to a struct v4l2_ctrl_h264_slice_params. - * @p_h264_decode_param: Pointer to a struct v4l2_ctrl_h264_decode_params. + * @p_h264_slice_params: Pointer to a struct v4l2_ctrl_h264_slice_params. + * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. + * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. + * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. + * @p_hevc_slice_params Pointer to an HEVC slice parameters structure. * @p: Pointer to a compound value. */ union v4l2_ctrl_ptr { -@@ -71,6 +75,9 @@ union v4l2_ctrl_ptr { +@@ -74,6 +78,9 @@ union v4l2_ctrl_ptr { struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; - struct v4l2_ctrl_h264_slice_params *p_h264_slice_param; - struct v4l2_ctrl_h264_decode_params *p_h264_decode_param; + struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; + struct v4l2_ctrl_h264_decode_params *p_h264_decode_params; + struct v4l2_ctrl_hevc_sps *p_hevc_sps; + struct v4l2_ctrl_hevc_pps *p_hevc_pps; + struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; void *p; }; -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 673172c84fb9..5ae4f00f4078 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -669,6 +669,7 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ - #define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ - #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */ -+#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ - #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */ - - /* Vendor-specific formats */ +-- +2.21.0 -From patchwork Thu Feb 14 09:53:09 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Paul Kocialkowski -X-Patchwork-Id: 10812215 -Return-Path: -Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org - [172.30.200.125]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE979746 - for ; - Thu, 14 Feb 2019 09:54:56 +0000 (UTC) -Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB33928703 - for ; - Thu, 14 Feb 2019 09:54:56 +0000 (UTC) -Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) - id 9ED1728752; Thu, 14 Feb 2019 09:54:56 +0000 (UTC) -X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on - pdx-wl-mail.web.codeaurora.org -X-Spam-Level: -X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, - RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 -Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6651528703 - for ; - Thu, 14 Feb 2019 09:54:54 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S2438109AbfBNJys (ORCPT - ); - Thu, 14 Feb 2019 04:54:48 -0500 -Received: from relay8-d.mail.gandi.net ([217.70.183.201]:40921 "EHLO - relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S2392881AbfBNJyq (ORCPT - ); - Thu, 14 Feb 2019 04:54:46 -0500 -X-Originating-IP: 90.88.30.68 -Received: from localhost.localdomain - (aaubervilliers-681-1-89-68.w90-88.abo.wanadoo.fr [90.88.30.68]) - (Authenticated sender: paul.kocialkowski@bootlin.com) - by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 2F2A01BF219; - Thu, 14 Feb 2019 09:54:39 +0000 (UTC) +From dd424b21e39cd7e65a40298ddbaba468878ad1f5 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski -To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, - devel@driverdev.osuosl.org, linux-arm-kernel@lists.infradead.org, - linux-sunxi@googlegroups.com -Cc: Mauro Carvalho Chehab , - Maxime Ripard , - Paul Kocialkowski , - Greg Kroah-Hartman , - Chen-Yu Tsai , - Thomas Petazzoni , - Hans Verkuil , - Sakari Ailus , - Randy Li , - Ezequiel Garcia , - Tomasz Figa , - Alexandre Courbot -Subject: [PATCH v3 2/2] media: cedrus: Add HEVC/H.265 decoding support -Date: Thu, 14 Feb 2019 10:53:09 +0100 -Message-Id: <20190214095309.19594-3-paul.kocialkowski@bootlin.com> -X-Mailer: git-send-email 2.20.1 -In-Reply-To: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> -References: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> -MIME-Version: 1.0 -Sender: linux-media-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-media@vger.kernel.org -X-Virus-Scanned: ClamAV using ClamSMTP +Date: Fri, 24 May 2019 11:36:33 +0200 +Subject: [PATCH 10/12] media: pixfmt: Add HEVC slice pixel format + +Introduce the V4L2_PIX_FMT_HEVC_SLICE pixel format, which currently +describes an output buffer with enough appended slice data for +producing one decoded frame with a stateless video decoder. + +This will need to be reworked (along with the controls and the core) to +allow passing slice data individually, as it is the natural decoding +unit in HEVC. + +We also need to figure out the description of the possible source data: +* Compressed slice data only, with slice controls attached; +* Slice data in Annex-B format (with raw slice header), without slice + controls attached; +* Slice data in Annex-B format (with raw slice header), with slice + controls attached. + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +--- + include/media/hevc-ctrls.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h +index 9ea013c88afc..2de83d9f6d47 100644 +--- a/include/media/hevc-ctrls.h ++++ b/include/media/hevc-ctrls.h +@@ -11,6 +11,9 @@ + #ifndef _HEVC_CTRLS_H_ + #define _HEVC_CTRLS_H_ + ++/* The pixel format isn't stable at the moment and will likely be renamed. */ ++#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ ++ + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) +-- +2.21.0 + +From 256c89e4dd0621198cad6fbf0689682116cad795 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Fri, 24 May 2019 11:36:34 +0200 +Subject: [PATCH 11/12] media: pixfmt: Document the HEVC slice pixel format + +Document the current state of the HEVC slice pixel format. +The format will need to evolve in the future, which is why it is +not part of the public API. + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +--- + .../media/uapi/v4l/pixfmt-compressed.rst | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +index 4b701fc7653e..9d4195723c3e 100644 +--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst ++++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +@@ -143,6 +143,27 @@ Compressed Formats + - ``V4L2_PIX_FMT_HEVC`` + - 'HEVC' + - HEVC/H.265 video elementary stream. ++ * .. _V4L2-PIX-FMT-HEVC-SLICE: ++ ++ - ``V4L2_PIX_FMT_HEVC_SLICE`` ++ - 'S265' ++ - HEVC parsed slice data, as extracted from the HEVC bitstream. ++ This format is adapted for stateless video decoders that implement a ++ HEVC pipeline (using the :ref:`codec` and :ref:`media-request-api`). ++ Metadata associated with the frame to decode is required to be passed ++ through the following controls : ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` ++ See the :ref:`associated Codec Control IDs `. ++ Buffers associated with this pixel format must contain the appropriate ++ number of macroblocks to decode a full corresponding frame. ++ ++ .. note:: ++ ++ This format is not yet part of the public kernel API and it ++ is expected to change. ++ + * .. _V4L2-PIX-FMT-FWHT: + + - ``V4L2_PIX_FMT_FWHT`` +-- +2.21.0 + +From ef19574101a1e649c440c43615420b7047f8f4ef Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Fri, 24 May 2019 11:36:35 +0200 +Subject: [PATCH 12/12] media: cedrus: Add HEVC/H.265 decoding support This introduces support for HEVC/H.265 to the Cedrus VPU driver, with both uni-directional and bi-directional prediction modes supported. @@ -566,37 +937,37 @@ Field-coded (interlaced) pictures, custom quantization matrices and 10-bit output are not supported at this point. Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil --- drivers/staging/media/sunxi/cedrus/Makefile | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus.c | 27 +- + drivers/staging/media/sunxi/cedrus/cedrus.c | 31 +- drivers/staging/media/sunxi/cedrus/cedrus.h | 18 + .../staging/media/sunxi/cedrus/cedrus_dec.c | 9 + - .../staging/media/sunxi/cedrus/cedrus_h265.c | 531 ++++++++++++++++++ + .../staging/media/sunxi/cedrus/cedrus_h265.c | 532 ++++++++++++++++++ .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 + .../staging/media/sunxi/cedrus/cedrus_regs.h | 290 ++++++++++ .../staging/media/sunxi/cedrus/cedrus_video.c | 10 + - 8 files changed, 887 insertions(+), 4 deletions(-) + 8 files changed, 891 insertions(+), 5 deletions(-) create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h265.c diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile -index aaf141fc58b6..186cb6d01b67 100644 +index c85ac6db0302..1bce49d3e7e2 100644 --- a/drivers/staging/media/sunxi/cedrus/Makefile +++ b/drivers/staging/media/sunxi/cedrus/Makefile -@@ -1,4 +1,4 @@ +@@ -2,4 +2,4 @@ obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ - cedrus_mpeg2.o cedrus_h264.o + cedrus_mpeg2.o cedrus_h264.o cedrus_h265.o diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index b275607b8111..a713630ce7ba 100644 +index 370937edfc14..70642834f351 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -68,6 +68,23 @@ static const struct cedrus_control cedrus_controls[] = { - .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, - .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), +@@ -70,6 +70,24 @@ static const struct cedrus_control cedrus_controls[] = { .codec = CEDRUS_CODEC_H264, -+ }, + .required = true, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, + .elem_size = sizeof(struct v4l2_ctrl_hevc_sps), @@ -613,10 +984,12 @@ index b275607b8111..a713630ce7ba 100644 + .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, + .elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params), + .codec = CEDRUS_CODEC_H265, - .required = true, - }, ++ .required = true, ++ }, }; -@@ -309,6 +326,7 @@ static int cedrus_probe(struct platform_device *pdev) + + #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) +@@ -309,6 +327,7 @@ static int cedrus_probe(struct platform_device *pdev) dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; @@ -624,38 +997,49 @@ index b275607b8111..a713630ce7ba 100644 mutex_init(&dev->dev_mutex); -@@ -416,15 +434,18 @@ static const struct cedrus_variant sun8i_a33_cedrus_variant = { +@@ -417,22 +436,26 @@ static const struct cedrus_variant sun8i_a33_cedrus_variant = { }; static const struct cedrus_variant sun8i_h3_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, + .capabilities = CEDRUS_CAPABILITY_UNTILED | + CEDRUS_CAPABILITY_H265_DEC, + .mod_rate = 402000000, }; static const struct cedrus_variant sun50i_a64_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, + .capabilities = CEDRUS_CAPABILITY_UNTILED | + CEDRUS_CAPABILITY_H265_DEC, + .mod_rate = 402000000, }; static const struct cedrus_variant sun50i_h5_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, + .capabilities = CEDRUS_CAPABILITY_UNTILED | + CEDRUS_CAPABILITY_H265_DEC, + .mod_rate = 402000000, }; - static const struct of_device_id cedrus_dt_match[] = { + static const struct cedrus_variant sun50i_h6_cedrus_variant = { +- .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .capabilities = CEDRUS_CAPABILITY_UNTILED | ++ CEDRUS_CAPABILITY_H265_DEC, + .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, + .mod_rate = 600000000, + }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index 8c64f9a27e9d..b5d083812bea 100644 +index 3f476d0fd981..f19be772d78b 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -27,10 +27,12 @@ +@@ -27,12 +27,14 @@ #define CEDRUS_NAME "cedrus" #define CEDRUS_CAPABILITY_UNTILED BIT(0) +#define CEDRUS_CAPABILITY_H265_DEC BIT(1) + #define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) + enum cedrus_codec { CEDRUS_CODEC_MPEG2, CEDRUS_CODEC_H264, @@ -663,7 +1047,7 @@ index 8c64f9a27e9d..b5d083812bea 100644 CEDRUS_CODEC_LAST, }; -@@ -66,6 +68,12 @@ struct cedrus_mpeg2_run { +@@ -68,6 +70,12 @@ struct cedrus_mpeg2_run { const struct v4l2_ctrl_mpeg2_quantization *quantization; }; @@ -676,7 +1060,7 @@ index 8c64f9a27e9d..b5d083812bea 100644 struct cedrus_run { struct vb2_v4l2_buffer *src; struct vb2_v4l2_buffer *dst; -@@ -73,6 +81,7 @@ struct cedrus_run { +@@ -75,6 +83,7 @@ struct cedrus_run { union { struct cedrus_h264_run h264; struct cedrus_mpeg2_run mpeg2; @@ -684,7 +1068,7 @@ index 8c64f9a27e9d..b5d083812bea 100644 }; }; -@@ -111,6 +120,14 @@ struct cedrus_ctx { +@@ -113,6 +122,14 @@ struct cedrus_ctx { void *neighbor_info_buf; dma_addr_t neighbor_info_buf_dma; } h264; @@ -699,7 +1083,7 @@ index 8c64f9a27e9d..b5d083812bea 100644 } codec; }; -@@ -154,6 +171,7 @@ struct cedrus_dev { +@@ -158,6 +175,7 @@ struct cedrus_dev { extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; extern struct cedrus_dec_ops cedrus_dec_ops_h264; @@ -708,10 +1092,10 @@ index 8c64f9a27e9d..b5d083812bea 100644 static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) { diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index abf17dc18ecf..c50397f8692f 100644 +index bdad87eb9d79..c6d0ef66cdd0 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -61,6 +61,15 @@ void cedrus_device_run(void *priv) +@@ -59,6 +59,15 @@ void cedrus_device_run(void *priv) V4L2_CID_MPEG_VIDEO_H264_SPS); break; @@ -729,10 +1113,10 @@ index abf17dc18ecf..c50397f8692f 100644 } diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c new file mode 100644 -index 000000000000..f1c3665e95ab +index 000000000000..fd4d86b02156 --- /dev/null +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -0,0 +1,531 @@ +@@ -0,0 +1,532 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Cedrus VPU driver @@ -849,16 +1233,17 @@ index 000000000000..f1c3665e95ab + u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + + VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; + struct cedrus_h265_sram_frame_info frame_info = { -+ .top_pic_order_cnt = pic_order_cnt[0], -+ .bottom_pic_order_cnt = field_pic ? pic_order_cnt[1] : -+ pic_order_cnt[0], ++ .top_pic_order_cnt = cpu_to_le32(pic_order_cnt[0]), ++ .bottom_pic_order_cnt = cpu_to_le32(field_pic ? ++ pic_order_cnt[1] : ++ pic_order_cnt[0]), + .top_mv_col_buf_addr = -+ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0]), -+ .bottom_mv_col_buf_addr = field_pic ? ++ cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])), ++ .bottom_mv_col_buf_addr = cpu_to_le32(field_pic ? + VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) : -+ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0]), -+ .luma_addr = VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr), -+ .chroma_addr = VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr), ++ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])), ++ .luma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr)), ++ .chroma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr)), + }; + + cedrus_h265_sram_write_offset(dev, offset); @@ -925,7 +1310,7 @@ index 000000000000..f1c3665e95ab + u32 sram_luma_offset, + u32 sram_chroma_offset) +{ -+ struct cedrus_h265_sram_pred_weight pred_weight[2] = { 0 }; ++ struct cedrus_h265_sram_pred_weight pred_weight[2] = { { 0 } }; + unsigned int i, j; + + cedrus_h265_sram_write_offset(dev, sram_luma_offset); @@ -1265,7 +1650,7 @@ index 000000000000..f1c3665e95ab + .trigger = cedrus_h265_trigger, +}; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index ab402b0cac4e..6be604c52d5c 100644 +index c34aec7c6e40..7d2f6eedfc28 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c @@ -50,6 +50,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) @@ -1592,7 +1977,7 @@ index 3e9931416e45..87651d6b6227 100644 #define VE_H264_SPS_MBS_ONLY BIT(18) #define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index d1c0562d1a62..b871976b5ead 100644 +index e2b530b1a956..6cc65d85cf98 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c @@ -41,6 +41,11 @@ static struct cedrus_format cedrus_formats[] = { @@ -1626,3 +2011,5 @@ index d1c0562d1a62..b871976b5ead 100644 default: return -EINVAL; } +-- +2.21.0 diff --git a/projects/Allwinner/patches/linux/0011-hdmi-init-fix.patch b/projects/Allwinner/patches/linux/0005-hdmi-init-fix.patch similarity index 100% rename from projects/Allwinner/patches/linux/0011-hdmi-init-fix.patch rename to projects/Allwinner/patches/linux/0005-hdmi-init-fix.patch diff --git a/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch b/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch deleted file mode 100644 index 923ccba80d..0000000000 --- a/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch +++ /dev/null @@ -1,1420 +0,0 @@ -Date: Thu, 4 Apr 2019 14:59:02 +0200 - -From: Pawel Osciak - -Stateless video codecs will require both the H264 metadata and slices in -order to be able to decode frames. - -This introduces the definitions for a new pixel format for H264 slices that -have been parsed, as well as the structures used to pass the metadata from -the userspace to the kernel. - -Reviewed-by: Tomasz Figa -Signed-off-by: Pawel Osciak -Signed-off-by: Guenter Roeck -Co-developed-by: Maxime Ripard -Signed-off-by: Maxime Ripard ---- - Documentation/media/uapi/v4l/biblio.rst | 9 +- - Documentation/media/uapi/v4l/ext-ctrls-codec.rst | 569 ++++++++++++++- - Documentation/media/uapi/v4l/pixfmt-compressed.rst | 19 +- - Documentation/media/uapi/v4l/vidioc-queryctrl.rst | 30 +- - Documentation/media/videodev2.h.rst.exceptions | 5 +- - drivers/media/v4l2-core/v4l2-ctrls.c | 42 +- - drivers/media/v4l2-core/v4l2-ioctl.c | 1 +- - include/media/h264-ctrls.h | 192 +++++- - include/media/v4l2-ctrls.h | 13 +- - include/uapi/linux/videodev2.h | 1 +- - 10 files changed, 880 insertions(+), 1 deletion(-) - create mode 100644 include/media/h264-ctrls.h - -diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst -index ec33768c055e..8f4eb8823d82 100644 ---- a/Documentation/media/uapi/v4l/biblio.rst -+++ b/Documentation/media/uapi/v4l/biblio.rst -@@ -122,6 +122,15 @@ ITU BT.1119 - - :author: International Telecommunication Union (http://www.itu.ch) - -+.. _h264: -+ -+ITU-T Rec. H.264 Specification (04/2017 Edition) -+================================================ -+ -+:title: ITU-T Recommendation H.264 "Advanced Video Coding for Generic Audiovisual Services" -+ -+:author: International Telecommunication Union (http://www.itu.ch) -+ - .. _jfif: - - JFIF -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index 6c961cfb74da..ea0a8a68759b 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -52,6 +52,25 @@ Compressed Formats - - ``V4L2_PIX_FMT_H264_MVC`` - - 'M264' - - H264 MVC video elementary stream. -+ * .. _V4L2-PIX-FMT-H264-SLICE: -+ -+ - ``V4L2_PIX_FMT_H264_SLICE_RAW`` -+ - 'S264' -+ - H264 parsed slice data, as extracted from the H264 bitstream. -+ This format is adapted for stateless video decoders that -+ implement an H264 pipeline (using the :ref:`codec` and -+ :ref:`media-request-api`). Metadata associated with the frame -+ to decode are required to be passed through the -+ ``V4L2_CID_MPEG_VIDEO_H264_SPS``, -+ ``V4L2_CID_MPEG_VIDEO_H264_PPS``, -+ ``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``, -+ ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS`` and -+ ``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS`` controls. See the -+ :ref:`associated Codec Control IDs `. -+ Exactly one output and one capture buffer must be provided for -+ use with this pixel format. The output buffer must contain the -+ appropriate number of macroblocks to decode a full -+ corresponding frame to the matching capture buffer. - * .. _V4L2-PIX-FMT-H263: - - - ``V4L2_PIX_FMT_H263`` -diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -index f824162d0ea9..dc500632095d 100644 ---- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -+++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -@@ -443,6 +443,36 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_mpeg2_quantization`, containing MPEG-2 - quantization matrices for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_sps`, containing H264 -+ sequence parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_PPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_pps`, containing H264 -+ picture parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SCALING_MATRIX`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_scaling_matrix`, containing H264 -+ scaling matrices for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SLICE_PARAMS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_slice_params`, containing H264 -+ slice parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_DECODE_PARAMS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 -+ decode parameters for stateless video decoders. - - .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| - -diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions -index 64d348e67df9..55cbe324b9fc 100644 ---- a/Documentation/media/videodev2.h.rst.exceptions -+++ b/Documentation/media/videodev2.h.rst.exceptions -@@ -136,6 +136,11 @@ replace symbol V4L2_CTRL_TYPE_U32 :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_U8 :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_MPEG2_QUANTIZATION :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` - - # V4L2 capability defines - replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index b1ae2e555c68..46aec8c3acde 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -828,6 +828,11 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: - return "H264 Constrained Intra Pred"; - case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: return "H264 Chroma QP Index Offset"; -+ case V4L2_CID_MPEG_VIDEO_H264_SPS: return "H264 Sequence Parameter Set"; -+ case V4L2_CID_MPEG_VIDEO_H264_PPS: return "H264 Picture Parameter Set"; -+ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: return "H264 Scaling Matrix"; -+ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters"; -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters"; - case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; -@@ -1309,6 +1314,21 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: - *type = V4L2_CTRL_TYPE_FWHT_PARAMS; - break; -+ case V4L2_CID_MPEG_VIDEO_H264_SPS: -+ *type = V4L2_CTRL_TYPE_H264_SPS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_PPS: -+ *type = V4L2_CTRL_TYPE_H264_PPS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: -+ *type = V4L2_CTRL_TYPE_H264_SCALING_MATRIX; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: -+ *type = V4L2_CTRL_TYPE_H264_SLICE_PARAMS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: -+ *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; -+ break; - default: - *type = V4L2_CTRL_TYPE_INTEGER; - break; -@@ -1678,6 +1698,13 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, - case V4L2_CTRL_TYPE_FWHT_PARAMS: - return 0; - -+ case V4L2_CTRL_TYPE_H264_SPS: -+ case V4L2_CTRL_TYPE_H264_PPS: -+ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: -+ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: -+ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: -+ return 0; -+ - default: - return -EINVAL; - } -@@ -2261,6 +2288,21 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_FWHT_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_fwht_params); - break; -+ case V4L2_CTRL_TYPE_H264_SPS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_sps); -+ break; -+ case V4L2_CTRL_TYPE_H264_PPS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_pps); -+ break; -+ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: -+ elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix); -+ break; -+ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_slice_params); -+ break; -+ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); -+ break; - default: - if (type < V4L2_CTRL_COMPOUND_TYPES) - elem_size = sizeof(s32); -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index ac87c3e37280..f6e1254064d2 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1325,6 +1325,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_H264: descr = "H.264"; break; - case V4L2_PIX_FMT_H264_NO_SC: descr = "H.264 (No Start Codes)"; break; - case V4L2_PIX_FMT_H264_MVC: descr = "H.264 MVC"; break; -+ case V4L2_PIX_FMT_H264_SLICE_RAW: descr = "H.264 Parsed Slice Data"; break; - case V4L2_PIX_FMT_H263: descr = "H.263"; break; - case V4L2_PIX_FMT_MPEG1: descr = "MPEG-1 ES"; break; - case V4L2_PIX_FMT_MPEG2: descr = "MPEG-2 ES"; break; -diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h -new file mode 100644 -index 000000000000..e2f83b3cdbef ---- /dev/null -+++ b/include/media/h264-ctrls.h -@@ -0,0 +1,192 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * These are the H.264 state controls for use with stateless H.264 -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. -+ */ -+ -+#ifndef _H264_CTRLS_H_ -+#define _H264_CTRLS_H_ -+ -+/* -+ * This is put insanely high to avoid conflicting with controls that -+ * would be added during the phase where those controls are not -+ * stable. It should be fixed eventually. -+ */ -+#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+1000) -+#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+1001) -+#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) -+#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) -+#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) -+ -+/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_H264_SPS 0x0110 -+#define V4L2_CTRL_TYPE_H264_PPS 0x0111 -+#define V4L2_CTRL_TYPE_H264_SCALING_MATRIX 0x0112 -+#define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 -+#define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 -+ -+#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 -+#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 -+#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 -+#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 -+#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 -+#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 -+ -+#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 -+#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 -+#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 -+#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 -+#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 -+#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 -+#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 -+ -+struct v4l2_ctrl_h264_sps { -+ __u8 profile_idc; -+ __u8 constraint_set_flags; -+ __u8 level_idc; -+ __u8 seq_parameter_set_id; -+ __u8 chroma_format_idc; -+ __u8 bit_depth_luma_minus8; -+ __u8 bit_depth_chroma_minus8; -+ __u8 log2_max_frame_num_minus4; -+ __u8 pic_order_cnt_type; -+ __u8 log2_max_pic_order_cnt_lsb_minus4; -+ __u8 max_num_ref_frames; -+ __u8 num_ref_frames_in_pic_order_cnt_cycle; -+ __s32 offset_for_ref_frame[255]; -+ __s32 offset_for_non_ref_pic; -+ __s32 offset_for_top_to_bottom_field; -+ __u16 pic_width_in_mbs_minus1; -+ __u16 pic_height_in_map_units_minus1; -+ __u32 flags; -+}; -+ -+#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 -+#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 -+#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 -+#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 -+#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 -+#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 -+#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 -+#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 -+ -+struct v4l2_ctrl_h264_pps { -+ __u8 pic_parameter_set_id; -+ __u8 seq_parameter_set_id; -+ __u8 num_slice_groups_minus1; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; -+ __u8 weighted_bipred_idc; -+ __s8 pic_init_qp_minus26; -+ __s8 pic_init_qs_minus26; -+ __s8 chroma_qp_index_offset; -+ __s8 second_chroma_qp_index_offset; -+ __u16 flags; -+}; -+ -+struct v4l2_ctrl_h264_scaling_matrix { -+ __u8 scaling_list_4x4[6][16]; -+ __u8 scaling_list_8x8[6][64]; -+}; -+ -+struct v4l2_h264_weight_factors { -+ __s16 luma_weight[32]; -+ __s16 luma_offset[32]; -+ __s16 chroma_weight[32][2]; -+ __s16 chroma_offset[32][2]; -+}; -+ -+struct v4l2_h264_pred_weight_table { -+ __u16 luma_log2_weight_denom; -+ __u16 chroma_log2_weight_denom; -+ struct v4l2_h264_weight_factors weight_factors[2]; -+}; -+ -+#define V4L2_H264_SLICE_TYPE_P 0 -+#define V4L2_H264_SLICE_TYPE_B 1 -+#define V4L2_H264_SLICE_TYPE_I 2 -+#define V4L2_H264_SLICE_TYPE_SP 3 -+#define V4L2_H264_SLICE_TYPE_SI 4 -+ -+#define V4L2_H264_SLICE_FLAG_FIELD_PIC 0x01 -+#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD 0x02 -+#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 -+#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x08 -+ -+struct v4l2_ctrl_h264_slice_params { -+ /* Size in bytes, including header */ -+ __u32 size; -+ /* Offset in bits to slice_data() from the beginning of this slice. */ -+ __u32 header_bit_size; -+ -+ __u16 first_mb_in_slice; -+ __u8 slice_type; -+ __u8 pic_parameter_set_id; -+ __u8 colour_plane_id; -+ __u8 redundant_pic_cnt; -+ __u16 frame_num; -+ __u16 idr_pic_id; -+ __u16 pic_order_cnt_lsb; -+ __s32 delta_pic_order_cnt_bottom; -+ __s32 delta_pic_order_cnt0; -+ __s32 delta_pic_order_cnt1; -+ -+ struct v4l2_h264_pred_weight_table pred_weight_table; -+ /* Size in bits of dec_ref_pic_marking() syntax element. */ -+ __u32 dec_ref_pic_marking_bit_size; -+ /* Size in bits of pic order count syntax. */ -+ __u32 pic_order_cnt_bit_size; -+ -+ __u8 cabac_init_idc; -+ __s8 slice_qp_delta; -+ __s8 slice_qs_delta; -+ __u8 disable_deblocking_filter_idc; -+ __s8 slice_alpha_c0_offset_div2; -+ __s8 slice_beta_offset_div2; -+ __u8 num_ref_idx_l0_active_minus1; -+ __u8 num_ref_idx_l1_active_minus1; -+ __u32 slice_group_change_cycle; -+ -+ /* -+ * Entries on each list are indices into -+ * v4l2_ctrl_h264_decode_params.dpb[]. -+ */ -+ __u8 ref_pic_list0[32]; -+ __u8 ref_pic_list1[32]; -+ -+ __u32 flags; -+}; -+ -+#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 -+#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 -+#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 -+ -+struct v4l2_h264_dpb_entry { -+ __u64 reference_ts; -+ __u16 frame_num; -+ __u16 pic_num; -+ /* Note that field is indicated by v4l2_buffer.field */ -+ __s32 top_field_order_cnt; -+ __s32 bottom_field_order_cnt; -+ __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ -+}; -+ -+#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 -+ -+struct v4l2_ctrl_h264_decode_params { -+ struct v4l2_h264_dpb_entry dpb[16]; -+ __u16 num_slices; -+ __u16 nal_ref_idc; -+ __u8 ref_pic_list_p0[32]; -+ __u8 ref_pic_list_b0[32]; -+ __u8 ref_pic_list_b1[32]; -+ __s32 top_field_order_cnt; -+ __s32 bottom_field_order_cnt; -+ __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ -+}; -+ -+#endif -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index bd621cec65a5..dce6f33fd749 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -23,11 +23,12 @@ - #include - - /* -- * Include the mpeg2 and fwht stateless codec compound control definitions. -+ * Include the stateless codec compound control definitions. - * This will move to the public headers once this API is fully stable. - */ - #include - #include -+#include - - /* forward references */ - struct file; -@@ -51,6 +52,11 @@ struct poll_table_struct; - * @p_mpeg2_slice_params: Pointer to a MPEG2 slice parameters structure. - * @p_mpeg2_quantization: Pointer to a MPEG2 quantization data structure. - * @p_fwht_params: Pointer to a FWHT stateless parameters structure. -+ * @p_h264_sps: Pointer to a struct v4l2_ctrl_h264_sps. -+ * @p_h264_pps: Pointer to a struct v4l2_ctrl_h264_pps. -+ * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. -+ * @p_h264_slice_param: Pointer to a struct v4l2_ctrl_h264_slice_params. -+ * @p_h264_decode_param: Pointer to a struct v4l2_ctrl_h264_decode_params. - * @p: Pointer to a compound value. - */ - union v4l2_ctrl_ptr { -@@ -63,6 +69,11 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; - struct v4l2_ctrl_mpeg2_quantization *p_mpeg2_quantization; - struct v4l2_ctrl_fwht_params *p_fwht_params; -+ struct v4l2_ctrl_h264_sps *p_h264_sps; -+ struct v4l2_ctrl_h264_pps *p_h264_pps; -+ struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; -+ struct v4l2_ctrl_h264_slice_params *p_h264_slice_param; -+ struct v4l2_ctrl_h264_decode_params *p_h264_decode_param; - void *p; - }; - -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 496e6453450c..838732acdefc 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -657,6 +657,7 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ - #define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ - #define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */ -+#define V4L2_PIX_FMT_H264_SLICE_RAW v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ - #define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */ - #define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */ - #define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */ -From patchwork Thu Apr 4 12:59:03 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,2/2] media: cedrus: Add H264 decoding support -From: Maxime Ripard -X-Patchwork-Id: 55457 -Message-Id: <157519b5571e24c9ef4189d30f8434b5b61121b1.1554382670.git-series.maxime.ripard@bootlin.com> -X-Patchwork-Delegate: hverkuil@xs4all.nl -To: hans.verkuil@cisco.com, acourbot@chromium.org, - sakari.ailus@linux.intel.com, - Laurent Pinchart -Cc: tfiga@chromium.org, posciak@chromium.org, - Paul Kocialkowski , - Chen-Yu Tsai , linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, - nicolas.dufresne@collabora.com, jenskuske@gmail.com, - jernej.skrabec@gmail.com, jonas@kwiboo.se, ezequiel@collabora.com, - linux-sunxi@googlegroups.com, - Thomas Petazzoni , - Maxime Ripard , - Jernej Skrabec -Date: Thu, 4 Apr 2019 14:59:03 +0200 - -Introduce some basic H264 decoding support in cedrus. So far, only the -baseline profile videos have been tested, and some more advanced features -used in higher profiles are not even implemented. - -Reviewed-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - drivers/staging/media/sunxi/cedrus/Makefile | 3 +- - drivers/staging/media/sunxi/cedrus/cedrus.c | 31 +- - drivers/staging/media/sunxi/cedrus/cedrus.h | 38 +- - drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 13 +- - drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 574 +++++++++++++++- - drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 4 +- - drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 91 ++- - drivers/staging/media/sunxi/cedrus/cedrus_video.c | 9 +- - 8 files changed, 761 insertions(+), 2 deletions(-) - create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h264.c - -diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile -index 808842f0119e..c85ac6db0302 100644 ---- a/drivers/staging/media/sunxi/cedrus/Makefile -+++ b/drivers/staging/media/sunxi/cedrus/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o - --sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o cedrus_mpeg2.o -+sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ -+ cedrus_mpeg2.o cedrus_h264.o -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index b98add3cdedd..d613f5c24a2f 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -40,6 +40,36 @@ static const struct cedrus_control cedrus_controls[] = { - .codec = CEDRUS_CODEC_MPEG2, - .required = false, - }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_decode_params), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_slice_params), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_sps), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_pps), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, - }; - - #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) -@@ -278,6 +308,7 @@ static int cedrus_probe(struct platform_device *pdev) - } - - dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; -+ dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; - - mutex_init(&dev->dev_mutex); - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index c57c04b41d2e..bef79f630520 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -32,7 +32,7 @@ - - enum cedrus_codec { - CEDRUS_CODEC_MPEG2, -- -+ CEDRUS_CODEC_H264, - CEDRUS_CODEC_LAST, - }; - -@@ -42,6 +42,12 @@ enum cedrus_irq_status { - CEDRUS_IRQ_OK, - }; - -+enum cedrus_h264_pic_type { -+ CEDRUS_H264_PIC_TYPE_FRAME = 0, -+ CEDRUS_H264_PIC_TYPE_FIELD, -+ CEDRUS_H264_PIC_TYPE_MBAFF, -+}; -+ - struct cedrus_control { - u32 id; - u32 elem_size; -@@ -49,6 +55,14 @@ struct cedrus_control { - unsigned char required:1; - }; - -+struct cedrus_h264_run { -+ const struct v4l2_ctrl_h264_decode_params *decode_params; -+ const struct v4l2_ctrl_h264_pps *pps; -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; -+ const struct v4l2_ctrl_h264_slice_params *slice_params; -+ const struct v4l2_ctrl_h264_sps *sps; -+}; -+ - struct cedrus_mpeg2_run { - const struct v4l2_ctrl_mpeg2_slice_params *slice_params; - const struct v4l2_ctrl_mpeg2_quantization *quantization; -@@ -59,12 +73,20 @@ struct cedrus_run { - struct vb2_v4l2_buffer *dst; - - union { -+ struct cedrus_h264_run h264; - struct cedrus_mpeg2_run mpeg2; - }; - }; - - struct cedrus_buffer { - struct v4l2_m2m_buffer m2m_buf; -+ -+ union { -+ struct { -+ unsigned int position; -+ enum cedrus_h264_pic_type pic_type; -+ } h264; -+ } codec; - }; - - struct cedrus_ctx { -@@ -79,6 +101,19 @@ struct cedrus_ctx { - struct v4l2_ctrl **ctrls; - - struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME]; -+ -+ union { -+ struct { -+ void *mv_col_buf; -+ dma_addr_t mv_col_buf_dma; -+ ssize_t mv_col_buf_field_size; -+ ssize_t mv_col_buf_size; -+ void *pic_info_buf; -+ dma_addr_t pic_info_buf_dma; -+ void *neighbor_info_buf; -+ dma_addr_t neighbor_info_buf_dma; -+ } h264; -+ } codec; - }; - - struct cedrus_dec_ops { -@@ -121,6 +156,7 @@ struct cedrus_dev { - }; - - extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; -+extern struct cedrus_dec_ops cedrus_dec_ops_h264; - - static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) - { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index 4d6d602cdde6..bdad87eb9d79 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -46,6 +46,19 @@ void cedrus_device_run(void *priv) - V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); - break; - -+ case V4L2_PIX_FMT_H264_SLICE_RAW: -+ run.h264.decode_params = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); -+ run.h264.pps = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_PPS); -+ run.h264.scaling_matrix = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX); -+ run.h264.slice_params = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); -+ run.h264.sps = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SPS); -+ break; -+ - default: - break; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -new file mode 100644 -index 000000000000..2c98a3e46d2b ---- /dev/null -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -0,0 +1,574 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Cedrus VPU driver -+ * -+ * Copyright (c) 2013 Jens Kuske -+ * Copyright (c) 2018 Bootlin -+ */ -+ -+#include -+ -+#include -+ -+#include "cedrus.h" -+#include "cedrus_hw.h" -+#include "cedrus_regs.h" -+ -+enum cedrus_h264_sram_off { -+ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE = 0x000, -+ CEDRUS_SRAM_H264_FRAMEBUFFER_LIST = 0x100, -+ CEDRUS_SRAM_H264_REF_LIST_0 = 0x190, -+ CEDRUS_SRAM_H264_REF_LIST_1 = 0x199, -+ CEDRUS_SRAM_H264_SCALING_LIST_8x8_0 = 0x200, -+ CEDRUS_SRAM_H264_SCALING_LIST_8x8_1 = 0x210, -+ CEDRUS_SRAM_H264_SCALING_LIST_4x4 = 0x220, -+}; -+ -+struct cedrus_h264_sram_ref_pic { -+ __le32 top_field_order_cnt; -+ __le32 bottom_field_order_cnt; -+ __le32 frame_info; -+ __le32 luma_ptr; -+ __le32 chroma_ptr; -+ __le32 mv_col_top_ptr; -+ __le32 mv_col_bot_ptr; -+ __le32 reserved; -+} __packed; -+ -+#define CEDRUS_H264_FRAME_NUM 18 -+ -+#define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) -+#define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) -+ -+static void cedrus_h264_write_sram(struct cedrus_dev *dev, -+ enum cedrus_h264_sram_off off, -+ const void *data, size_t len) -+{ -+ const u32 *buffer = data; -+ size_t count = DIV_ROUND_UP(len, 4); -+ -+ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, off << 2); -+ -+ while (count--) -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, *buffer++); -+} -+ -+static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, -+ unsigned int position, -+ unsigned int field) -+{ -+ dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; -+ -+ /* Adjust for the position */ -+ addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; -+ -+ /* Adjust for the field */ -+ addr += field * ctx->codec.h264.mv_col_buf_field_size; -+ -+ return addr; -+} -+ -+static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, -+ struct cedrus_buffer *buf, -+ unsigned int top_field_order_cnt, -+ unsigned int bottom_field_order_cnt, -+ struct cedrus_h264_sram_ref_pic *pic) -+{ -+ struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; -+ unsigned int position = buf->codec.h264.position; -+ -+ pic->top_field_order_cnt = top_field_order_cnt; -+ pic->bottom_field_order_cnt = bottom_field_order_cnt; -+ pic->frame_info = buf->codec.h264.pic_type << 8; -+ -+ pic->luma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0); -+ pic->chroma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1); -+ pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 0); -+ pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 1); -+} -+ -+static void cedrus_write_frame_list(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ struct cedrus_h264_sram_ref_pic pic_list[CEDRUS_H264_FRAME_NUM]; -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; -+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; -+ struct cedrus_buffer *output_buf; -+ struct cedrus_dev *dev = ctx->dev; -+ unsigned long used_dpbs = 0; -+ unsigned int position; -+ unsigned int output = 0; -+ unsigned int i; -+ -+ memset(pic_list, 0, sizeof(pic_list)); -+ -+ for (i = 0; i < ARRAY_SIZE(decode->dpb); i++) { -+ const struct v4l2_h264_dpb_entry *dpb = &decode->dpb[i]; -+ struct cedrus_buffer *cedrus_buf; -+ int buf_idx; -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) -+ continue; -+ -+ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); -+ if (buf_idx < 0) -+ continue; -+ -+ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[buf_idx]); -+ position = cedrus_buf->codec.h264.position; -+ used_dpbs |= BIT(position); -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ continue; -+ -+ cedrus_fill_ref_pic(ctx, cedrus_buf, -+ dpb->top_field_order_cnt, -+ dpb->bottom_field_order_cnt, -+ &pic_list[position]); -+ -+ output = max(position, output); -+ } -+ -+ position = find_next_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM, -+ output); -+ if (position >= CEDRUS_H264_FRAME_NUM) -+ position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); -+ -+ output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); -+ output_buf->codec.h264.position = position; -+ -+ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; -+ else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_MBAFF; -+ else -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FRAME; -+ -+ cedrus_fill_ref_pic(ctx, output_buf, -+ decode->top_field_order_cnt, -+ decode->bottom_field_order_cnt, -+ &pic_list[position]); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_FRAMEBUFFER_LIST, -+ pic_list, sizeof(pic_list)); -+ -+ cedrus_write(dev, VE_H264_OUTPUT_FRAME_IDX, position); -+} -+ -+#define CEDRUS_MAX_REF_IDX 32 -+ -+static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, -+ struct cedrus_run *run, -+ const u8 *ref_list, u8 num_ref, -+ enum cedrus_h264_sram_off sram) -+{ -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; -+ struct cedrus_dev *dev = ctx->dev; -+ u8 sram_array[CEDRUS_MAX_REF_IDX]; -+ unsigned int i; -+ size_t size; -+ -+ memset(sram_array, 0, sizeof(sram_array)); -+ -+ for (i = 0; i < num_ref; i++) { -+ const struct v4l2_h264_dpb_entry *dpb; -+ const struct cedrus_buffer *cedrus_buf; -+ const struct vb2_v4l2_buffer *ref_buf; -+ unsigned int position; -+ int buf_idx; -+ u8 dpb_idx; -+ -+ dpb_idx = ref_list[i]; -+ dpb = &decode->dpb[dpb_idx]; -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ continue; -+ -+ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); -+ if (buf_idx < 0) -+ continue; -+ -+ ref_buf = to_vb2_v4l2_buffer(ctx->dst_bufs[buf_idx]); -+ cedrus_buf = vb2_v4l2_to_cedrus_buffer(ref_buf); -+ position = cedrus_buf->codec.h264.position; -+ -+ sram_array[i] |= position << 1; -+ if (ref_buf->field == V4L2_FIELD_BOTTOM) -+ sram_array[i] |= BIT(0); -+ } -+ -+ size = min_t(size_t, ALIGN(num_ref, 4), sizeof(sram_array)); -+ cedrus_h264_write_sram(dev, sram, &sram_array, size); -+} -+ -+static void cedrus_write_ref_list0(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ -+ _cedrus_write_ref_list(ctx, run, -+ slice->ref_pic_list0, -+ slice->num_ref_idx_l0_active_minus1 + 1, -+ CEDRUS_SRAM_H264_REF_LIST_0); -+} -+ -+static void cedrus_write_ref_list1(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ -+ _cedrus_write_ref_list(ctx, run, -+ slice->ref_pic_list1, -+ slice->num_ref_idx_l1_active_minus1 + 1, -+ CEDRUS_SRAM_H264_REF_LIST_1); -+} -+ -+static void cedrus_write_scaling_lists(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling = -+ run->h264.scaling_matrix; -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_0, -+ scaling->scaling_list_8x8[0], -+ sizeof(scaling->scaling_list_8x8[0])); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_1, -+ scaling->scaling_list_8x8[3], -+ sizeof(scaling->scaling_list_8x8[3])); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_4x4, -+ scaling->scaling_list_4x4, -+ sizeof(scaling->scaling_list_4x4)); -+} -+ -+static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = -+ run->h264.slice_params; -+ const struct v4l2_h264_pred_weight_table *pred_weight = -+ &slice->pred_weight_table; -+ struct cedrus_dev *dev = ctx->dev; -+ int i, j, k; -+ -+ cedrus_write(dev, VE_H264_SHS_WP, -+ ((pred_weight->chroma_log2_weight_denom & 0x7) << 4) | -+ ((pred_weight->luma_log2_weight_denom & 0x7) << 0)); -+ -+ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, -+ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE << 2); -+ -+ for (i = 0; i < ARRAY_SIZE(pred_weight->weight_factors); i++) { -+ const struct v4l2_h264_weight_factors *factors = -+ &pred_weight->weight_factors[i]; -+ -+ for (j = 0; j < ARRAY_SIZE(factors->luma_weight); j++) { -+ u32 val; -+ -+ val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | -+ (factors->luma_weight[j] & 0x1ff); -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); -+ } -+ -+ for (j = 0; j < ARRAY_SIZE(factors->chroma_weight); j++) { -+ for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { -+ u32 val; -+ -+ val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | -+ (factors->chroma_weight[j][k] & 0x1ff); -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); -+ } -+ } -+ } -+} -+ -+static void cedrus_set_params(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; -+ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; -+ struct vb2_buffer *src_buf = &run->src->vb2_buf; -+ struct cedrus_dev *dev = ctx->dev; -+ dma_addr_t src_buf_addr; -+ u32 offset = slice->header_bit_size; -+ u32 len = (slice->size * 8) - offset; -+ u32 reg; -+ -+ cedrus_write(dev, VE_H264_VLD_LEN, len); -+ cedrus_write(dev, VE_H264_VLD_OFFSET, offset); -+ -+ src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); -+ cedrus_write(dev, VE_H264_VLD_END, -+ src_buf_addr + vb2_get_plane_payload(src_buf, 0)); -+ cedrus_write(dev, VE_H264_VLD_ADDR, -+ VE_H264_VLD_ADDR_VAL(src_buf_addr) | -+ VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | -+ VE_H264_VLD_ADDR_LAST); -+ -+ /* -+ * FIXME: Since the bitstream parsing is done in software, and -+ * in userspace, this shouldn't be needed anymore. But it -+ * turns out that removing it breaks the decoding process, -+ * without any clear indication why. -+ */ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_INIT_SWDEC); -+ -+ if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_P || -+ slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || -+ (pps->weighted_bipred_idc == 1 && -+ slice->slice_type == V4L2_H264_SLICE_TYPE_B)) -+ cedrus_write_pred_weight_table(ctx, run); -+ -+ if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_SP) || -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_B)) -+ cedrus_write_ref_list0(ctx, run); -+ -+ if (slice->slice_type == V4L2_H264_SLICE_TYPE_B) -+ cedrus_write_ref_list1(ctx, run); -+ -+ // picture parameters -+ reg = 0; -+ /* -+ * FIXME: the kernel headers are allowing the default value to -+ * be passed, but the libva doesn't give us that. -+ */ -+ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; -+ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; -+ reg |= (pps->weighted_bipred_idc & 0x3) << 2; -+ if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) -+ reg |= VE_H264_PPS_ENTROPY_CODING_MODE; -+ if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) -+ reg |= VE_H264_PPS_WEIGHTED_PRED; -+ if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) -+ reg |= VE_H264_PPS_CONSTRAINED_INTRA_PRED; -+ if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) -+ reg |= VE_H264_PPS_TRANSFORM_8X8_MODE; -+ cedrus_write(dev, VE_H264_PPS, reg); -+ -+ // sequence parameters -+ reg = 0; -+ reg |= (sps->chroma_format_idc & 0x7) << 19; -+ reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; -+ reg |= sps->pic_height_in_map_units_minus1 & 0xff; -+ if (sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) -+ reg |= VE_H264_SPS_MBS_ONLY; -+ if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) -+ reg |= VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD; -+ if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) -+ reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; -+ cedrus_write(dev, VE_H264_SPS, reg); -+ -+ // slice parameters -+ reg = 0; -+ reg |= decode->nal_ref_idc ? BIT(12) : 0; -+ reg |= (slice->slice_type & 0xf) << 8; -+ reg |= slice->cabac_init_idc & 0x3; -+ reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) -+ reg |= VE_H264_SHS_FIELD_PIC; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) -+ reg |= VE_H264_SHS_BOTTOM_FIELD; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED) -+ reg |= VE_H264_SHS_DIRECT_SPATIAL_MV_PRED; -+ cedrus_write(dev, VE_H264_SHS, reg); -+ -+ reg = 0; -+ reg |= VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD; -+ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 24; -+ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 16; -+ reg |= (slice->disable_deblocking_filter_idc & 0x3) << 8; -+ reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; -+ reg |= slice->slice_beta_offset_div2 & 0xf; -+ cedrus_write(dev, VE_H264_SHS2, reg); -+ -+ reg = 0; -+ reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; -+ reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; -+ reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; -+ cedrus_write(dev, VE_H264_SHS_QP, reg); -+ -+ // clear status flags -+ cedrus_write(dev, VE_H264_STATUS, cedrus_read(dev, VE_H264_STATUS)); -+ -+ // enable int -+ cedrus_write(dev, VE_H264_CTRL, -+ VE_H264_CTRL_SLICE_DECODE_INT | -+ VE_H264_CTRL_DECODE_ERR_INT | -+ VE_H264_CTRL_VLD_DATA_REQ_INT); -+} -+ -+static enum cedrus_irq_status -+cedrus_h264_irq_status(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_H264_STATUS); -+ -+ if (reg & (VE_H264_STATUS_DECODE_ERR_INT | -+ VE_H264_STATUS_VLD_DATA_REQ_INT)) -+ return CEDRUS_IRQ_ERROR; -+ -+ if (reg & VE_H264_CTRL_SLICE_DECODE_INT) -+ return CEDRUS_IRQ_OK; -+ -+ return CEDRUS_IRQ_NONE; -+} -+ -+static void cedrus_h264_irq_clear(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_H264_STATUS, -+ VE_H264_STATUS_INT_MASK); -+} -+ -+static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_H264_CTRL); -+ -+ cedrus_write(dev, VE_H264_CTRL, -+ reg & ~VE_H264_CTRL_INT_MASK); -+} -+ -+static void cedrus_h264_setup(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_engine_enable(dev, CEDRUS_CODEC_H264); -+ -+ cedrus_write(dev, VE_H264_SDROT_CTRL, 0); -+ cedrus_write(dev, VE_H264_EXTRA_BUFFER1, -+ ctx->codec.h264.pic_info_buf_dma); -+ cedrus_write(dev, VE_H264_EXTRA_BUFFER2, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ -+ cedrus_write_scaling_lists(ctx, run); -+ cedrus_write_frame_list(ctx, run); -+ -+ cedrus_set_params(ctx, run); -+} -+ -+static int cedrus_h264_start(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ unsigned int field_size; -+ unsigned int mv_col_size; -+ int ret; -+ -+ /* -+ * FIXME: It seems that the H6 cedarX code is using a formula -+ * here based on the size of the frame, while all the older -+ * code is using a fixed size, so that might need to be -+ * changed at some point. -+ */ -+ ctx->codec.h264.pic_info_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ &ctx->codec.h264.pic_info_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.pic_info_buf) -+ return -ENOMEM; -+ -+ /* -+ * That buffer is supposed to be 16kiB in size, and be aligned -+ * on 16kiB as well. However, dma_alloc_coherent provides the -+ * guarantee that we'll have a CPU and DMA address aligned on -+ * the smallest page order that is greater to the requested -+ * size, so we don't have to overallocate. -+ */ -+ ctx->codec.h264.neighbor_info_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ &ctx->codec.h264.neighbor_info_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.neighbor_info_buf) { -+ ret = -ENOMEM; -+ goto err_pic_buf; -+ } -+ -+ field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * -+ DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; -+ -+ /* -+ * FIXME: This is actually conditional to -+ * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we -+ * might have to rework this if memory efficiency ever is -+ * something we need to work on. -+ */ -+ field_size = field_size * 2; -+ -+ /* -+ * FIXME: This is actually conditional to -+ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might -+ * have to rework this if memory efficiency ever is something -+ * we need to work on. -+ */ -+ field_size = field_size * 2; -+ ctx->codec.h264.mv_col_buf_field_size = field_size; -+ -+ mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; -+ ctx->codec.h264.mv_col_buf_size = mv_col_size; -+ ctx->codec.h264.mv_col_buf = dma_alloc_coherent(dev->dev, -+ ctx->codec.h264.mv_col_buf_size, -+ &ctx->codec.h264.mv_col_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.mv_col_buf) { -+ ret = -ENOMEM; -+ goto err_neighbor_buf; -+ } -+ -+ return 0; -+ -+err_neighbor_buf: -+ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ ctx->codec.h264.neighbor_info_buf, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ -+err_pic_buf: -+ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ ctx->codec.h264.pic_info_buf, -+ ctx->codec.h264.pic_info_buf_dma); -+ return ret; -+} -+ -+static void cedrus_h264_stop(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, -+ ctx->codec.h264.mv_col_buf, -+ ctx->codec.h264.mv_col_buf_dma); -+ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ ctx->codec.h264.neighbor_info_buf, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ ctx->codec.h264.pic_info_buf, -+ ctx->codec.h264.pic_info_buf_dma); -+} -+ -+static void cedrus_h264_trigger(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE); -+} -+ -+struct cedrus_dec_ops cedrus_dec_ops_h264 = { -+ .irq_clear = cedrus_h264_irq_clear, -+ .irq_disable = cedrus_h264_irq_disable, -+ .irq_status = cedrus_h264_irq_status, -+ .setup = cedrus_h264_setup, -+ .start = cedrus_h264_start, -+ .stop = cedrus_h264_stop, -+ .trigger = cedrus_h264_trigger, -+}; -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index fbfff7c1c771..748f7f673547 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -46,6 +46,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) - reg |= VE_MODE_DEC_MPEG; - break; - -+ case CEDRUS_CODEC_H264: -+ reg |= VE_MODE_DEC_H264; -+ break; -+ - default: - return -EINVAL; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index de2d6b6f64bf..3e9931416e45 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -232,4 +232,95 @@ - #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) - #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) - -+#define VE_H264_SPS 0x200 -+#define VE_H264_SPS_MBS_ONLY BIT(18) -+#define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) -+#define VE_H264_SPS_DIRECT_8X8_INFERENCE BIT(16) -+ -+#define VE_H264_PPS 0x204 -+#define VE_H264_PPS_ENTROPY_CODING_MODE BIT(15) -+#define VE_H264_PPS_WEIGHTED_PRED BIT(4) -+#define VE_H264_PPS_CONSTRAINED_INTRA_PRED BIT(1) -+#define VE_H264_PPS_TRANSFORM_8X8_MODE BIT(0) -+ -+#define VE_H264_SHS 0x208 -+#define VE_H264_SHS_FIRST_SLICE_IN_PIC BIT(5) -+#define VE_H264_SHS_FIELD_PIC BIT(4) -+#define VE_H264_SHS_BOTTOM_FIELD BIT(3) -+#define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED BIT(2) -+ -+#define VE_H264_SHS2 0x20c -+#define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD BIT(12) -+ -+#define VE_H264_SHS_WP 0x210 -+ -+#define VE_H264_SHS_QP 0x21c -+#define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) -+ -+#define VE_H264_CTRL 0x220 -+#define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) -+#define VE_H264_CTRL_DECODE_ERR_INT BIT(1) -+#define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) -+ -+#define VE_H264_CTRL_INT_MASK (VE_H264_CTRL_VLD_DATA_REQ_INT | \ -+ VE_H264_CTRL_DECODE_ERR_INT | \ -+ VE_H264_CTRL_SLICE_DECODE_INT) -+ -+#define VE_H264_TRIGGER_TYPE 0x224 -+#define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) -+#define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) -+ -+#define VE_H264_STATUS 0x228 -+#define VE_H264_STATUS_VLD_DATA_REQ_INT VE_H264_CTRL_VLD_DATA_REQ_INT -+#define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT -+#define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT -+ -+#define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK -+ -+#define VE_H264_CUR_MB_NUM 0x22c -+ -+#define VE_H264_VLD_ADDR 0x230 -+#define VE_H264_VLD_ADDR_FIRST BIT(30) -+#define VE_H264_VLD_ADDR_LAST BIT(29) -+#define VE_H264_VLD_ADDR_VALID BIT(28) -+#define VE_H264_VLD_ADDR_VAL(x) (((x) & 0x0ffffff0) | ((x) >> 28)) -+ -+#define VE_H264_VLD_OFFSET 0x234 -+#define VE_H264_VLD_LEN 0x238 -+#define VE_H264_VLD_END 0x23c -+#define VE_H264_SDROT_CTRL 0x240 -+#define VE_H264_OUTPUT_FRAME_IDX 0x24c -+#define VE_H264_EXTRA_BUFFER1 0x250 -+#define VE_H264_EXTRA_BUFFER2 0x254 -+#define VE_H264_BASIC_BITS 0x2dc -+#define VE_AVC_SRAM_PORT_OFFSET 0x2e0 -+#define VE_AVC_SRAM_PORT_DATA 0x2e4 -+ -+#define VE_ISP_INPUT_SIZE 0xa00 -+#define VE_ISP_INPUT_STRIDE 0xa04 -+#define VE_ISP_CTRL 0xa08 -+#define VE_ISP_INPUT_LUMA 0xa78 -+#define VE_ISP_INPUT_CHROMA 0xa7c -+ -+#define VE_AVC_PARAM 0xb04 -+#define VE_AVC_QP 0xb08 -+#define VE_AVC_MOTION_EST 0xb10 -+#define VE_AVC_CTRL 0xb14 -+#define VE_AVC_TRIGGER 0xb18 -+#define VE_AVC_STATUS 0xb1c -+#define VE_AVC_BASIC_BITS 0xb20 -+#define VE_AVC_UNK_BUF 0xb60 -+#define VE_AVC_VLE_ADDR 0xb80 -+#define VE_AVC_VLE_END 0xb84 -+#define VE_AVC_VLE_OFFSET 0xb88 -+#define VE_AVC_VLE_MAX 0xb8c -+#define VE_AVC_VLE_LENGTH 0xb90 -+#define VE_AVC_REF_LUMA 0xba0 -+#define VE_AVC_REF_CHROMA 0xba4 -+#define VE_AVC_REC_LUMA 0xbb0 -+#define VE_AVC_REC_CHROMA 0xbb4 -+#define VE_AVC_REF_SLUMA 0xbb8 -+#define VE_AVC_REC_SLUMA 0xbbc -+#define VE_AVC_MB_INFO 0xbc0 -+ - #endif -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index 9673874ece10..e2b530b1a956 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -38,6 +38,10 @@ static struct cedrus_format cedrus_formats[] = { - .directions = CEDRUS_DECODE_SRC, - }, - { -+ .pixelformat = V4L2_PIX_FMT_H264_SLICE_RAW, -+ .directions = CEDRUS_DECODE_SRC, -+ }, -+ { - .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, - .directions = CEDRUS_DECODE_DST, - }, -@@ -100,6 +104,7 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) - - switch (pix_fmt->pixelformat) { - case V4L2_PIX_FMT_MPEG2_SLICE: -+ case V4L2_PIX_FMT_H264_SLICE_RAW: - /* Zero bytes per line for encoded source. */ - bytesperline = 0; - -@@ -464,6 +469,10 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) - ctx->current_codec = CEDRUS_CODEC_MPEG2; - break; - -+ case V4L2_PIX_FMT_H264_SLICE_RAW: -+ ctx->current_codec = CEDRUS_CODEC_H264; -+ break; -+ - default: - return -EINVAL; - } diff --git a/projects/Allwinner/patches/linux/0013-cec-improvements.patch b/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch similarity index 65% rename from projects/Allwinner/patches/linux/0013-cec-improvements.patch rename to projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch index f9360ec979..fc1b07d068 100644 --- a/projects/Allwinner/patches/linux/0013-cec-improvements.patch +++ b/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch @@ -1,8 +1,85 @@ +From bf21ad0889bdcc1dc12fe5a024fd7df7ad2c4310 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 26 Feb 2019 20:45:14 +0000 +Subject: [PATCH 1/2] WIP: dw-hdmi-cec: sleep 100ms on error + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +index 6c323510f128..b5a1a85c8700 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +@@ -7,6 +7,7 @@ + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ ++#include + #include + #include + #include +@@ -132,8 +133,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + + dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); + +- if (stat & CEC_STAT_ERROR_INIT) { +- cec->tx_status = CEC_TX_STATUS_ERROR; ++ /* Status with both done and error_initiator bits have been seen ++ * on Rockchip RK3328 devices, transmit attempt seems to have failed ++ * when this happens, report as low drive and block cec-framework ++ * 100ms before core retransmits the failed message, this seems to ++ * mitigate the issue with failed transmit attempts. ++ */ ++ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { ++ pr_info("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); ++ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_DONE) { +@@ -144,6 +152,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + cec->tx_status = CEC_TX_STATUS_NACK; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; ++ } else if (stat & CEC_STAT_ERROR_INIT) { ++ cec->tx_status = CEC_TX_STATUS_ERROR; ++ cec->tx_done = true; ++ ret = IRQ_WAKE_THREAD; + } + + if (stat & CEC_STAT_EOM) { +@@ -176,6 +188,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data) + + if (cec->tx_done) { + cec->tx_done = false; ++ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) ++ msleep(100); + cec_transmit_attempt_done(adap, cec->tx_status); + } + if (cec->rx_done) { +-- +2.21.0 + + +From 12f1abe2b5cee6575c6dd9cd29b17b589f044b80 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 25 May 2019 12:03:39 +0200 +Subject: [PATCH 2/2] WIP: sun8i-hdmi CEC improvements + +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- + drivers/gpu/drm/sun4i/Kconfig | 10 +++ + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 11 +++ + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 83 ++++++++++++++++++++++- + include/drm/bridge/dw_hdmi.h | 2 + + 5 files changed, 105 insertions(+), 3 deletions(-) + diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index a63e5f0dae56..fdda26f8b056 100644 +index 09fdc9f87651..f359c4c3f1d1 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2634,7 +2634,7 @@ __dw_hdmi_probe(struct platform_device *pdev, +@@ -2713,7 +2713,7 @@ __dw_hdmi_probe(struct platform_device *pdev, hdmi->audio = platform_device_register_full(&pdevinfo); } @@ -33,7 +110,7 @@ index 1dbbc3a1b763..7149c72e44c8 100644 tristate "Support for Allwinner Display Engine 2.0 Mixer" default MACH_SUN8I diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -index 720c5aa8adc1..82dd84094638 100644 +index 720c5aa8adc1..49ca001923e3 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h @@ -12,6 +12,7 @@ @@ -71,15 +148,15 @@ index 720c5aa8adc1..82dd84094638 100644 struct sun8i_hdmi_phy { + struct cec_adapter *cec_adapter; -+ struct cec_notifier *cec_notifier; ++ struct cec_notifier *cec_notifier; struct clk *clk_bus; struct clk *clk_mod; struct clk *clk_phy; diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -index 66ea3a902e36..70e291353569 100644 +index 43643ad31730..d840bc07cba6 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -503,8 +503,9 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) +@@ -504,8 +504,9 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0); @@ -91,7 +168,7 @@ index 66ea3a902e36..70e291353569 100644 /* read calibration data */ regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); -@@ -530,8 +531,49 @@ void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, +@@ -531,8 +532,49 @@ void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, plat_data->cur_ctr = variant->cur_ctr; plat_data->phy_config = variant->phy_cfg; } @@ -141,7 +218,7 @@ index 66ea3a902e36..70e291353569 100644 static struct regmap_config sun8i_hdmi_phy_regmap_config = { .reg_bits = 32, .val_bits = 32, -@@ -548,6 +590,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = { +@@ -549,6 +591,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = { }; static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { @@ -149,7 +226,7 @@ index 66ea3a902e36..70e291353569 100644 .has_phy_clk = true, .is_custom_phy = true, .phy_init = &sun8i_hdmi_phy_init_h3, -@@ -556,6 +599,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { +@@ -557,6 +600,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { }; static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { @@ -157,7 +234,7 @@ index 66ea3a902e36..70e291353569 100644 .has_phy_clk = true, .has_second_pll = true, .is_custom_phy = true, -@@ -565,6 +609,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { +@@ -566,6 +610,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { }; static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { @@ -165,7 +242,7 @@ index 66ea3a902e36..70e291353569 100644 .has_phy_clk = true, .is_custom_phy = true, .phy_init = &sun8i_hdmi_phy_init_h3, -@@ -708,10 +753,40 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) +@@ -711,10 +756,40 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) clk_prepare_enable(phy->clk_phy); } @@ -204,9 +281,9 @@ index 66ea3a902e36..70e291353569 100644 +err_disable_clk_phy: + clk_disable_unprepare(phy->clk_phy); err_disable_clk_mod: - clk_disable_unprepare(phy->clk_mod); + clk_disable_unprepare(phy->clk_mod); err_disable_clk_bus: -@@ -736,6 +811,10 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) +@@ -739,6 +814,10 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) { struct sun8i_hdmi_phy *phy = hdmi->phy; @@ -218,7 +295,7 @@ index 66ea3a902e36..70e291353569 100644 clk_disable_unprepare(phy->clk_bus); clk_disable_unprepare(phy->clk_phy); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 66e70770cce5..764b8bcfa62c 100644 +index 323febe7f102..cec73761856d 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -144,6 +144,8 @@ struct dw_hdmi_plat_data { @@ -230,3 +307,6 @@ index 66e70770cce5..764b8bcfa62c 100644 }; struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0007-media-cedrus-Fix-decoding-for-some-H264-videos.patch b/projects/Allwinner/patches/linux/0007-media-cedrus-Fix-decoding-for-some-H264-videos.patch new file mode 100644 index 0000000000..f8ba373631 --- /dev/null +++ b/projects/Allwinner/patches/linux/0007-media-cedrus-Fix-decoding-for-some-H264-videos.patch @@ -0,0 +1,76 @@ +From 443ca53cf78c635aa5bebe9f115721e55fe9ca38 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 25 May 2019 12:33:05 +0200 +Subject: [PATCH] media: cedrus: Fix decoding for some H264 videos + +It seems that for some H264 videos at least one bitstream parsing +trigger must be called in order to be decoded correctly. There is no +explanation why this helps, but it was observed that two sample videos +with this fix are now decoded correctly and there is no regression with +others. + +Signed-off-by: Jernej Skrabec +--- + .../staging/media/sunxi/cedrus/cedrus_h264.c | 22 ++++++++++++++++--- + 1 file changed, 19 insertions(+), 3 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +index a30bb283f69f..fab14de1815a 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -6,6 +6,7 @@ + * Copyright (c) 2018 Bootlin + */ + ++#include + #include + + #include +@@ -289,6 +290,20 @@ static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, + } + } + ++static void cedrus_skip_bits(struct cedrus_dev *dev, int num) ++{ ++ for (; num > 32; num -= 32) { ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, 0x3 | (32 << 8)); ++ while (cedrus_read(dev, VE_H264_STATUS) & (1 << 8)) ++ udelay(1); ++ } ++ if (num > 0) { ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, 0x3 | (num << 8)); ++ while (cedrus_read(dev, VE_H264_STATUS) & (1 << 8)) ++ udelay(1); ++ } ++} ++ + static void cedrus_set_params(struct cedrus_ctx *ctx, + struct cedrus_run *run) + { +@@ -299,12 +314,11 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + struct vb2_buffer *src_buf = &run->src->vb2_buf; + struct cedrus_dev *dev = ctx->dev; + dma_addr_t src_buf_addr; +- u32 offset = slice->header_bit_size; +- u32 len = (slice->size * 8) - offset; ++ u32 len = slice->size * 8; + u32 reg; + + cedrus_write(dev, VE_H264_VLD_LEN, len); +- cedrus_write(dev, VE_H264_VLD_OFFSET, offset); ++ cedrus_write(dev, VE_H264_VLD_OFFSET, 0); + + src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); + cedrus_write(dev, VE_H264_VLD_END, +@@ -323,6 +337,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + cedrus_write(dev, VE_H264_TRIGGER_TYPE, + VE_H264_TRIGGER_TYPE_INIT_SWDEC); + ++ cedrus_skip_bits(dev, slice->header_bit_size); ++ + if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && + (slice->slice_type == V4L2_H264_SLICE_TYPE_P || + slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0008-media-cedrus-Fix-H264-default-reference-index-count.patch b/projects/Allwinner/patches/linux/0008-media-cedrus-Fix-H264-default-reference-index-count.patch new file mode 100644 index 0000000000..6b08bad539 --- /dev/null +++ b/projects/Allwinner/patches/linux/0008-media-cedrus-Fix-H264-default-reference-index-count.patch @@ -0,0 +1,36 @@ +From fce7f7e700176b402b303d2a62813cc0cdd061e0 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 25 May 2019 13:18:50 +0200 +Subject: [PATCH 2/5] media: cedrus: Fix H264 default reference index count + +Reference index count in VE_H264_PPS should come from PPS control. +However, this is not really important, because reference index count is +in our case always overridden by that from slice header. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +index fab14de1815a..d0ee3f90ff46 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -356,12 +356,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + + // picture parameters + reg = 0; +- /* +- * FIXME: the kernel headers are allowing the default value to +- * be passed, but the libva doesn't give us that. +- */ +- reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; +- reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; ++ reg |= (pps->num_ref_idx_l0_default_active_minus1 & 0x1f) << 10; ++ reg |= (pps->num_ref_idx_l1_default_active_minus1 & 0x1f) << 5; + reg |= (pps->weighted_bipred_idc & 0x3) << 2; + if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) + reg |= VE_H264_PPS_ENTROPY_CODING_MODE; +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0007-H264-improvements.patch b/projects/Allwinner/patches/linux/0009-media-cedrus-WIP-H264-improvements.patch similarity index 72% rename from projects/Allwinner/patches/linux/0007-H264-improvements.patch rename to projects/Allwinner/patches/linux/0009-media-cedrus-WIP-H264-improvements.patch index 0efa61a7fc..3abe59c038 100644 --- a/projects/Allwinner/patches/linux/0007-H264-improvements.patch +++ b/projects/Allwinner/patches/linux/0009-media-cedrus-WIP-H264-improvements.patch @@ -1,18 +1,18 @@ -From e41186f41a546d1c60797f090001da969f5eda5a Mon Sep 17 00:00:00 2001 +From 9714cf1bc8c5b48f21af3500e34497621b51a4b1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 14 Feb 2019 22:50:12 +0100 -Subject: [PATCH] cedrus: Improve H264 +Subject: [PATCH 3/5] media: cedrus: WIP H264 improvements Signed-off-by: Jernej Skrabec --- - .../staging/media/sunxi/cedrus/cedrus_h264.c | 69 +++++++++++-------- - 1 file changed, 41 insertions(+), 28 deletions(-) + .../staging/media/sunxi/cedrus/cedrus_h264.c | 37 ++++++++++++++----- + 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index a5c5f13ffecb..405545947b85 100644 +index d0ee3f90ff46..dcb8d3837869 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -38,7 +38,7 @@ struct cedrus_h264_sram_ref_pic { +@@ -39,7 +39,7 @@ struct cedrus_h264_sram_ref_pic { #define CEDRUS_H264_FRAME_NUM 18 #define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) @@ -21,7 +21,7 @@ index a5c5f13ffecb..405545947b85 100644 static void cedrus_h264_write_sram(struct cedrus_dev *dev, enum cedrus_h264_sram_off off, -@@ -101,7 +101,7 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -102,7 +102,7 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, struct cedrus_dev *dev = ctx->dev; unsigned long used_dpbs = 0; unsigned int position; @@ -30,7 +30,7 @@ index a5c5f13ffecb..405545947b85 100644 unsigned int i; memset(pic_list, 0, sizeof(pic_list)); -@@ -126,6 +126,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -123,6 +123,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, position = cedrus_buf->codec.h264.position; used_dpbs |= BIT(position); @@ -42,7 +42,7 @@ index a5c5f13ffecb..405545947b85 100644 if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) continue; -@@ -133,13 +138,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -130,13 +135,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, dpb->top_field_order_cnt, dpb->bottom_field_order_cnt, &pic_list[position]); @@ -59,7 +59,7 @@ index a5c5f13ffecb..405545947b85 100644 position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); -@@ -165,6 +168,10 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -162,6 +165,10 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, #define CEDRUS_MAX_REF_IDX 32 @@ -70,7 +70,7 @@ index a5c5f13ffecb..405545947b85 100644 static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, struct cedrus_run *run, const u8 *ref_list, u8 num_ref, -@@ -187,7 +194,7 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, +@@ -184,7 +191,7 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, int buf_idx; u8 dpb_idx; @@ -79,7 +79,7 @@ index a5c5f13ffecb..405545947b85 100644 dpb = &decode->dpb[dpb_idx]; if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -@@ -206,7 +213,8 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, +@@ -199,7 +206,8 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, position = cedrus_buf->codec.h264.position; sram_array[i] |= position << 1; @@ -89,16 +89,16 @@ index a5c5f13ffecb..405545947b85 100644 sram_array[i] |= BIT(0); } -@@ -309,6 +317,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, +@@ -315,6 +323,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + struct cedrus_dev *dev = ctx->dev; dma_addr_t src_buf_addr; - u32 offset = slice->header_bit_size; - u32 len = (slice->size * 8) - offset; + u32 len = slice->size * 8; + unsigned int pic_width_in_mbs; + bool mbaff_picture; u32 reg; cedrus_write(dev, VE_H264_VLD_LEN, len); -@@ -378,12 +387,19 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, +@@ -382,12 +392,19 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; cedrus_write(dev, VE_H264_SPS, reg); @@ -119,15 +119,6 @@ index a5c5f13ffecb..405545947b85 100644 if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) reg |= VE_H264_SHS_FIELD_PIC; if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) -@@ -531,7 +541,7 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) - * we need to work on. - */ - field_size = field_size * 2; -- ctx->codec.h264.mv_col_buf_field_size = field_size; -+ ctx->codec.h264.mv_col_buf_field_size = ALIGN(field_size, 1024); - - mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; - ctx->codec.h264.mv_col_buf_size = mv_col_size; -- -2.20.1 +2.21.0 diff --git a/projects/Allwinner/patches/linux/0008-HEVC-improvements.patch b/projects/Allwinner/patches/linux/0010-WIP-HEVC-improvements.patch similarity index 84% rename from projects/Allwinner/patches/linux/0008-HEVC-improvements.patch rename to projects/Allwinner/patches/linux/0010-WIP-HEVC-improvements.patch index 38c5f5f04c..96c0a6da59 100644 --- a/projects/Allwinner/patches/linux/0008-HEVC-improvements.patch +++ b/projects/Allwinner/patches/linux/0010-WIP-HEVC-improvements.patch @@ -1,8 +1,25 @@ +From c6582c38df2f78dc9d4f8fd920780a82a01e4d8e Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 25 May 2019 13:58:17 +0200 +Subject: [PATCH 2/3] WIP: HEVC improvements + +Signed-off-by: Jernej Skrabec +--- + drivers/media/v4l2-core/v4l2-ctrls.c | 8 + + drivers/staging/media/sunxi/cedrus/cedrus.c | 6 + + drivers/staging/media/sunxi/cedrus/cedrus.h | 11 +- + .../staging/media/sunxi/cedrus/cedrus_dec.c | 2 + + .../staging/media/sunxi/cedrus/cedrus_h265.c | 348 +++++++++++++----- + .../staging/media/sunxi/cedrus/cedrus_regs.h | 3 + + .../staging/media/sunxi/cedrus/cedrus_video.c | 12 +- + include/media/hevc-ctrls.h | 20 +- + 8 files changed, 301 insertions(+), 109 deletions(-) + diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 3bab9d4e3304..a14762dff91d 100644 +index 1107698b9d06..aed7a4526193 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -916,6 +916,7 @@ const char *v4l2_ctrl_get_name(u32 id) +@@ -947,6 +947,7 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; @@ -10,7 +27,7 @@ index 3bab9d4e3304..a14762dff91d 100644 /* CAMERA controls */ /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1332,6 +1333,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, +@@ -1368,6 +1369,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; break; @@ -20,7 +37,7 @@ index 3bab9d4e3304..a14762dff91d 100644 default: *type = V4L2_CTRL_TYPE_INTEGER; break; -@@ -1708,6 +1712,7 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, +@@ -1747,6 +1751,7 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, case V4L2_CTRL_TYPE_HEVC_SPS: case V4L2_CTRL_TYPE_HEVC_PPS: case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: @@ -28,7 +45,7 @@ index 3bab9d4e3304..a14762dff91d 100644 return 0; default: -@@ -2314,6 +2319,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, +@@ -2356,6 +2361,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); break; @@ -39,10 +56,10 @@ index 3bab9d4e3304..a14762dff91d 100644 if (type < V4L2_CTRL_COMPOUND_TYPES) elem_size = sizeof(s32); diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index a713630ce7ba..3040f483e0a2 100644 +index 70642834f351..01860f247aa6 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -87,6 +87,12 @@ static const struct cedrus_control cedrus_controls[] = { +@@ -88,6 +88,12 @@ static const struct cedrus_control cedrus_controls[] = { .codec = CEDRUS_CODEC_H265, .required = true, }, @@ -56,10 +73,10 @@ index a713630ce7ba..3040f483e0a2 100644 #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index b5d083812bea..deb9fa1de97c 100644 +index f19be772d78b..b518c5613fdf 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -72,6 +72,7 @@ struct cedrus_h265_run { +@@ -74,6 +74,7 @@ struct cedrus_h265_run { const struct v4l2_ctrl_hevc_sps *sps; const struct v4l2_ctrl_hevc_pps *pps; const struct v4l2_ctrl_hevc_slice_params *slice_params; @@ -67,7 +84,7 @@ index b5d083812bea..deb9fa1de97c 100644 }; struct cedrus_run { -@@ -88,6 +89,10 @@ struct cedrus_run { +@@ -90,6 +91,10 @@ struct cedrus_run { struct cedrus_buffer { struct v4l2_m2m_buffer m2m_buf; @@ -78,7 +95,7 @@ index b5d083812bea..deb9fa1de97c 100644 union { struct { unsigned int position; -@@ -121,12 +126,10 @@ struct cedrus_ctx { +@@ -123,12 +128,10 @@ struct cedrus_ctx { dma_addr_t neighbor_info_buf_dma; } h264; struct { @@ -94,10 +111,10 @@ index b5d083812bea..deb9fa1de97c 100644 } codec; }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index c50397f8692f..80c6d920142d 100644 +index c6d0ef66cdd0..104adb08492c 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -68,6 +68,8 @@ void cedrus_device_run(void *priv) +@@ -66,6 +66,8 @@ void cedrus_device_run(void *priv) V4L2_CID_MPEG_VIDEO_HEVC_PPS); run.h265.slice_params = cedrus_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); @@ -107,7 +124,7 @@ index c50397f8692f..80c6d920142d 100644 default: diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -index f1c3665e95ab..2cc36d69548e 100644 +index fd4d86b02156..82d29c59b787 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -77,24 +77,25 @@ static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset) @@ -157,7 +174,7 @@ index f1c3665e95ab..2cc36d69548e 100644 }; u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; -@@ -157,28 +157,24 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev, +@@ -158,28 +158,24 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev, u8 num_ref_idx_active, u32 sram_offset) { @@ -195,7 +212,7 @@ index f1c3665e95ab..2cc36d69548e 100644 } static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, -@@ -219,6 +215,105 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, +@@ -220,6 +216,131 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, } } @@ -204,6 +221,7 @@ index f1c3665e95ab..2cc36d69548e 100644 +{ + const struct v4l2_ctrl_hevc_scaling_matrix *scaling; + struct cedrus_dev *dev = ctx->dev; ++ u32 i, j, k, val; + + scaling = run->h265.scaling_matrix; + @@ -219,21 +237,46 @@ index f1c3665e95ab..2cc36d69548e 100644 + (scaling->scaling_list_dc_coef_16x16[3] << 8) | + (scaling->scaling_list_dc_coef_16x16[2] << 0)); + -+ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_8x8); -+ cedrus_h265_sram_write_data(dev, scaling->scaling_list_8x8, -+ sizeof(scaling->scaling_list_8x8)); ++ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS); + -+ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_32x32); -+ cedrus_h265_sram_write_data(dev, scaling->scaling_list_32x32, -+ sizeof(scaling->scaling_list_32x32)); ++ for (i = 0; i < 6; i++) ++ for (j = 0; j < 8; j++) ++ for (k = 0; k < 8; k += 4) { ++ val = ((u32)scaling->scaling_list_8x8[i][j + (k + 3) * 8] << 24) | ++ ((u32)scaling->scaling_list_8x8[i][j + (k + 2) * 8] << 16) | ++ ((u32)scaling->scaling_list_8x8[i][j + (k + 1) * 8] << 8) | ++ scaling->scaling_list_8x8[i][j + k * 8]; ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val); ++ } + -+ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_16x16); -+ cedrus_h265_sram_write_data(dev, scaling->scaling_list_16x16, -+ sizeof(scaling->scaling_list_16x16)); ++ for (i = 0; i < 2; i++) ++ for (j = 0; j < 8; j++) ++ for (k = 0; k < 8; k += 4) { ++ val = ((u32)scaling->scaling_list_32x32[i][j + (k + 3) * 8] << 24) | ++ ((u32)scaling->scaling_list_32x32[i][j + (k + 2) * 8] << 16) | ++ ((u32)scaling->scaling_list_32x32[i][j + (k + 1) * 8] << 8) | ++ scaling->scaling_list_32x32[i][j + k * 8]; ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val); ++ } + -+ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_4x4); -+ cedrus_h265_sram_write_data(dev, scaling->scaling_list_4x4, -+ sizeof(scaling->scaling_list_4x4)); ++ for (i = 0; i < 6; i++) ++ for (j = 0; j < 8; j++) ++ for (k = 0; k < 8; k += 4) { ++ val = ((u32)scaling->scaling_list_16x16[i][j + (k + 3) * 8] << 24) | ++ ((u32)scaling->scaling_list_16x16[i][j + (k + 2) * 8] << 16) | ++ ((u32)scaling->scaling_list_16x16[i][j + (k + 1) * 8] << 8) | ++ scaling->scaling_list_16x16[i][j + k * 8]; ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val); ++ } ++ ++ for (i = 0; i < 6; i++) ++ for (j = 0; j < 4; j++) { ++ val = ((u32)scaling->scaling_list_4x4[i][j + 12] << 24) | ++ ((u32)scaling->scaling_list_4x4[i][j + 8] << 16) | ++ ((u32)scaling->scaling_list_4x4[i][j + 4] << 8) | ++ scaling->scaling_list_4x4[i][j]; ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val); ++ } +} + +static void write_entry_point_list(struct cedrus_ctx *ctx, @@ -301,7 +344,7 @@ index f1c3665e95ab..2cc36d69548e 100644 static void cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { -@@ -227,6 +322,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -228,6 +349,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, const struct v4l2_ctrl_hevc_pps *pps; const struct v4l2_ctrl_hevc_slice_params *slice_params; const struct v4l2_hevc_pred_weight_table *pred_weight_table; @@ -309,7 +352,7 @@ index f1c3665e95ab..2cc36d69548e 100644 dma_addr_t src_buf_addr; dma_addr_t src_buf_end_addr; u32 chroma_log2_weight_denom; -@@ -239,43 +335,10 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -240,43 +362,10 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, slice_params = run->h265.slice_params; pred_weight_table = &slice_params->pred_weight_table; @@ -355,7 +398,7 @@ index f1c3665e95ab..2cc36d69548e 100644 /* Source offset and length in bits. */ -@@ -299,18 +362,35 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -300,18 +389,35 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, src_buf_end_addr = src_buf_addr + DIV_ROUND_UP(slice_params->bit_size, 8); @@ -397,7 +440,7 @@ index f1c3665e95ab..2cc36d69548e 100644 /* Initialize bitstream access. */ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); -@@ -333,6 +413,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -334,6 +440,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) | VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) | VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) | @@ -405,7 +448,7 @@ index f1c3665e95ab..2cc36d69548e 100644 VE_DEC_H265_DEC_SPS_HDR_SEPARATE_COLOUR_PLANE_FLAG(sps->separate_colour_plane_flag) | VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc); -@@ -362,7 +443,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -363,7 +470,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, VE_DEC_H265_DEC_PPS_CTRL1_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG(pps->pps_loop_filter_across_slices_enabled_flag) | VE_DEC_H265_DEC_PPS_CTRL1_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG(pps->loop_filter_across_tiles_enabled_flag) | VE_DEC_H265_DEC_PPS_CTRL1_ENTROPY_CODING_SYNC_ENABLED_FLAG(pps->entropy_coding_sync_enabled_flag) | @@ -414,7 +457,7 @@ index f1c3665e95ab..2cc36d69548e 100644 VE_DEC_H265_DEC_PPS_CTRL1_TRANSQUANT_BYPASS_ENABLE_FLAG(pps->transquant_bypass_enabled_flag) | VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_BIPRED_FLAG(pps->weighted_bipred_flag) | VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_PRED_FLAG(pps->weighted_pred_flag); -@@ -383,7 +464,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -384,7 +491,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) | VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type) | VE_DEC_H265_DEC_SLICE_HDR_INFO0_DEPENDENT_SLICE_SEGMENT_FLAG(pps->dependent_slice_segment_flag) | @@ -423,7 +466,7 @@ index f1c3665e95ab..2cc36d69548e 100644 cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); -@@ -400,34 +481,68 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -401,34 +508,68 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + pred_weight_table->delta_chroma_log2_weight_denom; @@ -497,7 +540,7 @@ index f1c3665e95ab..2cc36d69548e 100644 output_pic_list_index = V4L2_HEVC_DPB_ENTRIES_NUM_MAX; pic_order_cnt[0] = slice_params->slice_pic_order_cnt; pic_order_cnt[1] = slice_params->slice_pic_order_cnt; -@@ -443,36 +558,36 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -444,36 +585,36 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, slice_params->ref_idx_l0, @@ -552,7 +595,7 @@ index f1c3665e95ab..2cc36d69548e 100644 } /* Enable appropriate interruptions. */ -@@ -483,9 +598,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) +@@ -484,9 +625,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) { struct cedrus_dev *dev = ctx->dev; @@ -562,7 +605,7 @@ index f1c3665e95ab..2cc36d69548e 100644 ctx->codec.h265.neighbor_info_buf = dma_alloc_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, &ctx->codec.h265.neighbor_info_buf_addr, -@@ -493,6 +605,17 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) +@@ -494,6 +632,17 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) if (!ctx->codec.h265.neighbor_info_buf) return -ENOMEM; @@ -580,7 +623,7 @@ index f1c3665e95ab..2cc36d69548e 100644 return 0; } -@@ -500,17 +623,12 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx) +@@ -501,17 +650,12 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx) { struct cedrus_dev *dev = ctx->dev; @@ -602,7 +645,7 @@ index f1c3665e95ab..2cc36d69548e 100644 static void cedrus_h265_trigger(struct cedrus_ctx *ctx) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index 87651d6b6227..a2931f322c7a 100644 +index 87651d6b6227..8d153dbe4f83 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h @@ -496,6 +496,9 @@ @@ -615,23 +658,11 @@ index 87651d6b6227..a2931f322c7a 100644 #define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) #define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \ -@@ -513,7 +516,10 @@ - #define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80 - #define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO 0x400 - #define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT 0x20 --#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS 0x800 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_8x8 0x800 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_32x32 0x980 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_16x16 0xa00 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_4x4 0xb80 - #define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0 0xc00 - #define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1 0xc10 - diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index b9acdc03c839..adf00513c15f 100644 +index dbe6f9510641..a0817cae1d69 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -423,8 +423,18 @@ static void cedrus_buf_cleanup(struct vb2_buffer *vb) +@@ -433,8 +433,18 @@ static void cedrus_buf_cleanup(struct vb2_buffer *vb) struct vb2_queue *vq = vb->vb2_queue; struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); @@ -652,24 +683,24 @@ index b9acdc03c839..adf00513c15f 100644 static int cedrus_buf_out_validate(struct vb2_buffer *vb) diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 005c71c67163..4bf3d79047f4 100644 +index 2de83d9f6d47..19469097c6d4 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -14,11 +14,13 @@ - #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 645) - #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 646) - #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 647) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 648) +@@ -17,11 +17,13 @@ + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 1011) /* enum v4l2_ctrl_type type values */ - #define V4L2_CTRL_TYPE_HEVC_SPS 0x0115 - #define V4L2_CTRL_TYPE_HEVC_PPS 0x0116 - #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0117 -+#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0118 + #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 + #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 + #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 ++#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 #define V4L2_HEVC_SLICE_TYPE_B 0 #define V4L2_HEVC_SLICE_TYPE_P 1 -@@ -91,7 +93,7 @@ struct v4l2_ctrl_hevc_pps { +@@ -95,7 +97,7 @@ struct v4l2_ctrl_hevc_pps { __u8 lists_modification_present_flag; __u8 log2_parallel_merge_level_minus2; __u8 slice_segment_header_extension_present_flag; @@ -678,7 +709,7 @@ index 005c71c67163..4bf3d79047f4 100644 }; #define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01 -@@ -175,7 +177,21 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -179,7 +181,21 @@ struct v4l2_ctrl_hevc_slice_params { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ struct v4l2_hevc_pred_weight_table pred_weight_table; @@ -701,3 +732,6 @@ index 005c71c67163..4bf3d79047f4 100644 }; #endif +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch b/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch deleted file mode 100644 index 4ce824a326..0000000000 --- a/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 9ce5c66f0f98cc968598307f7f7feb39a83d7342 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 26 Feb 2019 20:45:14 +0000 -Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error - ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++-- - 1 file changed, 16 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -index 6c323510f128..b5a1a85c8700 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -@@ -7,6 +7,7 @@ - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -+#include - #include - #include - #include -@@ -132,8 +133,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) - - dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); - -- if (stat & CEC_STAT_ERROR_INIT) { -- cec->tx_status = CEC_TX_STATUS_ERROR; -+ /* Status with both done and error_initiator bits have been seen -+ * on Rockchip RK3328 devices, transmit attempt seems to have failed -+ * when this happens, report as low drive and block cec-framework -+ * 100ms before core retransmits the failed message, this seems to -+ * mitigate the issue with failed transmit attempts. -+ */ -+ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { -+ pr_info("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); -+ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; - cec->tx_done = true; - ret = IRQ_WAKE_THREAD; - } else if (stat & CEC_STAT_DONE) { -@@ -144,6 +152,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) - cec->tx_status = CEC_TX_STATUS_NACK; - cec->tx_done = true; - ret = IRQ_WAKE_THREAD; -+ } else if (stat & CEC_STAT_ERROR_INIT) { -+ cec->tx_status = CEC_TX_STATUS_ERROR; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; - } - - if (stat & CEC_STAT_EOM) { -@@ -176,6 +188,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data) - - if (cec->tx_done) { - cec->tx_done = false; -+ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) -+ msleep(100); - cec_transmit_attempt_done(adap, cec->tx_status); - } - if (cec->rx_done) { --- -2.20.1 - diff --git a/projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch b/projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch similarity index 86% rename from projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch rename to projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch index 40849ac4ab..2d5ff656c0 100644 --- a/projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch +++ b/projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch @@ -1,7 +1,7 @@ -From bd5fed9f390fea4ef8df1abb5f4ac6b64fab5974 Mon Sep 17 00:00:00 2001 +From 6a900f36a70f921886f05373846368ca6f09446e Mon Sep 17 00:00:00 2001 From: Jernej Skrabec -Date: Mon, 18 Feb 2019 21:51:31 +0100 -Subject: [PATCH] cedrus h264 4k +Date: Sat, 25 May 2019 14:16:55 +0200 +Subject: [PATCH 5/5] cedrus h264 4k Signed-off-by: Jernej Skrabec --- @@ -16,10 +16,10 @@ Signed-off-by: Jernej Skrabec 8 files changed, 98 insertions(+), 59 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index deb9fa1de97c..8815332fe1c1 100644 +index b518c5613fdf..ee00449d3345 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -116,14 +116,18 @@ struct cedrus_ctx { +@@ -118,14 +118,18 @@ struct cedrus_ctx { union { struct { @@ -43,7 +43,7 @@ index deb9fa1de97c..8815332fe1c1 100644 struct { void *neighbor_info_buf; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index 405545947b85..737a317fd1ee 100644 +index dcb8d3837869..4fafaf2c6c0a 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c @@ -55,16 +55,14 @@ static void cedrus_h264_write_sram(struct cedrus_dev *dev, @@ -73,20 +73,21 @@ index 405545947b85..737a317fd1ee 100644 struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; - unsigned int position = buf->codec.h264.position; - pic->top_field_order_cnt = top_field_order_cnt; - pic->bottom_field_order_cnt = bottom_field_order_cnt; -@@ -84,8 +81,8 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, - - pic->luma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0); - pic->chroma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1); -- pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 0); -- pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 1); -+ pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, buf, 0); -+ pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, buf, 1); + pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt); + pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt); +@@ -85,9 +82,9 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, + pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0)); + pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1)); + pic->mv_col_top_ptr = +- cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0)); ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, buf, 0)); + pic->mv_col_bot_ptr = +- cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1)); ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, buf, 1)); } static void cedrus_write_frame_list(struct cedrus_ctx *ctx, -@@ -148,6 +145,28 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -145,6 +142,28 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); output_buf->codec.h264.position = position; @@ -101,7 +102,7 @@ index 405545947b85..737a317fd1ee 100644 + if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) + field_size = field_size * 2; + -+ output_buf->mv_col_buf_size = ALIGN(field_size, 1024) * 2; ++ output_buf->mv_col_buf_size = field_size * 2; + output_buf->mv_col_buf = + dma_alloc_coherent(dev->dev, + output_buf->mv_col_buf_size, @@ -115,7 +116,7 @@ index 405545947b85..737a317fd1ee 100644 if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) -@@ -331,6 +350,14 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, +@@ -338,6 +357,14 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | VE_H264_VLD_ADDR_LAST); @@ -130,7 +131,7 @@ index 405545947b85..737a317fd1ee 100644 /* * FIXME: Since the bitstream parsing is done in software, and * in userspace, this shouldn't be needed anymore. But it -@@ -471,7 +498,8 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, +@@ -476,7 +503,8 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, { struct cedrus_dev *dev = ctx->dev; @@ -140,7 +141,7 @@ index 405545947b85..737a317fd1ee 100644 cedrus_write(dev, VE_H264_SDROT_CTRL, 0); cedrus_write(dev, VE_H264_EXTRA_BUFFER1, -@@ -490,8 +518,6 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, +@@ -493,8 +521,6 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, static int cedrus_h264_start(struct cedrus_ctx *ctx) { struct cedrus_dev *dev = ctx->dev; @@ -149,7 +150,7 @@ index 405545947b85..737a317fd1ee 100644 int ret; /* -@@ -523,44 +549,42 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) +@@ -526,44 +552,42 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) goto err_pic_buf; } @@ -183,7 +184,7 @@ index 405545947b85..737a317fd1ee 100644 - * we need to work on. - */ - field_size = field_size * 2; -- ctx->codec.h264.mv_col_buf_field_size = ALIGN(field_size, 1024); +- ctx->codec.h264.mv_col_buf_field_size = field_size; - - mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; - ctx->codec.h264.mv_col_buf_size = mv_col_size; @@ -221,7 +222,7 @@ index 405545947b85..737a317fd1ee 100644 err_pic_buf: dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ctx->codec.h264.pic_info_buf, -@@ -572,15 +596,20 @@ static void cedrus_h264_stop(struct cedrus_ctx *ctx) +@@ -575,15 +599,20 @@ static void cedrus_h264_stop(struct cedrus_ctx *ctx) { struct cedrus_dev *dev = ctx->dev; @@ -246,10 +247,10 @@ index 405545947b85..737a317fd1ee 100644 static void cedrus_h264_trigger(struct cedrus_ctx *ctx) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -index 2cc36d69548e..246d747d3fa9 100644 +index 51ee459b2d21..f915429e9c88 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -336,9 +336,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -337,9 +337,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, pred_weight_table = &slice_params->pred_weight_table; /* Activate H265 engine. */ @@ -261,7 +262,7 @@ index 2cc36d69548e..246d747d3fa9 100644 /* Source offset and length in bits. */ diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index 6be604c52d5c..4b6c69010e39 100644 +index 7d2f6eedfc28..9503d395855b 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c @@ -30,7 +30,8 @@ @@ -297,12 +298,12 @@ index 6be604c52d5c..4b6c69010e39 100644 cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -index b43c77d54b95..40b44722b7c0 100644 +index 27d0882397aa..0e67c69812be 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -@@ -18,7 +18,8 @@ - - #define CEDRUS_CLOCK_RATE_DEFAULT 320000000 +@@ -16,7 +16,8 @@ + #ifndef _CEDRUS_HW_H_ + #define _CEDRUS_HW_H_ -int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); +int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec, @@ -311,7 +312,7 @@ index b43c77d54b95..40b44722b7c0 100644 void cedrus_dst_format_set(struct cedrus_dev *dev, diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c -index cb45fda9aaeb..2f6384ca385d 100644 +index 13c34927bad5..fc00a2cbf9bf 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c @@ -96,7 +96,7 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) @@ -339,7 +340,7 @@ index a2931f322c7a..df000b7c99be 100644 #define VE_PRIMARY_FB_LINE_STRIDE 0xc8 diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index adf00513c15f..b24317b26fd2 100644 +index a0817cae1d69..d27a9e82ff91 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c @@ -29,8 +29,8 @@ @@ -354,5 +355,5 @@ index adf00513c15f..b24317b26fd2 100644 static struct cedrus_format cedrus_formats[] = { { -- -2.20.1 +2.21.0 diff --git a/projects/Allwinner/patches/linux/0012-Revert-media-vb2-keep-track-of-timestamp-status.patch b/projects/Allwinner/patches/linux/0012-Revert-media-vb2-keep-track-of-timestamp-status.patch deleted file mode 100644 index 024278d6cc..0000000000 --- a/projects/Allwinner/patches/linux/0012-Revert-media-vb2-keep-track-of-timestamp-status.patch +++ /dev/null @@ -1,91 +0,0 @@ -From e3a864e94eb7b22812d7d9b80403aaba7ade8e49 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 8 May 2019 23:36:51 +0200 -Subject: [PATCH] Revert "media: vb2: keep track of timestamp status" - -This reverts commit 7e4e71624491d8a8befe62b43138beb0ab696006. ---- - drivers/media/common/videobuf2/videobuf2-core.c | 3 --- - drivers/media/common/videobuf2/videobuf2-v4l2.c | 3 +-- - drivers/media/v4l2-core/v4l2-mem2mem.c | 1 - - include/media/videobuf2-core.h | 3 --- - 4 files changed, 1 insertion(+), 9 deletions(-) - -diff --git a/drivers/media/common/videobuf2/videobuf2-core.c b/drivers/media/common/videobuf2/videobuf2-core.c -index 3cf25abf5807..3b0c6d3dd1e3 100644 ---- a/drivers/media/common/videobuf2/videobuf2-core.c -+++ b/drivers/media/common/videobuf2/videobuf2-core.c -@@ -1041,7 +1041,6 @@ static int __prepare_userptr(struct vb2_buffer *vb) - if (vb->planes[plane].mem_priv) { - if (!reacquired) { - reacquired = true; -- vb->copied_timestamp = 0; - call_void_vb_qop(vb, buf_cleanup, vb); - } - call_void_memop(vb, put_userptr, vb->planes[plane].mem_priv); -@@ -1166,7 +1165,6 @@ static int __prepare_dmabuf(struct vb2_buffer *vb) - - if (!reacquired) { - reacquired = true; -- vb->copied_timestamp = 0; - call_void_vb_qop(vb, buf_cleanup, vb); - } - -@@ -1957,7 +1955,6 @@ static void __vb2_queue_cancel(struct vb2_queue *q) - if (vb->request) - media_request_put(vb->request); - vb->request = NULL; -- vb->copied_timestamp = 0; - } - } - -diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c -index fb9ac7696fc6..ba57dee66592 100644 ---- a/drivers/media/common/videobuf2/videobuf2-v4l2.c -+++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c -@@ -608,8 +608,7 @@ int vb2_find_timestamp(const struct vb2_queue *q, u64 timestamp, - unsigned int i; - - for (i = start_idx; i < q->num_buffers; i++) -- if (q->bufs[i]->copied_timestamp && -- q->bufs[i]->timestamp == timestamp) -+ if (q->bufs[i]->timestamp == timestamp) - return i; - return -1; - } -diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c -index 3392833d9541..82ef90af3de1 100644 ---- a/drivers/media/v4l2-core/v4l2-mem2mem.c -+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c -@@ -989,7 +989,6 @@ void v4l2_m2m_buf_copy_metadata(const struct vb2_v4l2_buffer *out_vb, - cap_vb->field = out_vb->field; - cap_vb->flags &= ~mask; - cap_vb->flags |= out_vb->flags & mask; -- cap_vb->vb2_buf.copied_timestamp = 1; - } - EXPORT_SYMBOL_GPL(v4l2_m2m_buf_copy_metadata); - -diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h -index 22f3ff76a8b5..7cdeadb6b596 100644 ---- a/include/media/videobuf2-core.h -+++ b/include/media/videobuf2-core.h -@@ -260,8 +260,6 @@ struct vb2_buffer { - * prepared: this buffer has been prepared, i.e. the - * buf_prepare op was called. It is cleared again - * after the 'buf_finish' op is called. -- * copied_timestamp: the timestamp of this capture buffer was copied -- * from an output buffer. - * queued_entry: entry on the queued buffers list, which holds - * all buffers queued from userspace - * done_entry: entry on the list that stores all buffers ready -@@ -271,7 +269,6 @@ struct vb2_buffer { - enum vb2_buffer_state state; - unsigned int synced:1; - unsigned int prepared:1; -- unsigned int copied_timestamp:1; - - struct vb2_plane planes[VB2_MAX_PLANES]; - struct list_head queued_entry; --- -2.21.0 - diff --git a/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch b/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch deleted file mode 100644 index 680adb5aff..0000000000 --- a/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 18c9a269e2b744ee84f32de9d5c6c66857725ef8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 15 Dec 2018 12:56:53 +0100 -Subject: [PATCH 20/20] cedrus increase frequency - ---- - drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -index b43c77d54b95..70677571f3d3 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -@@ -16,7 +16,7 @@ - #ifndef _CEDRUS_HW_H_ - #define _CEDRUS_HW_H_ - --#define CEDRUS_CLOCK_RATE_DEFAULT 320000000 -+#define CEDRUS_CLOCK_RATE_DEFAULT 402000000 - - int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); - void cedrus_engine_disable(struct cedrus_dev *dev); --- -2.20.0 - diff --git a/scripts/uboot_helper b/scripts/uboot_helper index 8d993311c9..a44942420a 100755 --- a/scripts/uboot_helper +++ b/scripts/uboot_helper @@ -28,6 +28,7 @@ devices = { }, 'H6' : { 'pine_h64' : { 'dtb' : 'sun50i-h6-pine-h64.dtb', 'config' : 'pine_h64_defconfig' }, + 'orangepi_3' : { 'dtb' : 'sun50i-h6-orangepi-3.dtb', 'config' : 'orangepi_3_defconfig' }, }, }, 'Rockchip' : {