2014-08-04 19:55:20 +00:00
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#pragma once
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2014-06-25 01:59:58 +00:00
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#include "stdafx.h"
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#include "BaseMapper.h"
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2014-07-09 23:05:07 +00:00
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#include "CPU.h"
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#include "PPU.h"
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2016-01-07 04:10:29 +00:00
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#include "EmulationSettings.h"
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2014-06-25 01:59:58 +00:00
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class MMC3 : public BaseMapper
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{
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private:
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enum class MMC3Registers
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{
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Reg8000 = 0x8000,
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Reg8001 = 0x8001,
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RegA000 = 0xA000,
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RegA001 = 0xA001,
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RegC000 = 0xC000,
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RegC001 = 0xC001,
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RegE000 = 0xE000,
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RegE001 = 0xE001
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};
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uint8_t _currentRegister;
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uint8_t _prgMode;
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bool _wramEnabled;
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bool _wramWriteProtected;
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2016-07-17 03:19:02 +00:00
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uint32_t _lastCycle;
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uint32_t _cyclesDown;
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2016-06-03 00:35:08 +00:00
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bool _needIrq;
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2014-06-25 01:59:58 +00:00
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struct {
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uint8_t Reg8000;
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uint8_t RegA000;
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uint8_t RegA001;
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} _state;
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void Reset()
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{
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_state.Reg8000 = 0;
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_state.RegA000 = 0;
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_state.RegA001 = 0;
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_chrMode = 0;
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_prgMode = 0;
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_currentRegister = 0;
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memset(_registers, 0, sizeof(_registers));
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_irqCounter = 0;
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_irqReloadValue = 0;
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_irqReload = false;
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_irqEnabled = false;
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2014-06-26 01:52:37 +00:00
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_lastCycle = 0xFFFF;
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2014-06-26 20:41:07 +00:00
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_cyclesDown = 0xFFFF;
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2014-06-25 01:59:58 +00:00
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_wramEnabled = false;
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_wramWriteProtected = false;
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2016-06-03 00:35:08 +00:00
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_needIrq = false;
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2014-06-25 01:59:58 +00:00
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}
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2016-06-03 23:16:31 +00:00
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bool IsMcAcc()
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{
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return _mapperID == 4 && _subMapperID == 3;
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}
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2014-08-04 19:55:20 +00:00
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protected:
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2016-07-17 03:19:02 +00:00
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uint8_t _irqReloadValue;
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uint8_t _irqCounter;
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bool _irqReload;
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bool _irqEnabled;
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2016-07-23 00:27:35 +00:00
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uint8_t _chrMode;
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uint8_t _registers[8];
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2016-07-17 03:19:02 +00:00
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2016-01-24 02:09:01 +00:00
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uint8_t GetCurrentRegister()
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{
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return _currentRegister;
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}
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uint8_t GetChrMode()
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{
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return _chrMode;
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}
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2016-01-21 01:32:49 +00:00
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virtual bool ForceMmc3RevAIrqs() { return false; }
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2014-06-25 01:59:58 +00:00
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2016-01-01 17:34:16 +00:00
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virtual void UpdateMirroring()
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{
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2015-07-30 02:10:34 +00:00
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if(GetMirroringType() != MirroringType::FourScreens) {
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SetMirroringType(((_state.RegA000 & 0x01) == 0x01) ? MirroringType::Horizontal : MirroringType::Vertical);
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2014-06-25 01:59:58 +00:00
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}
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2016-01-01 17:34:16 +00:00
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}
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2014-06-25 01:59:58 +00:00
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2016-01-01 17:34:16 +00:00
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virtual void UpdateChrMapping()
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{
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2014-06-25 01:59:58 +00:00
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if(_chrMode == 0) {
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2014-07-13 01:01:28 +00:00
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SelectCHRPage(0, _registers[0] & 0xFE);
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SelectCHRPage(1, _registers[0] | 0x01);
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SelectCHRPage(2, _registers[1] & 0xFE);
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SelectCHRPage(3, _registers[1] | 0x01);
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2014-06-25 01:59:58 +00:00
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SelectCHRPage(4, _registers[2]);
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SelectCHRPage(5, _registers[3]);
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SelectCHRPage(6, _registers[4]);
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SelectCHRPage(7, _registers[5]);
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} else if(_chrMode == 1) {
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SelectCHRPage(0, _registers[2]);
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SelectCHRPage(1, _registers[3]);
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SelectCHRPage(2, _registers[4]);
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SelectCHRPage(3, _registers[5]);
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2014-07-13 01:01:28 +00:00
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SelectCHRPage(4, _registers[0] & 0xFE);
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SelectCHRPage(5, _registers[0] | 0x01);
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SelectCHRPage(6, _registers[1] & 0xFE);
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SelectCHRPage(7, _registers[1] | 0x01);
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2014-06-25 01:59:58 +00:00
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}
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2016-01-01 17:34:16 +00:00
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}
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2016-01-21 01:05:18 +00:00
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bool CanWriteToWorkRam()
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{
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return _wramEnabled && !_wramWriteProtected;
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}
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2016-01-01 17:34:16 +00:00
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virtual void UpdateState()
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{
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_currentRegister = _state.Reg8000 & 0x07;
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_chrMode = (_state.Reg8000 & 0x80) >> 7;
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_prgMode = (_state.Reg8000 & 0x40) >> 6;
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UpdateMirroring();
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_wramEnabled = (_state.RegA001 & 0x80) == 0x80;
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_wramWriteProtected = (_state.RegA001 & 0x40) == 0x40;
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if(_prgMode == 0) {
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SelectPRGPage(0, _registers[6]);
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SelectPRGPage(1, _registers[7]);
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SelectPRGPage(2, -2);
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SelectPRGPage(3, -1);
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} else if(_prgMode == 1) {
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SelectPRGPage(0, -2);
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SelectPRGPage(1, _registers[7]);
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SelectPRGPage(2, _registers[6]);
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SelectPRGPage(3, -1);
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}
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UpdateChrMapping();
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2014-06-25 01:59:58 +00:00
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}
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2014-08-04 19:55:20 +00:00
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virtual void StreamState(bool saving)
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2014-06-26 01:52:37 +00:00
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{
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BaseMapper::StreamState(saving);
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2016-06-03 03:56:11 +00:00
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ArrayInfo<uint8_t> registers = { _registers, 8 };
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2016-06-03 00:20:26 +00:00
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Stream(_state.Reg8000, _state.RegA000, _state.RegA001, _currentRegister, _chrMode, _prgMode,
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_irqReloadValue, _irqCounter, _irqReload, _irqEnabled, _lastCycle, _cyclesDown,
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2016-06-03 03:56:11 +00:00
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_wramEnabled, _wramWriteProtected, registers, _needIrq);
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2014-06-26 01:52:37 +00:00
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}
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2015-08-10 00:45:45 +00:00
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virtual uint16_t GetPRGPageSize() { return 0x2000; }
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virtual uint16_t GetCHRPageSize() { return 0x0400; }
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2014-06-25 01:59:58 +00:00
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2016-01-21 01:32:49 +00:00
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virtual void InitMapper()
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2014-06-25 01:59:58 +00:00
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{
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Reset();
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2016-01-24 16:18:50 +00:00
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SetCpuMemoryMapping(0x6000, 0x7FFF, 0, HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam);
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2014-06-25 01:59:58 +00:00
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UpdateState();
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}
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2016-01-01 17:34:16 +00:00
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virtual void WriteRegister(uint16_t addr, uint8_t value)
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2014-06-25 01:59:58 +00:00
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{
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switch((MMC3Registers)(addr & 0xE001)) {
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case MMC3Registers::Reg8000:
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_state.Reg8000 = value;
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UpdateState();
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break;
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case MMC3Registers::Reg8001:
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if(_currentRegister >= 6) {
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//"Writes to registers 6 and 7 always ignore bits 6 and 7, as the MMC3 has only 6 PRG ROM address output lines."
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value &= 0x3F;
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} else if(_currentRegister <= 1) {
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//"Writes to registers 0 and 1 always ignore bit 0"
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value &= ~0x01;
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}
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_registers[_currentRegister] = value;
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UpdateState();
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break;
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case MMC3Registers::RegA000:
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_state.RegA000 = value;
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UpdateState();
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break;
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case MMC3Registers::RegA001:
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_state.RegA001 = value;
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UpdateState();
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break;
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case MMC3Registers::RegC000:
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_irqReloadValue = value;
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break;
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case MMC3Registers::RegC001:
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_irqCounter = 0;
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_irqReload = true;
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break;
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case MMC3Registers::RegE000:
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_irqEnabled = false;
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2014-06-25 21:30:35 +00:00
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CPU::ClearIRQSource(IRQSource::External);
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2014-06-25 01:59:58 +00:00
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break;
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case MMC3Registers::RegE001:
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_irqEnabled = true;
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break;
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}
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}
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2016-07-17 03:19:02 +00:00
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virtual void TriggerIrq()
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2016-06-03 00:35:08 +00:00
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{
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2016-06-03 23:16:31 +00:00
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if(IsMcAcc()) {
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//MC-ACC (Acclaim copy of the MMC3)
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2016-06-03 00:35:08 +00:00
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//IRQ will be triggered on the next falling edge of A12 instead of on the rising edge like normal MMC3 behavior
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//This adds a 4 ppu cycle delay (until the PPU fetches the next garbage NT tile between sprites)
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_needIrq = true;
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2016-06-03 23:16:31 +00:00
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} else {
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CPU::SetIRQSource(IRQSource::External);
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2016-06-03 00:35:08 +00:00
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}
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}
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2014-07-13 02:22:40 +00:00
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public:
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2014-06-25 21:30:35 +00:00
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virtual void NotifyVRAMAddressChange(uint16_t addr)
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2014-06-25 01:59:58 +00:00
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{
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2014-06-26 20:41:07 +00:00
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uint32_t cycle = PPU::GetFrameCycle();
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2014-06-25 21:30:35 +00:00
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if((addr & 0x1000) == 0) {
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2016-06-03 00:35:08 +00:00
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if(_needIrq) {
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2016-06-03 23:16:31 +00:00
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//Used by MC-ACC (Acclaim copy of the MMC3), see TriggerIrq above
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2016-06-03 00:35:08 +00:00
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CPU::SetIRQSource(IRQSource::External);
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_needIrq = false;
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}
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2014-06-25 21:30:35 +00:00
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if(_cyclesDown == 0) {
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_cyclesDown = 1;
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2014-06-25 01:59:58 +00:00
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} else {
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2014-06-25 21:30:35 +00:00
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if(_lastCycle > cycle) {
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2014-06-26 20:41:07 +00:00
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//We changed frames
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_cyclesDown += (89342 - _lastCycle) + cycle;
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2014-06-25 21:30:35 +00:00
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} else {
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2014-06-26 20:41:07 +00:00
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_cyclesDown += (cycle - _lastCycle);
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2014-06-25 21:30:35 +00:00
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}
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2014-06-25 01:59:58 +00:00
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}
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2014-06-25 21:30:35 +00:00
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} else if(addr & 0x1000) {
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if(_cyclesDown > 8) {
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uint32_t count = _irqCounter;
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if(_irqCounter == 0 || _irqReload) {
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_irqCounter = _irqReloadValue;
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} else {
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_irqCounter--;
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}
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2014-06-26 20:41:07 +00:00
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2016-06-03 23:16:31 +00:00
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//SubMapper 2 = MC-ACC (Acclaim MMC3 clone)
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if(!IsMcAcc() && (ForceMmc3RevAIrqs() || EmulationSettings::CheckFlag(EmulationFlags::Mmc3IrqAltBehavior))) {
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2016-01-21 01:32:49 +00:00
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//MMC3 Revision A behavior
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2016-01-07 04:10:29 +00:00
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if((count > 0 || _irqReload) && _irqCounter == 0 && _irqEnabled) {
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2016-06-03 00:35:08 +00:00
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TriggerIrq();
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2016-01-07 04:10:29 +00:00
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}
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} else {
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if(_irqCounter == 0 && _irqEnabled) {
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2016-06-03 00:35:08 +00:00
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TriggerIrq();
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2016-01-07 04:10:29 +00:00
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}
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2014-06-25 21:30:35 +00:00
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}
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_irqReload = false;
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2014-06-25 01:59:58 +00:00
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}
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2014-06-25 21:30:35 +00:00
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_cyclesDown = 0;
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}
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_lastCycle = cycle;
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2014-06-25 01:59:58 +00:00
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}
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};
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