Study box - Minor improvements, most likely not accurate

This commit is contained in:
Souryo 2016-10-30 10:37:15 -04:00
parent 9aa6f1deaf
commit 6870dbbeb0

View File

@ -6,6 +6,9 @@ class StudyBox : public BaseMapper
{
private:
uint8_t _prgRamReg;
bool _tapeReady = false;
uint16_t _tapeReadyDelay = 0;
uint8_t _reg4202 = 0;
protected:
virtual uint16_t RegisterStartAddress() { return 0x4200; }
@ -41,8 +44,14 @@ protected:
uint8_t ReadRegister(uint16_t addr)
{
switch(addr) {
case 0x4200: case 0x4201: case 0x4203: return 0x00;
case 0x4202: return 0x40;
case 0x4200: case 0x4203: return 0x00;
case 0x4201:
return 0x10; /* | (EmulationSettings::CheckFlag(EmulationFlags::ShowFPS) ? 0x20 : 0x00)
| (EmulationSettings::CheckFlag(EmulationFlags::Turbo) ? 0x40 : 0x00); */
/*(EmulationSettings::CheckFlag(EmulationFlags::ShowFPS) ? 0x00 : 0x20) |
(EmulationSettings::CheckFlag(EmulationFlags::Turbo) ? 0x00 : 0x50);*/
case 0x4202: return _tapeReady ? 0x40 : 0x00;
default: return 0xFF;
}
}
@ -52,12 +61,28 @@ protected:
SetCpuMemoryMapping(0x6000, 0x7FFF, _prgRamReg, PrgMemoryType::WorkRam);
}
void ProcessCpuClock()
{
if(_tapeReadyDelay > 0) {
_tapeReadyDelay--;
if(_tapeReadyDelay == 0) {
_tapeReady = (_reg4202 & 0x10) == 0x10;
}
}
}
void WriteRegister(uint16_t addr, uint8_t value)
{
if(addr & 0x4203) {
switch(addr & 0x03) {
case 0: _prgRamReg = value >> 6; UpdateState(); break;
case 1: SelectPRGPage(0, value); break;
case 2:
_reg4202 = value;
_tapeReadyDelay = 100;
break;
case 3:
break;
}
}
}