mirror of
https://github.com/libretro/Mesen.git
synced 2024-11-24 01:29:41 +00:00
CPU: Rewrote logic to use an addressing mode table, implemented dummy writes
This commit is contained in:
Souryo
parent
674e64e655
commit
941efc4110
62
Core/CPU.cpp
62
Core/CPU.cpp
@ -9,23 +9,42 @@ uint32_t CPU::IRQFlag = 0;
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CPU::CPU(MemoryManager *memoryManager) : _memoryManager(memoryManager)
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CPU::CPU(MemoryManager *memoryManager) : _memoryManager(memoryManager)
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{
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{
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Func opTable[] = {
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Func opTable[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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&CPU::BRK, &CPU::ORA_IndX, nullptr, nullptr, nullptr, &CPU::ORA_Zero, &CPU::ASL_Zero, nullptr, &CPU::PHP, &CPU::ORA_Imm, &CPU::ASL_Acc, nullptr, nullptr, &CPU::ORA_Abs, &CPU::ASL_Abs, nullptr, //0
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&CPU::BRK, &CPU::ORA, nullptr, nullptr, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, nullptr, &CPU::PHP, &CPU::ORA, &CPU::ASL_Acc, nullptr, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, nullptr, //0
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&CPU::BPL, &CPU::ORA_IndY, nullptr, nullptr, nullptr, &CPU::ORA_ZeroX, &CPU::ASL_ZeroX, nullptr, &CPU::CLC, &CPU::ORA_AbsY, nullptr, nullptr, nullptr, &CPU::ORA_AbsX, &CPU::ASL_AbsX, nullptr, //1
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&CPU::BPL, &CPU::ORA, nullptr, nullptr, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, nullptr, &CPU::CLC, &CPU::ORA, nullptr, nullptr, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, nullptr, //1
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&CPU::JSR, &CPU::AND_IndX, nullptr, nullptr, &CPU::BIT_Zero, &CPU::AND_Zero, &CPU::ROL_Zero, nullptr, &CPU::PLP, &CPU::AND_Imm, &CPU::ROL_Acc, nullptr, &CPU::BIT_Abs, &CPU::AND_Abs, &CPU::ROL_Abs, nullptr, //2
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&CPU::JSR, &CPU::AND, nullptr, nullptr, &CPU::BIT, &CPU::AND, &CPU::ROL_Memory, nullptr, &CPU::PLP, &CPU::AND, &CPU::ROL_Acc, nullptr, &CPU::BIT, &CPU::AND, &CPU::ROL_Memory, nullptr, //2
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&CPU::BMI, &CPU::AND_IndY, nullptr, nullptr, nullptr, &CPU::AND_ZeroX, &CPU::ROL_ZeroX, nullptr, &CPU::SEC, &CPU::AND_AbsY, nullptr, nullptr, nullptr, &CPU::AND_AbsX, &CPU::ROL_AbsX, nullptr, //3
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&CPU::BMI, &CPU::AND, nullptr, nullptr, &CPU::NOP, &CPU::AND, &CPU::ROL_Memory, nullptr, &CPU::SEC, &CPU::AND, nullptr, nullptr, &CPU::NOP, &CPU::AND, &CPU::ROL_Memory, nullptr, //3
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&CPU::RTI, &CPU::EOR_IndX, nullptr, nullptr, nullptr, &CPU::EOR_Zero, &CPU::LSR_Zero, nullptr, &CPU::PHA, &CPU::EOR_Imm, &CPU::LSR_Acc, nullptr, &CPU::JMP_Abs, &CPU::EOR_Abs, &CPU::LSR_Abs, nullptr, //4
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&CPU::RTI, &CPU::EOR, nullptr, nullptr, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, nullptr, &CPU::PHA, &CPU::EOR, &CPU::LSR_Acc, nullptr, &CPU::JMP_Abs, &CPU::EOR, &CPU::LSR_Memory, nullptr, //4
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&CPU::BVC, &CPU::EOR_IndY, nullptr, nullptr, nullptr, &CPU::EOR_ZeroX, &CPU::LSR_ZeroX, nullptr, &CPU::CLI, &CPU::EOR_AbsY, nullptr, nullptr, nullptr, &CPU::EOR_AbsX, &CPU::LSR_AbsX, nullptr, //5
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&CPU::BVC, &CPU::EOR, nullptr, nullptr, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, nullptr, &CPU::CLI, &CPU::EOR, nullptr, nullptr, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, nullptr, //5
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&CPU::RTS, &CPU::ADC_IndX, nullptr, nullptr, nullptr, &CPU::ADC_Zero, &CPU::ROR_Zero, nullptr, &CPU::PLA, &CPU::ADC_Imm, &CPU::ROR_Acc, nullptr, &CPU::JMP_Ind, &CPU::ADC_Abs, &CPU::ROR_Abs, nullptr, //6
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&CPU::RTS, &CPU::ADC, nullptr, nullptr, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, nullptr, &CPU::PLA, &CPU::ADC, &CPU::ROR_Acc, nullptr, &CPU::JMP_Ind, &CPU::ADC, &CPU::ROR_Memory, nullptr, //6
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&CPU::BVS, &CPU::ADC_IndY, nullptr, nullptr, nullptr, &CPU::ADC_ZeroX, &CPU::ROR_ZeroX, nullptr, &CPU::SEI, &CPU::ADC_AbsY, nullptr, nullptr, nullptr, &CPU::ADC_AbsX, &CPU::ROR_AbsX, nullptr, //7
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&CPU::BVS, &CPU::ADC, nullptr, nullptr, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, nullptr, &CPU::SEI, &CPU::ADC, nullptr, nullptr, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, nullptr, //7
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nullptr, &CPU::STA_IndX, nullptr, nullptr, &CPU::STY_Zero, &CPU::STA_Zero, &CPU::STX_Zero, nullptr, &CPU::DEY, &CPU::NOP2, &CPU::TXA, nullptr, &CPU::STY_Abs, &CPU::STA_Abs, &CPU::STX_Abs, nullptr, //8
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&CPU::NOP, &CPU::STA, &CPU::NOP, nullptr, &CPU::STY, &CPU::STA, &CPU::STX, nullptr, &CPU::DEY, &CPU::NOP, &CPU::TXA, nullptr, &CPU::STY, &CPU::STA, &CPU::STX, nullptr, //8
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&CPU::BCC, &CPU::STA_IndY, nullptr, nullptr, &CPU::STY_ZeroX, &CPU::STA_ZeroX, &CPU::STX_ZeroY, nullptr, &CPU::TYA, &CPU::STA_AbsY, &CPU::TXS, nullptr, nullptr, &CPU::STA_AbsX, nullptr, nullptr, //9
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&CPU::BCC, &CPU::STA, nullptr, nullptr, &CPU::STY, &CPU::STA, &CPU::STX, nullptr, &CPU::TYA, &CPU::STA, &CPU::TXS, nullptr, nullptr, &CPU::STA, nullptr, nullptr, //9
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&CPU::LDY_Imm, &CPU::LDA_IndX, &CPU::LDX_Imm, nullptr, &CPU::LDY_Zero, &CPU::LDA_Zero, &CPU::LDX_Zero, nullptr, &CPU::TAY, &CPU::LDA_Imm, &CPU::TAX, nullptr, &CPU::LDY_Abs, &CPU::LDA_Abs, &CPU::LDX_Abs, nullptr, //A
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&CPU::LDY, &CPU::LDA, &CPU::LDX, nullptr, &CPU::LDY, &CPU::LDA, &CPU::LDX, nullptr, &CPU::TAY, &CPU::LDA, &CPU::TAX, nullptr, &CPU::LDY, &CPU::LDA, &CPU::LDX, nullptr, //A
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&CPU::BCS, &CPU::LDA_IndY, nullptr, nullptr, &CPU::LDY_ZeroX, &CPU::LDA_ZeroX, &CPU::LDX_ZeroY, nullptr, &CPU::CLV, &CPU::LDA_AbsY, &CPU::TSX, nullptr, &CPU::LDY_AbsX, &CPU::LDA_AbsX, &CPU::LDX_AbsY, nullptr, //B
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&CPU::BCS, &CPU::LDA, nullptr, nullptr, &CPU::LDY, &CPU::LDA, &CPU::LDX, nullptr, &CPU::CLV, &CPU::LDA, &CPU::TSX, nullptr, &CPU::LDY, &CPU::LDA, &CPU::LDX, nullptr, //B
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&CPU::CPY_Imm, &CPU::CMP_IndX, nullptr, nullptr, &CPU::CPY_Zero, &CPU::CMP_Zero, &CPU::DEC_Zero, nullptr, &CPU::INY, &CPU::CMP_Imm, &CPU::DEX, nullptr, &CPU::CPY_Abs, &CPU::CMP_Abs, &CPU::DEC_Abs, nullptr, //C
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&CPU::CPY, &CPU::CPA, &CPU::NOP, nullptr, &CPU::CPY, &CPU::CPA, &CPU::DEC, nullptr, &CPU::INY, &CPU::CPA, &CPU::DEX, nullptr, &CPU::CPY, &CPU::CPA, &CPU::DEC, nullptr, //C
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&CPU::BNE, &CPU::CMP_IndY, nullptr, nullptr, nullptr, &CPU::CMP_ZeroX, &CPU::DEC_ZeroX, nullptr, &CPU::CLD, &CPU::CMP_AbsY, nullptr, nullptr, nullptr, &CPU::CMP_AbsX, &CPU::DEC_AbsX, nullptr, //D
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&CPU::BNE, &CPU::CPA, nullptr, nullptr, &CPU::NOP, &CPU::CPA, &CPU::DEC, nullptr, &CPU::CLD, &CPU::CPA, nullptr, nullptr, &CPU::NOP, &CPU::CPA, &CPU::DEC, nullptr, //D
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&CPU::CPX_Imm, &CPU::SBC_IndX, nullptr, nullptr, &CPU::CPX_Zero, &CPU::SBC_Zero, &CPU::INC_Zero, nullptr, &CPU::INX, &CPU::SBC_Imm, &CPU::NOP, nullptr, &CPU::CPX_Abs, &CPU::SBC_Abs, &CPU::INC_Abs, nullptr, //E
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&CPU::CPX, &CPU::SBC, &CPU::NOP, nullptr, &CPU::CPX, &CPU::SBC, &CPU::INC, nullptr, &CPU::INX, &CPU::SBC, &CPU::NOP, nullptr, &CPU::CPX, &CPU::SBC, &CPU::INC, nullptr, //E
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&CPU::BEQ, &CPU::SBC_IndY, nullptr, nullptr, nullptr, &CPU::SBC_ZeroX, &CPU::INC_ZeroX, nullptr, &CPU::SED, &CPU::SBC_AbsY, nullptr, nullptr, nullptr, &CPU::SBC_AbsX, &CPU::INC_AbsX, nullptr //F
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&CPU::BEQ, &CPU::SBC, nullptr, nullptr, &CPU::NOP, &CPU::SBC, &CPU::INC, nullptr, &CPU::SED, &CPU::SBC, nullptr, nullptr, &CPU::NOP, &CPU::SBC, &CPU::INC, nullptr //F
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};
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AddrMode addrMode[] = {
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Imm, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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None, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Imp, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Imp, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndYW, None, IndY, ZeroX, ZeroX, ZeroY, ZeroY, Imp, AbsYW, Imp, AbsY, AbsXW, AbsXW, AbsYW, AbsY,
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndY, ZeroX, ZeroX, ZeroY, ZeroY, Imp, AbsY, Imp, AbsY, AbsX, AbsX, AbsY, AbsY,
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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};
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};
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uint8_t cycles[] {
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uint8_t cycles[] {
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@ -66,9 +85,10 @@ CPU::CPU(MemoryManager *memoryManager) : _memoryManager(memoryManager)
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3, 6, 2, 8, 4, 4, 6, 6, 2, 5, 2, 7, 5, 5, 7, 7,
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3, 6, 2, 8, 4, 4, 6, 6, 2, 5, 2, 7, 5, 5, 7, 7,
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};
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};
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memcpy(_opTable, opTable, sizeof(Func) * 256);
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memcpy(_opTable, opTable, sizeof(opTable));
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memcpy(_cycles, cycles, sizeof(uint8_t) * 256);
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memcpy(_cycles, cycles, sizeof(cycles));
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memcpy(_cyclesPageCrossed, cyclesPageCrossed, sizeof(uint8_t) * 256);
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memcpy(_addrMode, addrMode, sizeof(addrMode));
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memcpy(_cyclesPageCrossed, cyclesPageCrossed, sizeof(cyclesPageCrossed));
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}
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}
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void CPU::Reset(bool softReset)
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void CPU::Reset(bool softReset)
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@ -106,11 +126,13 @@ uint32_t CPU::Exec()
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_runIRQ = true;
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_runIRQ = true;
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}
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}
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_instAddrMode = _addrMode[opCode];
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if(_opTable[opCode] != nullptr) {
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if(_opTable[opCode] != nullptr) {
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//std::cout << std::hex << (_state.PC - 1) << ": " << (short)opCode << std::endl;
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//std::cout << std::hex << (_state.PC - 1) << ": " << (short)opCode << std::endl;
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(this->*_opTable[opCode])();
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(this->*_opTable[opCode])();
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executedCycles = (IsPageCrossed() ? _cyclesPageCrossed[opCode] : _cycles[opCode]);
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executedCycles = (IsPageCrossed() ? _cyclesPageCrossed[opCode] : _cycles[opCode]);
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} else {
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} else {
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GetOperandAddr();
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std::cout << "Invalid opcode: " << std::hex << (short)opCode;
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std::cout << "Invalid opcode: " << std::hex << (short)opCode;
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//throw exception("Invalid opcode");
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//throw exception("Invalid opcode");
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}
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}
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259
Core/CPU.h
259
Core/CPU.h
@ -19,6 +19,14 @@ namespace PSFlags
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};
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};
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}
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}
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enum AddrMode
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{
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None, Imp, Imm, Rel,
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Zero, ZeroX, ZeroY,
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IndX, IndY, IndYW,
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Abs, AbsX, AbsXW, AbsY, AbsYW
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};
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enum class IRQSource
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enum class IRQSource
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{
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{
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External = 1,
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External = 1,
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@ -50,6 +58,8 @@ private:
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Func _opTable[256];
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Func _opTable[256];
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uint8_t _cycles[256];
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uint8_t _cycles[256];
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AddrMode _addrMode[256];
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AddrMode _instAddrMode;
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uint8_t _cyclesPageCrossed[256];
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uint8_t _cyclesPageCrossed[256];
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bool _pageCrossed = false;
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bool _pageCrossed = false;
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@ -163,6 +173,36 @@ private:
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uint16_t PC() { return _state.PC; }
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uint16_t PC() { return _state.PC; }
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void SetPC(uint16_t value) { _state.PC = value; }
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void SetPC(uint16_t value) { _state.PC = value; }
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uint16_t GetOperandAddr()
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{
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switch(_instAddrMode) {
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case AddrMode::Abs: return GetAbsAddr();
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case AddrMode::AbsX: return GetAbsXAddr(false);
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case AddrMode::AbsXW: return GetAbsXAddr(true);
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case AddrMode::AbsY: return GetAbsYAddr(false);
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case AddrMode::AbsYW: return GetAbsYAddr(true);
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case AddrMode::Imm: return GetImmediate();
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case AddrMode::IndX: return GetIndXAddr();
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case AddrMode::IndY: return GetIndYAddr(false);
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case AddrMode::IndYW: return GetIndYAddr(true);
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case AddrMode::Zero: return GetZeroAddr();
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case AddrMode::ZeroX: return GetZeroXAddr();
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case AddrMode::ZeroY: return GetZeroYAddr();
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}
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return 0;
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}
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uint8_t GetOperand()
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{
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uint16_t addr = GetOperandAddr();
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if(_instAddrMode != AddrMode::Imm) {
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return MemoryRead(addr);
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} else {
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return (uint8_t)addr;
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}
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}
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uint8_t GetImmediate() { return ReadByte(); }
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uint8_t GetImmediate() { return ReadByte(); }
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uint8_t GetZero() { return MemoryRead(GetZeroAddr()); }
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uint8_t GetZero() { return MemoryRead(GetZeroAddr()); }
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uint8_t GetZeroAddr() { return ReadByte(); }
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uint8_t GetZeroAddr() { return ReadByte(); }
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@ -249,11 +289,12 @@ private:
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return addr + Y();
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return addr + Y();
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}
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}
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void AND(uint8_t value) { SetA(A() & value); }
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void AND() { SetA(A() & GetOperand()); }
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void XOR(uint8_t value) { SetA(A() ^ value); }
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void EOR() { SetA(A() ^ GetOperand()); }
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void OR(uint8_t value) { SetA(A() | value); }
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void ORA() { SetA(A() | GetOperand()); }
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void ADC(uint8_t value) {
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void ADD(uint8_t value)
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{
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uint16_t result = (uint16_t)A() + (uint16_t)value + (CheckFlag(PSFlags::Carry) ? PSFlags::Carry : 0x00);
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uint16_t result = (uint16_t)A() + (uint16_t)value + (CheckFlag(PSFlags::Carry) ? PSFlags::Carry : 0x00);
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ClearFlags(PSFlags::Carry | PSFlags::Negative | PSFlags::Overflow | PSFlags::Zero);
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ClearFlags(PSFlags::Carry | PSFlags::Negative | PSFlags::Overflow | PSFlags::Zero);
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@ -267,9 +308,11 @@ private:
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SetA((uint8_t)result);
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SetA((uint8_t)result);
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}
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}
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void SBC(uint8_t value) { ADC(value ^ 0xFF); }
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void ADC() { ADD(GetOperand()); }
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void SBC() { ADD(GetOperand() ^ 0xFF); }
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void CMP(uint8_t reg, uint8_t value) {
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void CMP(uint8_t reg, uint8_t value)
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{
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ClearFlags(PSFlags::Carry | PSFlags::Negative | PSFlags::Zero);
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ClearFlags(PSFlags::Carry | PSFlags::Negative | PSFlags::Zero);
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auto result = reg - value;
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auto result = reg - value;
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@ -285,22 +328,33 @@ private:
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}
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}
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}
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}
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void CPA(uint8_t value) { CMP(A(), value); }
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void CPA() { CMP(A(), GetOperand()); }
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void CPX(uint8_t value) { CMP(X(), value); }
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void CPX() { CMP(X(), GetOperand()); }
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void CPY(uint8_t value) { CMP(Y(), value); }
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void CPY() { CMP(Y(), GetOperand()); }
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void INC(uint16_t addr) {
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void INC()
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{
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uint16_t addr = GetOperandAddr();
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ClearFlags(PSFlags::Negative | PSFlags::Zero);
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ClearFlags(PSFlags::Negative | PSFlags::Zero);
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uint8_t memory = MemoryRead(addr) + 1;
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uint8_t value = MemoryRead(addr);
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SetZeroNegativeFlags(memory);
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MemoryWrite(addr, memory);
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MemoryWrite(addr, value); //Dummy write
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value++;
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SetZeroNegativeFlags(value);
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MemoryWrite(addr, value);
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}
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}
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void DEC(uint16_t addr) {
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void DEC()
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{
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uint16_t addr = GetOperandAddr();
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ClearFlags(PSFlags::Negative | PSFlags::Zero);
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ClearFlags(PSFlags::Negative | PSFlags::Zero);
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uint8_t memory = MemoryRead(addr) - 1;
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uint8_t value = MemoryRead(addr);
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SetZeroNegativeFlags(memory);
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MemoryWrite(addr, value); //Dummy write
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MemoryWrite(addr, memory);
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value--;
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SetZeroNegativeFlags(value);
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MemoryWrite(addr, value);
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}
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}
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uint8_t ASL(uint8_t value)
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uint8_t ASL(uint8_t value)
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@ -351,23 +405,31 @@ private:
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return result;
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return result;
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}
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}
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void ASLAddr(uint16_t addr) {
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void ASLAddr() {
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uint16_t addr = GetOperandAddr();
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uint8_t value = MemoryRead(addr);
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uint8_t value = MemoryRead(addr);
|
||||||
|
MemoryWrite(addr, value); //Dummy write
|
||||||
MemoryWrite(addr, ASL(value));
|
MemoryWrite(addr, ASL(value));
|
||||||
}
|
}
|
||||||
|
|
||||||
void LSRAddr(uint16_t addr) {
|
void LSRAddr() {
|
||||||
|
uint16_t addr = GetOperandAddr();
|
||||||
uint8_t value = MemoryRead(addr);
|
uint8_t value = MemoryRead(addr);
|
||||||
|
MemoryWrite(addr, value); //Dummy write
|
||||||
MemoryWrite(addr, LSR(value));
|
MemoryWrite(addr, LSR(value));
|
||||||
}
|
}
|
||||||
|
|
||||||
void ROLAddr(uint16_t addr) {
|
void ROLAddr() {
|
||||||
|
uint16_t addr = GetOperandAddr();
|
||||||
uint8_t value = MemoryRead(addr);
|
uint8_t value = MemoryRead(addr);
|
||||||
|
MemoryWrite(addr, value); //Dummy write
|
||||||
MemoryWrite(addr, ROL(value));
|
MemoryWrite(addr, ROL(value));
|
||||||
}
|
}
|
||||||
|
|
||||||
void RORAddr(uint16_t addr) {
|
void RORAddr() {
|
||||||
|
uint16_t addr = GetOperandAddr();
|
||||||
uint8_t value = MemoryRead(addr);
|
uint8_t value = MemoryRead(addr);
|
||||||
|
MemoryWrite(addr, value); //Dummy write
|
||||||
MemoryWrite(addr, ROR(value));
|
MemoryWrite(addr, ROR(value));
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -385,7 +447,8 @@ private:
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void BIT(uint8_t value) {
|
void BIT() {
|
||||||
|
uint8_t value = GetOperand();
|
||||||
ClearFlags(PSFlags::Zero | PSFlags::Overflow | PSFlags::Negative);
|
ClearFlags(PSFlags::Zero | PSFlags::Overflow | PSFlags::Negative);
|
||||||
if((A() & value) == 0) {
|
if((A() & value) == 0) {
|
||||||
SetFlags(PSFlags::Zero);
|
SetFlags(PSFlags::Zero);
|
||||||
@ -411,42 +474,13 @@ private:
|
|||||||
}
|
}
|
||||||
|
|
||||||
#pragma region OP Codes
|
#pragma region OP Codes
|
||||||
void LDA_Imm() { SetA(GetImmediate()); }
|
void LDA() { SetA(GetOperand()); }
|
||||||
void LDA_Zero() { SetA(GetZero()); }
|
void LDX() { SetX(GetOperand()); }
|
||||||
void LDA_ZeroX() { SetA(GetZeroX()); }
|
void LDY() { SetY(GetOperand()); }
|
||||||
void LDA_Abs() { SetA(GetAbs()); }
|
|
||||||
void LDA_AbsX() { SetA(GetAbsX()); }
|
|
||||||
void LDA_AbsY() { SetA(GetAbsY()); }
|
|
||||||
void LDA_IndX() { SetA(GetIndX()); }
|
|
||||||
void LDA_IndY() { SetA(GetIndY()); }
|
|
||||||
|
|
||||||
void LDX_Imm() { SetX(GetImmediate()); }
|
void STA() { MemoryWrite(GetOperandAddr(), A()); }
|
||||||
void LDX_Zero() { SetX(GetZero()); }
|
void STX() { MemoryWrite(GetOperandAddr(), X()); }
|
||||||
void LDX_ZeroY() { SetX(GetZeroY()); }
|
void STY() { MemoryWrite(GetOperandAddr(), Y()); }
|
||||||
void LDX_Abs() { SetX(GetAbs()); }
|
|
||||||
void LDX_AbsY() { SetX(GetAbsY()); }
|
|
||||||
|
|
||||||
void LDY_Imm() { SetY(GetImmediate()); }
|
|
||||||
void LDY_Zero() { SetY(GetZero()); }
|
|
||||||
void LDY_ZeroX() { SetY(GetZeroX()); }
|
|
||||||
void LDY_Abs() { SetY(GetAbs()); }
|
|
||||||
void LDY_AbsX() { SetY(GetAbsX()); }
|
|
||||||
|
|
||||||
void STA_Zero() { MemoryWrite(GetZeroAddr(), A()); }
|
|
||||||
void STA_ZeroX() { MemoryWrite(GetZeroXAddr(), A()); }
|
|
||||||
void STA_Abs() { MemoryWrite(GetAbsAddr(), A()); }
|
|
||||||
void STA_AbsX() { MemoryWrite(GetAbsXAddr(), A()); }
|
|
||||||
void STA_AbsY() { MemoryWrite(GetAbsYAddr(), A()); }
|
|
||||||
void STA_IndX() { MemoryWrite(GetIndXAddr(), A()); }
|
|
||||||
void STA_IndY() { MemoryWrite(GetIndYAddr(), A()); }
|
|
||||||
|
|
||||||
void STX_Zero() { MemoryWrite(GetZeroAddr(), X()); }
|
|
||||||
void STX_ZeroY() { MemoryWrite(GetZeroYAddr(), X()); }
|
|
||||||
void STX_Abs() { MemoryWrite(GetAbsAddr(), X()); }
|
|
||||||
|
|
||||||
void STY_Zero() { MemoryWrite(GetZeroAddr(), Y()); }
|
|
||||||
void STY_ZeroX() { MemoryWrite(GetZeroXAddr(), Y()); }
|
|
||||||
void STY_Abs() { MemoryWrite(GetAbsAddr(), Y()); }
|
|
||||||
|
|
||||||
void TAX() { SetX(A()); }
|
void TAX() { SetX(A()); }
|
||||||
void TAY() { SetY(A()); }
|
void TAY() { SetY(A()); }
|
||||||
@ -463,112 +497,23 @@ private:
|
|||||||
void PLA() { SetA(Pop()); }
|
void PLA() { SetA(Pop()); }
|
||||||
void PLP() { SetPS(Pop()); }
|
void PLP() { SetPS(Pop()); }
|
||||||
|
|
||||||
void AND_Imm() { AND(GetImmediate()); }
|
|
||||||
void AND_Zero() { AND(GetZero()); }
|
|
||||||
void AND_ZeroX() { AND(GetZeroX()); }
|
|
||||||
void AND_Abs() { AND(GetAbs()); }
|
|
||||||
void AND_AbsX() { AND(GetAbsX()); }
|
|
||||||
void AND_AbsY() { AND(GetAbsY()); }
|
|
||||||
void AND_IndX() { AND(GetIndX()); }
|
|
||||||
void AND_IndY() { AND(GetIndY()); }
|
|
||||||
|
|
||||||
void EOR_Imm() { XOR(GetImmediate()); }
|
|
||||||
void EOR_Zero() { XOR(GetZero()); }
|
|
||||||
void EOR_ZeroX() { XOR(GetZeroX()); }
|
|
||||||
void EOR_Abs() { XOR(GetAbs()); }
|
|
||||||
void EOR_AbsX() { XOR(GetAbsX()); }
|
|
||||||
void EOR_AbsY() { XOR(GetAbsY()); }
|
|
||||||
void EOR_IndX() { XOR(GetIndX()); }
|
|
||||||
void EOR_IndY() { XOR(GetIndY()); }
|
|
||||||
|
|
||||||
void ORA_Imm() { OR(GetImmediate()); }
|
|
||||||
void ORA_Zero() { OR(GetZero()); }
|
|
||||||
void ORA_ZeroX() { OR(GetZeroX()); }
|
|
||||||
void ORA_Abs() { OR(GetAbs()); }
|
|
||||||
void ORA_AbsX() { OR(GetAbsX()); }
|
|
||||||
void ORA_AbsY() { OR(GetAbsY()); }
|
|
||||||
void ORA_IndX() { OR(GetIndX()); }
|
|
||||||
void ORA_IndY() { OR(GetIndY()); }
|
|
||||||
|
|
||||||
void BIT_Zero() {
|
|
||||||
BIT(GetZero());
|
|
||||||
}
|
|
||||||
void BIT_Abs() {
|
|
||||||
BIT(GetAbs());
|
|
||||||
}
|
|
||||||
|
|
||||||
void ADC_Imm() { ADC(GetImmediate()); }
|
|
||||||
void ADC_Zero() { ADC(GetZero()); }
|
|
||||||
void ADC_ZeroX() { ADC(GetZeroX()); }
|
|
||||||
void ADC_Abs() { ADC(GetAbs()); }
|
|
||||||
void ADC_AbsX() { ADC(GetAbsX()); }
|
|
||||||
void ADC_AbsY() { ADC(GetAbsY()); }
|
|
||||||
void ADC_IndX() { ADC(GetIndX()); }
|
|
||||||
void ADC_IndY() { ADC(GetIndY()); }
|
|
||||||
|
|
||||||
void SBC_Imm() { SBC(GetImmediate()); }
|
|
||||||
void SBC_Zero() { SBC(GetZero()); }
|
|
||||||
void SBC_ZeroX() { SBC(GetZeroX()); }
|
|
||||||
void SBC_Abs() { SBC(GetAbs()); }
|
|
||||||
void SBC_AbsX() { SBC(GetAbsX()); }
|
|
||||||
void SBC_AbsY() { SBC(GetAbsY()); }
|
|
||||||
void SBC_IndX() { SBC(GetIndX()); }
|
|
||||||
void SBC_IndY() { SBC(GetIndY()); }
|
|
||||||
|
|
||||||
void CMP_Imm() { CPA(GetImmediate()); }
|
|
||||||
void CMP_Zero() { CPA(GetZero()); }
|
|
||||||
void CMP_ZeroX() { CPA(GetZeroX()); }
|
|
||||||
void CMP_Abs() { CPA(GetAbs()); }
|
|
||||||
void CMP_AbsX() { CPA(GetAbsX()); }
|
|
||||||
void CMP_AbsY() { CPA(GetAbsY()); }
|
|
||||||
void CMP_IndX() { CPA(GetIndX()); }
|
|
||||||
void CMP_IndY() { CPA(GetIndY()); }
|
|
||||||
|
|
||||||
void CPX_Imm() { CPX(GetImmediate()); }
|
|
||||||
void CPX_Zero() { CPX(GetZero()); }
|
|
||||||
void CPX_Abs() { CPX(GetAbs()); }
|
|
||||||
|
|
||||||
void CPY_Imm() { CPY(GetImmediate()); }
|
|
||||||
void CPY_Zero() { CPY(GetZero()); }
|
|
||||||
void CPY_Abs() { CPY(GetAbs()); }
|
|
||||||
|
|
||||||
void INC_Zero() { INC(GetZeroAddr()); }
|
|
||||||
void INC_ZeroX() { INC(GetZeroXAddr()); }
|
|
||||||
void INC_Abs() { INC(GetAbsAddr()); }
|
|
||||||
void INC_AbsX() { INC(GetAbsXAddr()); }
|
|
||||||
void INX() { SetX(X() + 1); }
|
void INX() { SetX(X() + 1); }
|
||||||
void INY() { SetY(Y() + 1); }
|
void INY() { SetY(Y() + 1); }
|
||||||
|
|
||||||
void DEC_Zero() { DEC(GetZeroAddr()); }
|
|
||||||
void DEC_ZeroX() { DEC(GetZeroXAddr()); }
|
|
||||||
void DEC_Abs() { DEC(GetAbsAddr()); }
|
|
||||||
void DEC_AbsX() { DEC(GetAbsXAddr()); }
|
|
||||||
void DEX() { SetX(X() - 1); }
|
void DEX() { SetX(X() - 1); }
|
||||||
void DEY() { SetY(Y() - 1); }
|
void DEY() { SetY(Y() - 1); }
|
||||||
|
|
||||||
void ASL_Acc() { SetA(ASL(A())); }
|
void ASL_Acc() { SetA(ASL(A())); }
|
||||||
void ASL_Zero() { ASLAddr(GetZeroAddr()); }
|
void ASL_Memory() { ASLAddr(); }
|
||||||
void ASL_ZeroX() { ASLAddr(GetZeroXAddr()); }
|
|
||||||
void ASL_Abs() { ASLAddr(GetAbsAddr()); }
|
|
||||||
void ASL_AbsX() { ASLAddr(GetAbsXAddr()); }
|
|
||||||
|
|
||||||
void LSR_Acc() { SetA(LSR(A())); }
|
void LSR_Acc() { SetA(LSR(A())); }
|
||||||
void LSR_Zero() { LSRAddr(GetZeroAddr()); }
|
void LSR_Memory() { LSRAddr(); }
|
||||||
void LSR_ZeroX() { LSRAddr(GetZeroXAddr()); }
|
|
||||||
void LSR_Abs() { LSRAddr(GetAbsAddr()); }
|
|
||||||
void LSR_AbsX() { LSRAddr(GetAbsXAddr()); }
|
|
||||||
|
|
||||||
void ROL_Acc() { SetA(ROL(A())); }
|
void ROL_Acc() { SetA(ROL(A())); }
|
||||||
void ROL_Zero() { ROLAddr(GetZeroAddr()); }
|
void ROL_Memory() { ROLAddr(); }
|
||||||
void ROL_ZeroX() { ROLAddr(GetZeroXAddr()); }
|
|
||||||
void ROL_Abs() { ROLAddr(GetAbsAddr()); }
|
|
||||||
void ROL_AbsX() { ROLAddr(GetAbsXAddr()); }
|
|
||||||
|
|
||||||
void ROR_Acc() { SetA(ROR(A())); }
|
void ROR_Acc() { SetA(ROR(A())); }
|
||||||
void ROR_Zero() { RORAddr(GetZeroAddr()); }
|
void ROR_Memory() { RORAddr(); }
|
||||||
void ROR_ZeroX() { RORAddr(GetZeroXAddr()); }
|
|
||||||
void ROR_Abs() { RORAddr(GetAbsAddr()); }
|
|
||||||
void ROR_AbsX() { RORAddr(GetAbsXAddr()); }
|
|
||||||
|
|
||||||
void JMP_Abs() {
|
void JMP_Abs() {
|
||||||
JMP(GetAbsAddr());
|
JMP(GetAbsAddr());
|
||||||
@ -663,18 +608,16 @@ private:
|
|||||||
SetPC(MemoryReadWord(CPU::IRQVector));
|
SetPC(MemoryReadWord(CPU::IRQVector));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
void NOP() {}
|
|
||||||
void NOP2() {
|
|
||||||
//Unofficial opcode, 2-byte NOP
|
|
||||||
ReadByte();
|
|
||||||
}
|
|
||||||
|
|
||||||
void RTI() {
|
void RTI() {
|
||||||
SetPS(Pop());
|
SetPS(Pop());
|
||||||
SetPC(PopWord());
|
SetPC(PopWord());
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void NOP() {
|
||||||
|
GetOperand();
|
||||||
|
}
|
||||||
|
|
||||||
#pragma endregion
|
#pragma endregion
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user