mirror of
https://github.com/libretro/Mesen.git
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226 lines
5.8 KiB
C++
226 lines
5.8 KiB
C++
#pragma once
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#include "stdafx.h"
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#include "IMemoryHandler.h"
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#include "CPU.h"
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#include "EmulationSettings.h"
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enum class FrameType
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{
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None = 0,
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QuarterFrame = 1,
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HalfFrame = 2,
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};
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class ApuFrameCounter : public IMemoryHandler, public Snapshotable
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{
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private:
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const int32_t _stepCyclesNtsc[2][6] = { { 7457, 14913, 22371, 29828, 29829, 29830},
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{ 7457, 14913, 22371, 29829, 37281, 37282} };
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const int32_t _stepCyclesPal[2][6] = { { 8313, 16627, 24939, 33252, 33253, 33254},
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{ 8313, 16627, 24939, 33253, 41565, 41566} };
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const FrameType _frameType[2][6] = { { FrameType::QuarterFrame, FrameType::HalfFrame, FrameType::QuarterFrame, FrameType::None, FrameType::HalfFrame, FrameType::None },
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{ FrameType::QuarterFrame, FrameType::HalfFrame, FrameType::QuarterFrame, FrameType::None, FrameType::HalfFrame, FrameType::None } };
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int32_t _stepCycles[2][6];
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NesModel _nesModel;
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int32_t _nextIrqCycle;
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int32_t _previousCycle;
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uint32_t _currentStep;
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uint32_t _stepMode; //0: 4-step mode, 1: 5-step mode
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bool _inhibitIRQ;
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uint8_t _blockFrameCounterTick;
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int16_t _newValue;
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int8_t _writeDelayCounter;
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void (*_callback)(FrameType);
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public:
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ApuFrameCounter(void (*frameCounterTickCallback)(FrameType))
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{
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_callback = frameCounterTickCallback;
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Reset(false);
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}
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void Reset(bool softReset)
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{
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_nextIrqCycle = 29828;
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_previousCycle = 0;
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//"After reset: APU mode in $4017 was unchanged", so we need to keep whatever value _stepMode has for soft resets
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if(!softReset) {
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_stepMode = 0;
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}
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_currentStep = 0;
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//"After reset or power-up, APU acts as if $4017 were written with $00 from 9 to 12 clocks before first instruction begins."
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//This is emulated in the CPU::Reset function
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//Reset acts as if $00 was written to $4017
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_newValue = _stepMode ? 0x80 : 0x00;
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_writeDelayCounter = 3;
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_inhibitIRQ = false;
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_blockFrameCounterTick = 0;
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}
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void StreamState(bool saving) override
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{
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Stream(_nextIrqCycle, _previousCycle, _currentStep, _stepMode, _inhibitIRQ, _nesModel, _blockFrameCounterTick, _writeDelayCounter, _newValue);
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if(!saving) {
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SetNesModel(_nesModel);
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}
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}
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void SetNesModel(NesModel model)
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{
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if(_nesModel != model) {
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_nesModel = model;
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switch(model) {
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case NesModel::NTSC:
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case NesModel::Dendy:
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memcpy(_stepCycles, _stepCyclesNtsc, sizeof(_stepCycles));
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break;
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case NesModel::PAL:
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memcpy(_stepCycles, _stepCyclesPal, sizeof(_stepCycles));
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break;
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}
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}
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}
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uint32_t Run(int32_t &cyclesToRun)
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{
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uint32_t cyclesRan;
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if(_previousCycle + cyclesToRun >= _stepCycles[_stepMode][_currentStep]) {
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if(!_inhibitIRQ && _stepMode == 0 && _currentStep >= 3) {
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//Set irq on the last 3 cycles for 4-step mode
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CPU::SetIRQSource(IRQSource::FrameCounter);
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_nextIrqCycle++;
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}
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FrameType type = _frameType[_stepMode][_currentStep];
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if(type != FrameType::None && !_blockFrameCounterTick) {
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_callback(type);
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//Do not allow writes to 4017 to clock the frame counter for the next cycle (i.e this odd cycle + the following even cycle)
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_blockFrameCounterTick = 2;
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}
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if(_stepCycles[_stepMode][_currentStep] < _previousCycle) {
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//This can happen when switching from PAL to NTSC, which can cause a freeze (endless loop in APU)
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cyclesRan = 0;
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} else {
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cyclesRan = _stepCycles[_stepMode][_currentStep] - _previousCycle;
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}
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cyclesToRun -= cyclesRan;
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_currentStep++;
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if(_currentStep == 6) {
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_currentStep = 0;
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_previousCycle = 0;
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if(_stepMode == 0 && !_inhibitIRQ) {
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_nextIrqCycle = 29828;
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}
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} else {
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_previousCycle += cyclesRan;
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}
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} else {
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cyclesRan = cyclesToRun;
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cyclesToRun = 0;
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_previousCycle += cyclesRan;
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}
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if(_newValue >= 0) {
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_writeDelayCounter--;
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if(_writeDelayCounter == 0) {
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//Apply new value after the appropriate number of cycles has elapsed
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_stepMode = ((_newValue & 0x80) == 0x80) ? 1 : 0;
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if(!_inhibitIRQ && _stepMode == 0) {
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_nextIrqCycle = 29828;
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} else {
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_nextIrqCycle = -1;
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}
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_writeDelayCounter = -1;
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_currentStep = 0;
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_previousCycle = 0;
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_newValue = -1;
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if(_stepMode && !_blockFrameCounterTick) {
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//"Writing to $4017 with bit 7 set will immediately generate a clock for both the quarter frame and the half frame units, regardless of what the sequencer is doing."
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_callback(FrameType::HalfFrame);
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_blockFrameCounterTick = 2;
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}
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}
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}
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if(_blockFrameCounterTick > 0) {
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_blockFrameCounterTick--;
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}
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return cyclesRan;
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}
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bool IrqPending(uint32_t cyclesToRun)
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{
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if(_newValue >= 0 || _blockFrameCounterTick > 0) {
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return true;
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}
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if(_previousCycle + (int32_t)cyclesToRun >= _stepCycles[_stepMode][_currentStep]) {
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return true;
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}
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if(_nextIrqCycle != -1) {
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if(_previousCycle + cyclesToRun >= (uint32_t)_nextIrqCycle) {
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return true;
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}
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}
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return false;
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}
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void GetMemoryRanges(MemoryRanges &ranges) override
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{
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ranges.AddHandler(MemoryOperation::Write, 0x4017);
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}
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uint8_t ReadRAM(uint16_t addr) override
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{
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return 0;
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}
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void WriteRAM(uint16_t addr, uint8_t value) override
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{
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APU::StaticRun();
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_newValue = value;
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//Reset sequence after $4017 is written to
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if(CPU::GetCycleCount() & 0x01) {
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//"If the write occurs during an APU cycle, the effects occur 3 CPU cycles after the $4017 write cycle"
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_writeDelayCounter = 3;
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} else {
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//"If the write occurs between APU cycles, the effects occur 4 CPU cycles after the write cycle. "
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_writeDelayCounter = 4;
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}
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_inhibitIRQ = (value & 0x40) == 0x40;
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if(_inhibitIRQ) {
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CPU::ClearIRQSource(IRQSource::FrameCounter);
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}
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}
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ApuFrameCounterState GetState()
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{
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ApuFrameCounterState state;
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state.IrqEnabled = !_inhibitIRQ;
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state.SequencePosition = _currentStep;
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state.FiveStepMode = _stepMode == 1;
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return state;
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}
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}; |