mirror of
https://github.com/libretro/Mesen.git
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226 lines
6.2 KiB
C++
226 lines
6.2 KiB
C++
#pragma once
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#include "stdafx.h"
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#include "CPU.h"
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#include "BaseMapper.h"
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class MMC1 : public BaseMapper
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{
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private:
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enum class MMC1Registers
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{
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Reg8000 = 0,
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RegA000 = 1,
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RegC000 = 2,
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RegE000 = 3
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};
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enum class PrgMode
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{
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_16k = 16,
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_32k = 32,
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};
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enum class ChrMode
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{
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_4k = 4,
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_8k = 8,
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};
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enum class SlotSelect
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{
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x8000 = 0x8000,
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xC000 = 0xC000,
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};
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uint8_t _writeBuffer = 0;
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uint8_t _shiftCount = 0;
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bool _wramDisable;
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ChrMode _chrMode;
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PrgMode _prgMode;
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SlotSelect _slotSelect;
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uint8_t _chrReg0;
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uint8_t _chrReg1;
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uint8_t _prgReg;
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int32_t _lastWriteCycle = -1;
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bool _forceWramOn;
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MMC1Registers _lastChrReg;
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private:
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bool HasResetFlag(uint8_t value)
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{
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return (value & 0x80) == 0x80;
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}
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void ResetBuffer()
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{
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_shiftCount = 0;
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_writeBuffer = 0;
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}
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bool IsBufferFull(uint8_t value)
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{
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if(HasResetFlag(value)) {
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//When 'r' is set:
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// - 'd' is ignored
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// - hidden temporary reg is reset (so that the next write is the "first" write)
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// - bits 2,3 of reg $8000 are set (16k PRG mode, $8000 swappable)
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// - other bits of $8000 (and other regs) are unchanged
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ResetBuffer();
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_state.Reg8000 |= 0x0C;
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return false;
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} else {
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_writeBuffer >>= 1;
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_writeBuffer |= ((value << 4) & 0x10);
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_shiftCount++;
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return _shiftCount == 5;
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}
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}
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protected:
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struct
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{
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uint8_t Reg8000;
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uint8_t RegA000;
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uint8_t RegC000;
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uint8_t RegE000;
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} _state;
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virtual void UpdateState()
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{
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switch(_state.Reg8000 & 0x03) {
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case 0: SetMirroringType(MirroringType::ScreenAOnly); break;
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case 1: SetMirroringType(MirroringType::ScreenBOnly); break;
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case 2: SetMirroringType(MirroringType::Vertical); break;
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case 3: SetMirroringType(MirroringType::Horizontal); break;
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}
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_wramDisable = (_state.RegE000 & 0x10) == 0x10;
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_slotSelect = ((_state.Reg8000 & 0x04) == 0x04) ? SlotSelect::x8000 : SlotSelect::xC000;
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_prgMode = ((_state.Reg8000 & 0x08) == 0x08) ? PrgMode::_16k : PrgMode::_32k;
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_chrMode = ((_state.Reg8000 & 0x10) == 0x10) ? ChrMode::_4k : ChrMode::_8k;
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_chrReg0 = _state.RegA000 & 0x1F;
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_chrReg1 = _state.RegC000 & 0x1F;
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_prgReg = _state.RegE000 & 0x0F;
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uint8_t extraReg = _lastChrReg == MMC1Registers::RegC000 && _chrMode == ChrMode::_4k ? _chrReg1 : _chrReg0;
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uint8_t prgBankSelect = 0;
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if(_prgSize == 0x80000) {
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//512kb carts use bit 7 of $A000/$C000 to select page
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//This is used for SUROM (Dragon Warrior 3/4, Dragon Quest 4)
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prgBankSelect = extraReg & 0x10;
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}
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if(_wramDisable && !_forceWramOn) {
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RemoveCpuMemoryMapping(0x6000, 0x7FFF);
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} else {
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if(_saveRamSize + _workRamSize > 0x4000) {
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//SXROM, 32kb of save ram
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SetCpuMemoryMapping(0x6000, 0x7FFF, (extraReg >> 2) & 0x03, HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam);
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} else if(_saveRamSize + _workRamSize > 0x2000) {
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if(_saveRamSize == 0x2000 && _workRamSize == 0x2000) {
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//SOROM, half of the 16kb ram is battery backed
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SetCpuMemoryMapping(0x6000, 0x7FFF, 0, (extraReg >> 3) & 0x01 ? PrgMemoryType::WorkRam : PrgMemoryType::SaveRam);
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} else {
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//Unknown, shouldn't happen
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SetCpuMemoryMapping(0x6000, 0x7FFF, (extraReg >> 2) & 0x01, HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam);
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}
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} else {
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//Everything else - 8kb of work or save ram
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SetCpuMemoryMapping(0x6000, 0x7FFF, 0, HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam);
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}
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}
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if(_subMapperID == 5) {
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//SubMapper 5
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//"001: 5 Fixed PRG SEROM, SHROM, SH1ROM use a fixed 32k PRG ROM with no banking support.
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SelectPrgPage2x(0, 0);
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} else {
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if(_prgMode == PrgMode::_32k) {
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SelectPrgPage2x(0, (_prgReg & 0xFE) | prgBankSelect);
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} else if(_prgMode == PrgMode::_16k) {
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if(_slotSelect == SlotSelect::x8000) {
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SelectPRGPage(0, _prgReg | prgBankSelect);
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SelectPRGPage(1, 0x0F | prgBankSelect);
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} else if(_slotSelect == SlotSelect::xC000) {
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SelectPRGPage(0, 0 | prgBankSelect);
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SelectPRGPage(1, _prgReg | prgBankSelect);
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}
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}
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}
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if(_chrMode == ChrMode::_8k) {
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SelectCHRPage(0, _chrReg0 & 0x1E);
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SelectCHRPage(1, (_chrReg0 & 0x1E) + 1);
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} else if(_chrMode == ChrMode::_4k) {
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SelectCHRPage(0, _chrReg0);
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SelectCHRPage(1, _chrReg1);
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}
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}
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virtual void StreamState(bool saving) override
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{
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BaseMapper::StreamState(saving);
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Stream(_state.Reg8000, _state.RegA000, _state.RegC000, _state.RegE000, _writeBuffer, _shiftCount, _lastWriteCycle, _lastChrReg);
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if(!saving) {
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UpdateState();
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}
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}
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virtual uint16_t GetPRGPageSize() override { return 0x4000; }
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virtual uint16_t GetCHRPageSize() override { return 0x1000; }
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virtual void InitMapper() override
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{
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_state.Reg8000 = 0x0C; //On powerup: bits 2,3 of $8000 are set (this ensures the $8000 is bank 0, and $C000 is the last bank - needed for SEROM/SHROM/SH1ROM which do no support banking)
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_state.RegA000 = 0x00;
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_state.RegC000 = 0x00;
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_state.RegE000 = (_databaseInfo.Board.find("MMC1B") != string::npos ? 0x10 : 0x00); //WRAM Disable: enabled by default for MMC1B
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//"MMC1A: PRG RAM is always enabled" - Normally these roms should be classified as mapper 155
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_forceWramOn = (_databaseInfo.Board.compare("MMC1A") == 0);
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_lastChrReg = MMC1Registers::RegA000;
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UpdateState();
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}
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virtual void WriteRegister(uint16_t addr, uint8_t value) override
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{
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int32_t currentCycle = CPU::GetCycleCount();
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//Ignore write if within 2 cycles of another write (i.e the real write after a dummy write)
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if(abs(currentCycle - _lastWriteCycle) >= 2) {
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if(IsBufferFull(value)) {
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switch((MMC1Registers)((addr & 0x6000) >> 13)) {
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case MMC1Registers::Reg8000: _state.Reg8000 = _writeBuffer; break;
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case MMC1Registers::RegA000:
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_lastChrReg = MMC1Registers::RegA000;
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_state.RegA000 = _writeBuffer;
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break;
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case MMC1Registers::RegC000:
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_lastChrReg = MMC1Registers::RegC000;
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_state.RegC000 = _writeBuffer;
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break;
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case MMC1Registers::RegE000: _state.RegE000 = _writeBuffer; break;
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}
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UpdateState();
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//Reset buffer after writing 5 bits
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ResetBuffer();
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}
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}
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_lastWriteCycle = currentCycle;
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}
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};
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