mirror of
https://github.com/libretro/Mesen.git
synced 2024-11-27 11:00:50 +00:00
227 lines
9.0 KiB
C++
227 lines
9.0 KiB
C++
#include "stdafx.h"
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#include "Disassembler.h"
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#include "DisassemblyInfo.h"
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#include "BaseMapper.h"
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Disassembler::Disassembler(uint8_t* internalRam, uint8_t* prgRom, uint32_t prgSize, uint8_t* prgRam, uint32_t prgRamSize)
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{
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_internalRam = internalRam;
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_prgRom = prgRom;
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_prgRam = prgRam;
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_prgSize = prgSize;
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for(uint32_t i = 0; i < prgSize; i++) {
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_disassembleCache.push_back(shared_ptr<DisassemblyInfo>(nullptr));
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}
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for(uint32_t i = 0; i < prgRamSize; i++) {
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_disassembleRamCache.push_back(shared_ptr<DisassemblyInfo>(nullptr));
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}
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for(uint32_t i = 0; i < 0x800; i++) {
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_disassembleMemoryCache.push_back(shared_ptr<DisassemblyInfo>(nullptr));
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}
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string opName[256] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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"BRK", "ORA", "", "SLO*", "NOP", "ORA", "ASL", "SLO*", "PHP", "ORA", "ASL", "AAC*", "NOP", "ORA", "ASL", "SLO*", //0
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"BPL", "ORA", "", "SLO*", "NOP", "ORA", "ASL", "SLO*", "CLC", "ORA", "NOP*", "SLO*", "NOP", "ORA", "ASL", "SLO*", //1
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"JSR", "AND", "", "RLA*", "BIT", "AND", "ROL", "RLA*", "PLP", "AND", "ROL", "AAC*", "BIT", "AND", "ROL", "RLA*", //2
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"BMI", "AND", "", "RLA*", "NOP", "AND", "ROL", "RLA*", "SEC", "AND", "NOP*", "RLA*", "NOP", "AND", "ROL", "RLA*", //3
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"RTI", "EOR", "", "SRE*", "NOP", "EOR", "LSR", "SRE*", "PHA", "EOR", "LSR", "ASR*", "JMP", "EOR", "LSR", "SRE*", //4
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"BVC", "EOR", "", "SRE*", "NOP", "EOR", "LSR", "SRE*", "CLI", "EOR", "NOP*", "SRE*", "NOP", "EOR", "LSR", "SRE*", //5
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"RTS", "ADC", "", "RRA*", "NOP", "ADC", "ROR", "RRA*", "PLA", "ADC", "ROR", "ARR*", "JMP", "ADC", "ROR", "RRA*", //6
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"BVS", "ADC", "", "RRA*", "NOP", "ADC", "ROR", "RRA*", "SEI", "ADC", "NOP*", "RRA*", "NOP", "ADC", "ROR", "RRA*", //7
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"NOP", "STA", "NOP", "SAX*", "STY", "STA", "STX", "SAX*", "DEY", "NOP", "TXA", "", "STY", "STA", "STX", "SAX*", //8
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"BCC", "STA", "", "AXA*", "STY", "STA", "STX", "SAX*", "TYA", "STA", "TXS", "TAS*", "SYA*", "STA", "SXA", "AXA*", //9
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"LDY", "LDA", "LDX", "LAX*", "LDY", "LDA", "LDX", "LAX*", "TAY", "LDA", "TAX", "ATX*", "LDY", "LDA", "LDX", "LAX*", //A
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"BCS", "LDA", "", "LAX*", "LDY", "LDA", "LDX", "LAX*", "CLV", "LDA", "TSX", "LAS*", "LDY", "LDA", "LDX", "LAX*", //B
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"CPY", "CPA", "NOP", "DCP*", "CPY", "CPA", "DEC", "DCP*", "INY", "CPA", "DEX", "AXS*", "CPY", "CPA", "DEC", "DCP*", //C
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"BNE", "CPA", "", "DCP*", "NOP", "CPA", "DEC", "DCP*", "CLD", "CPA", "NOP*", "DCP*", "NOP", "CPA", "DEC", "DCP*", //D
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"CPX", "SBC", "NOP", "ISB*", "CPX", "SBC", "INC", "ISB*", "INX", "SBC", "NOP", "SBC*", "CPX", "SBC", "INC", "ISB*", //E
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"BEQ", "SBC", "", "ISB*", "NOP", "SBC", "INC", "ISB*", "SED", "SBC", "NOP*", "ISB*", "NOP", "SBC", "INC", "ISB*" //F
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};
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AddrMode opMode[256] = {
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Imp, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Acc, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Abs, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Acc, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Imp, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Acc, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Imp, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Acc, Imm, Ind, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndYW, None, IndY, ZeroX, ZeroX, ZeroY, ZeroY, Imp, AbsYW, Imp, AbsY, AbsXW, AbsXW, AbsYW, AbsY,
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndY, ZeroX, ZeroX, ZeroY, ZeroY, Imp, AbsY, Imp, AbsY, AbsX, AbsX, AbsY, AbsY,
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs,
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW,
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};
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for(int i = 0; i < 256; i++) {
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DisassemblyInfo::OPName[i] = opName[i];
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DisassemblyInfo::OPMode[i] = opMode[i];
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switch(DisassemblyInfo::OPMode[i]) {
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case AddrMode::Abs:
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case AddrMode::AbsX:
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case AddrMode::AbsXW:
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case AddrMode::AbsY:
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case AddrMode::AbsYW:
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case AddrMode::Ind:
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DisassemblyInfo::OPSize[i] = 3;
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break;
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case AddrMode::Imm:
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case AddrMode::IndX:
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case AddrMode::IndY:
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case AddrMode::IndYW:
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case AddrMode::Rel:
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case AddrMode::Zero:
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case AddrMode::ZeroX:
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case AddrMode::ZeroY:
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DisassemblyInfo::OPSize[i] = 2;
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break;
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default:
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DisassemblyInfo::OPSize[i] = 1;
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break;
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}
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}
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}
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Disassembler::~Disassembler()
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{
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}
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uint32_t Disassembler::BuildCache(int32_t absoluteAddr, int32_t absoluteRamAddr, uint16_t memoryAddr, bool isSubEntryPoint)
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{
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if(memoryAddr < 0x2000) {
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memoryAddr = memoryAddr & 0x7FF;
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if(!_disassembleMemoryCache[memoryAddr]) {
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shared_ptr<DisassemblyInfo> disInfo(new DisassemblyInfo(&_internalRam[memoryAddr], isSubEntryPoint));
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_disassembleMemoryCache[memoryAddr] = disInfo;
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memoryAddr += disInfo->GetSize();
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} else if(isSubEntryPoint) {
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_disassembleMemoryCache[memoryAddr]->SetSubEntryPoint();
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}
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return memoryAddr;
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} else {
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vector<shared_ptr<DisassemblyInfo>> &cache = absoluteRamAddr >= 0 ? _disassembleRamCache : _disassembleCache;
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uint8_t *source = absoluteRamAddr >= 0 ? _prgRam : _prgRom;
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if(absoluteRamAddr >= 0) {
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absoluteAddr = absoluteRamAddr;
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}
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if(!cache[absoluteAddr]) {
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while(absoluteAddr < (int32_t)_prgSize && !cache[absoluteAddr]) {
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shared_ptr<DisassemblyInfo> disInfo(new DisassemblyInfo(&source[absoluteAddr], isSubEntryPoint));
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isSubEntryPoint = false;
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cache[absoluteAddr] = disInfo;
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uint8_t opCode = source[absoluteAddr];
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absoluteAddr += disInfo->GetSize();
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if(opCode == 0x10 || opCode == 0x20 || opCode == 0x30 || opCode == 0x40 || opCode == 0x50 || opCode == 0x60 || opCode == 0x70 || opCode == 0x90 || opCode == 0xB0 || opCode == 0xD0 || opCode == 0xF0 || opCode == 0x4C || opCode == 0x6C) {
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//Hit a jump/return instruction, can't assume that what follows is actual code, stop disassembling
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break;
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}
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}
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} else {
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if(isSubEntryPoint) {
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cache[absoluteAddr]->SetSubEntryPoint();
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}
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absoluteAddr += cache[absoluteAddr]->GetSize();
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}
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return absoluteAddr;
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}
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}
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void Disassembler::InvalidateCache(uint16_t memoryAddr, int32_t absoluteRamAddr)
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{
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uint32_t addr;
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vector<shared_ptr<DisassemblyInfo>> *cache;
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if(memoryAddr < 0x2000) {
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addr = memoryAddr & 0x7FF;
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cache = &_disassembleMemoryCache;
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} else {
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addr = absoluteRamAddr;
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cache = &_disassembleRamCache;
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}
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if(addr >= 0) {
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for(int i = 1; i <= 2; i++) {
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int offsetAddr = (int)addr - i;
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if(offsetAddr >= 0) {
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if((*cache)[offsetAddr] != nullptr) {
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if((*cache)[offsetAddr]->GetSize() >= (uint32_t)i + 1) {
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//Invalidate any instruction that overlapped this address
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(*cache)[offsetAddr] = nullptr;
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}
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}
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}
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}
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(*cache)[addr] = nullptr;
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}
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}
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string Disassembler::GetCode(uint32_t startAddr, uint32_t endAddr, uint16_t memoryAddr, PrgMemoryType memoryType)
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{
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std::ostringstream output;
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vector<shared_ptr<DisassemblyInfo>> *cache;
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uint8_t *source;
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uint32_t mask = 0xFFFFFFFF;
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if(memoryAddr < 0x2000) {
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cache = &_disassembleMemoryCache;
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source = _internalRam;
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mask = 0x7FF;
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} else if(memoryType == PrgMemoryType::WorkRam) {
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cache = &_disassembleRamCache;
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source = _prgRam;
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} else {
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cache = &_disassembleCache;
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source = _prgRom;
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}
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uint32_t addr = startAddr;
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uint32_t byteCount = 0;
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while(addr <= endAddr) {
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shared_ptr<DisassemblyInfo> info;
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if(info = (*cache)[addr&mask]) {
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if(byteCount > 0) {
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output << "\n";
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byteCount = 0;
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}
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output << std::hex << std::uppercase << memoryAddr << ":" << addr << ":" << info->ToString(memoryAddr) << "\n";
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addr += info->GetSize();
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memoryAddr += info->GetSize();
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} else {
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if(byteCount >= 8) {
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output << "\n";
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byteCount = 0;
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}
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if(byteCount == 0) {
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output << std::hex << std::uppercase << memoryAddr << ":" << addr << "::" << ".db";
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}
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output << std::hex << " $" << std::setfill('0') << std::setw(2) << (short)source[addr];
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byteCount++;
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addr++;
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memoryAddr++;
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}
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}
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output << "\n";
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return output.str();
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}
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shared_ptr<DisassemblyInfo> Disassembler::GetDisassemblyInfo(int32_t absoluteAddress, int32_t absoluteRamAddress, uint16_t memoryAddress)
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{
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if(memoryAddress < 0x2000) {
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return _disassembleMemoryCache[memoryAddress & 0x7FF];
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} else if(absoluteAddress >= 0) {
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return _disassembleCache[absoluteAddress];
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} else if(absoluteRamAddress >= 0) {
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return _disassembleRamCache[absoluteRamAddress];
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}
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return nullptr;
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} |