mirror of
https://github.com/libretro/Mesen.git
synced 2024-11-27 11:00:50 +00:00
249 lines
11 KiB
C++
249 lines
11 KiB
C++
#include "stdafx.h"
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#include "CPU.h"
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#include "PPU.h"
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#include "APU.h"
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#include "DeltaModulationChannel.h"
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#include "TraceLogger.h"
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#include "Debugger.h"
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#include "NsfMapper.h"
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CPU* CPU::Instance = nullptr;
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CPU::CPU(MemoryManager *memoryManager) : _memoryManager(memoryManager)
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{
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CPU::Instance = this;
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Func opTable[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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&CPU::BRK, &CPU::ORA, &CPU::HLT, &CPU::SLO, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, &CPU::SLO, &CPU::PHP, &CPU::ORA, &CPU::ASL_Acc, &CPU::AAC, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, &CPU::SLO, //0
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&CPU::BPL, &CPU::ORA, &CPU::HLT, &CPU::SLO, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, &CPU::SLO, &CPU::CLC, &CPU::ORA, &CPU::NOP, &CPU::SLO, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, &CPU::SLO, //1
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&CPU::JSR, &CPU::AND, &CPU::HLT, &CPU::RLA, &CPU::BIT, &CPU::AND, &CPU::ROL_Memory, &CPU::RLA, &CPU::PLP, &CPU::AND, &CPU::ROL_Acc, &CPU::AAC, &CPU::BIT, &CPU::AND, &CPU::ROL_Memory, &CPU::RLA, //2
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&CPU::BMI, &CPU::AND, &CPU::HLT, &CPU::RLA, &CPU::NOP, &CPU::AND, &CPU::ROL_Memory, &CPU::RLA, &CPU::SEC, &CPU::AND, &CPU::NOP, &CPU::RLA, &CPU::NOP, &CPU::AND, &CPU::ROL_Memory, &CPU::RLA, //3
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&CPU::RTI, &CPU::EOR, &CPU::HLT, &CPU::SRE, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, &CPU::SRE, &CPU::PHA, &CPU::EOR, &CPU::LSR_Acc, &CPU::ASR, &CPU::JMP_Abs, &CPU::EOR, &CPU::LSR_Memory, &CPU::SRE, //4
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&CPU::BVC, &CPU::EOR, &CPU::HLT, &CPU::SRE, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, &CPU::SRE, &CPU::CLI, &CPU::EOR, &CPU::NOP, &CPU::SRE, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, &CPU::SRE, //5
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&CPU::RTS, &CPU::ADC, &CPU::HLT, &CPU::RRA, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, &CPU::RRA, &CPU::PLA, &CPU::ADC, &CPU::ROR_Acc, &CPU::ARR, &CPU::JMP_Ind, &CPU::ADC, &CPU::ROR_Memory, &CPU::RRA, //6
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&CPU::BVS, &CPU::ADC, &CPU::HLT, &CPU::RRA, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, &CPU::RRA, &CPU::SEI, &CPU::ADC, &CPU::NOP, &CPU::RRA, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, &CPU::RRA, //7
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&CPU::NOP, &CPU::STA, &CPU::NOP, &CPU::SAX, &CPU::STY, &CPU::STA, &CPU::STX, &CPU::SAX, &CPU::DEY, &CPU::NOP, &CPU::TXA, &CPU::UNK, &CPU::STY, &CPU::STA, &CPU::STX, &CPU::SAX, //8
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&CPU::BCC, &CPU::STA, &CPU::HLT, &CPU::AXA, &CPU::STY, &CPU::STA, &CPU::STX, &CPU::SAX, &CPU::TYA, &CPU::STA, &CPU::TXS, &CPU::TAS, &CPU::SYA, &CPU::STA, &CPU::SXA, &CPU::AXA, //9
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&CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, &CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, &CPU::TAY, &CPU::LDA, &CPU::TAX, &CPU::ATX, &CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, //A
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&CPU::BCS, &CPU::LDA, &CPU::HLT, &CPU::LAX, &CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, &CPU::CLV, &CPU::LDA, &CPU::TSX, &CPU::LAS, &CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, //B
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&CPU::CPY, &CPU::CPA, &CPU::NOP, &CPU::DCP, &CPU::CPY, &CPU::CPA, &CPU::DEC, &CPU::DCP, &CPU::INY, &CPU::CPA, &CPU::DEX, &CPU::AXS, &CPU::CPY, &CPU::CPA, &CPU::DEC, &CPU::DCP, //C
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&CPU::BNE, &CPU::CPA, &CPU::HLT, &CPU::DCP, &CPU::NOP, &CPU::CPA, &CPU::DEC, &CPU::DCP, &CPU::CLD, &CPU::CPA, &CPU::NOP, &CPU::DCP, &CPU::NOP, &CPU::CPA, &CPU::DEC, &CPU::DCP, //D
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&CPU::CPX, &CPU::SBC, &CPU::NOP, &CPU::ISB, &CPU::CPX, &CPU::SBC, &CPU::INC, &CPU::ISB, &CPU::INX, &CPU::SBC, &CPU::NOP, &CPU::SBC, &CPU::CPX, &CPU::SBC, &CPU::INC, &CPU::ISB, //E
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&CPU::BEQ, &CPU::SBC, &CPU::HLT, &CPU::ISB, &CPU::NOP, &CPU::SBC, &CPU::INC, &CPU::ISB, &CPU::SED, &CPU::SBC, &CPU::NOP, &CPU::ISB, &CPU::NOP, &CPU::SBC, &CPU::INC, &CPU::ISB //F
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};
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AddrMode addrMode[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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Imp, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs, //0
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW, //1
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Abs, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs, //2
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW, //3
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Imp, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs, //4
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW, //5
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Imp, IndX, None, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs, //6
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW, //7
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs, //8
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Rel, IndYW, None, IndYW, ZeroX, ZeroX, ZeroY, ZeroY, Imp, AbsYW, Imp, AbsYW, AbsXW, AbsXW, AbsYW, AbsYW, //9
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs, //A
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Rel, IndY, None, IndY, ZeroX, ZeroX, ZeroY, ZeroY, Imp, AbsY, Imp, AbsY, AbsX, AbsX, AbsY, AbsY, //B
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs, //C
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW, //D
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Imm, IndX, Imm, IndX, Zero, Zero, Zero, Zero, Imp, Imm, Imp, Imm, Abs, Abs, Abs, Abs, //E
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Rel, IndY, None, IndYW, ZeroX, ZeroX, ZeroX, ZeroX, Imp, AbsY, Imp, AbsYW, AbsX, AbsX, AbsXW, AbsXW, //F
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};
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memcpy(_opTable, opTable, sizeof(opTable));
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memcpy(_addrMode, addrMode, sizeof(addrMode));
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}
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void CPU::Reset(bool softReset)
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{
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_state.NMIFlag = false;
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_state.IRQFlag = 0;
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_cycleCount = -1;
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_spriteDmaTransfer = false;
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_spriteDmaCounter = 0;
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_dmcCounter = -1;
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_dmcDmaRunning = false;
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//Used by NSF code to disable Frame Counter & DMC interrupts
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_irqMask = 0xFF;
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//Use _memoryManager->Read() directly to prevent clocking the PPU/APU when setting PC at reset
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_state.PC = _memoryManager->Read(CPU::ResetVector) | _memoryManager->Read(CPU::ResetVector+1) << 8;
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if(softReset) {
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SetFlags(PSFlags::Interrupt);
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_state.SP -= 0x03;
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} else {
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_state.A = 0;
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_state.SP = 0xFD;
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_state.X = 0;
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_state.Y = 0;
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_state.PS = PSFlags::Reserved | PSFlags::Interrupt;
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_runIrq = false;
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}
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}
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void CPU::Exec()
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{
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uint8_t opCode = GetOPCode();
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_instAddrMode = _addrMode[opCode];
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_operand = FetchOperand();
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(this->*_opTable[opCode])();
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if(_prevRunIrq) {
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IRQ();
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}
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}
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uint16_t CPU::FetchOperand()
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{
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switch(_instAddrMode) {
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case AddrMode::Acc:
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case AddrMode::Imp: DummyRead(); return 0;
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case AddrMode::Imm:
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case AddrMode::Rel: return GetImmediate();
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case AddrMode::Zero: return GetZeroAddr();
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case AddrMode::ZeroX: return GetZeroXAddr();
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case AddrMode::ZeroY: return GetZeroYAddr();
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case AddrMode::Ind: return GetIndAddr();
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case AddrMode::IndX: return GetIndXAddr();
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case AddrMode::IndY: return GetIndYAddr(false);
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case AddrMode::IndYW: return GetIndYAddr(true);
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case AddrMode::Abs: return GetAbsAddr();
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case AddrMode::AbsX: return GetAbsXAddr(false);
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case AddrMode::AbsXW: return GetAbsXAddr(true);
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case AddrMode::AbsY: return GetAbsYAddr(false);
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case AddrMode::AbsYW: return GetAbsYAddr(true);
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default: break;
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}
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Debugger::BreakIfDebugging();
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if(NsfMapper::GetInstance()) {
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//Don't stop emulation on CPU crash when playing NSFs, reset cpu instead
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Reset(false);
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return 0;
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} else {
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throw std::runtime_error("Invalid OP code - CPU crashed");
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}
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}
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void CPU::IncCycleCount()
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{
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_cycleCount++;
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_memoryManager->ProcessCpuClock();
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if(_dmcDmaRunning) {
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//CPU is being stalled by the DMC's DMA transfer
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_dmcCounter--;
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if(_dmcCounter == 0) {
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//Update the DMC buffer when the stall period is completed
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_dmcDmaRunning = false;
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DeltaModulationChannel::SetReadBuffer();
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TraceLogger::LogStatic("DMC DMA End");
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}
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}
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PPU::ExecStatic();
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APU::ExecStatic();
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if(!_spriteDmaTransfer && !_dmcDmaRunning) {
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//IRQ flags are ignored during Sprite DMA - fixes irq_and_dma
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//"it's really the status of the interrupt lines at the end of the second-to-last cycle that matters."
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//Keep the irq lines values from the previous cycle. The before-to-last cycle's values will be used
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_prevRunIrq = _runIrq;
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_runIrq = _state.NMIFlag || ((_state.IRQFlag & _irqMask) > 0 && !CheckFlag(PSFlags::Interrupt));
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}
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}
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void CPU::RunDMATransfer(uint8_t* spriteRAM, uint8_t offsetValue)
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{
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TraceLogger::LogStatic("Sprite DMA Start");
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Instance->_spriteDmaTransfer = true;
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//"The CPU is suspended during the transfer, which will take 513 or 514 cycles after the $4014 write tick."
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//"(1 dummy read cycle while waiting for writes to complete, +1 if on an odd CPU cycle, then 256 alternating read/write cycles.)"
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if(Instance->_cycleCount % 2 != 0) {
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Instance->DummyRead();
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}
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Instance->DummyRead();
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Instance->_spriteDmaCounter = 256;
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//DMA transfer starts at SpriteRamAddr and wraps around
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for(int i = 0; i < 0x100; i++) {
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//Read value
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uint8_t readValue = Instance->MemoryRead(offsetValue * 0x100 + i);
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//Write to sprite ram via $2004 ("DMA is implemented in the 2A03/7 chip and works by repeatedly writing to OAMDATA")
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Instance->MemoryWrite(0x2004, readValue);
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Instance->_spriteDmaCounter--;
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}
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Instance->_spriteDmaTransfer = false;
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TraceLogger::LogStatic("Sprite DMA End");
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}
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void CPU::StartDmcTransfer()
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{
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//"DMC DMA adds 4 cycles normally, 2 if it lands on the $4014 write or during OAM DMA"
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//3 cycles if it lands on the last write cycle of any instruction
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TraceLogger::LogStatic("DMC DMA Start");
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Instance->_dmcDmaRunning = true;
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if(Instance->_spriteDmaTransfer) {
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if(Instance->_spriteDmaCounter == 2) {
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Instance->_dmcCounter = 1;
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} else if(Instance->_spriteDmaCounter == 1) {
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Instance->_dmcCounter = 3;
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} else {
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Instance->_dmcCounter = 2;
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}
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} else {
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if(Instance->_cpuWrite) {
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if(Instance->_writeAddr == 0x4014) {
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Instance->_dmcCounter = 2;
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} else {
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Instance->_dmcCounter = 3;
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}
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} else {
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Instance->_dmcCounter = 4;
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}
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}
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}
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uint32_t CPU::GetClockRate(NesModel model)
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{
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switch(model) {
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default:
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case NesModel::NTSC: return CPU::ClockRateNtsc; break;
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case NesModel::PAL: return CPU::ClockRatePal; break;
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case NesModel::Dendy: return CPU::ClockRateDendy; break;
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}
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}
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void CPU::StreamState(bool saving)
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{
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uint32_t overclockRate = EmulationSettings::GetOverclockRateSetting();
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bool overclockAdjustApu = EmulationSettings::GetOverclockAdjustApu();
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uint32_t extraScanlinesBeforeNmi = EmulationSettings::GetPpuExtraScanlinesBeforeNmi();
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uint32_t extraScanlinesAfterNmi = EmulationSettings::GetPpuExtraScanlinesAfterNmi();
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Stream(_state.PC, _state.SP, _state.PS, _state.A, _state.X, _state.Y, _cycleCount, _state.NMIFlag,
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_state.IRQFlag, _dmcCounter, _dmcDmaRunning, _spriteDmaCounter, _spriteDmaTransfer,
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overclockRate, overclockAdjustApu, extraScanlinesBeforeNmi, extraScanlinesBeforeNmi);
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if(!saving) {
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EmulationSettings::SetOverclockRate(overclockRate, overclockAdjustApu);
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EmulationSettings::SetPpuNmiConfig(extraScanlinesBeforeNmi, extraScanlinesAfterNmi);
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}
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} |