mirror of
https://github.com/libretro/Mesen.git
synced 2024-11-23 17:19:39 +00:00
624 lines
23 KiB
C++
624 lines
23 KiB
C++
#include "stdafx.h"
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#include <algorithm>
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#include "Disassembler.h"
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#include "DisassemblyInfo.h"
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#include "BaseMapper.h"
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#include "MemoryManager.h"
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#include "CPU.h"
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#include "LabelManager.h"
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#include "../Utilities/HexUtilities.h"
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#include "../Utilities/StringUtilities.h"
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#include "Debugger.h"
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Disassembler::Disassembler(MemoryManager* memoryManager, BaseMapper* mapper, Debugger* debugger)
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{
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_debugger = debugger;
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_memoryManager = memoryManager;
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_mapper = mapper;
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BuildOpCodeTables(false);
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}
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Disassembler::~Disassembler()
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{
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}
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void Disassembler::Reset()
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{
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_disassembleCache.clear();
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_disassembleWorkRamCache.clear();
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_disassembleSaveRamCache.clear();
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_disassembleMemoryCache.clear();
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_disassembleCache.insert(_disassembleCache.end(), _mapper->GetMemorySize(DebugMemoryType::PrgRom), shared_ptr<DisassemblyInfo>(nullptr));
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_disassembleWorkRamCache.insert(_disassembleWorkRamCache.end(), _mapper->GetMemorySize(DebugMemoryType::WorkRam), shared_ptr<DisassemblyInfo>(nullptr));
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_disassembleSaveRamCache.insert(_disassembleSaveRamCache.end(), _mapper->GetMemorySize(DebugMemoryType::SaveRam), shared_ptr<DisassemblyInfo>(nullptr));
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_disassembleMemoryCache.insert(_disassembleMemoryCache.end(), 0x800, shared_ptr<DisassemblyInfo>(nullptr));
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}
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void Disassembler::BuildOpCodeTables(bool useLowerCase)
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{
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string opName[256] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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"BRK", "ORA", "STP", "SLO", "NOP", "ORA", "ASL", "SLO", "PHP", "ORA", "ASL", "ANC", "NOP", "ORA", "ASL", "SLO", //0
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"BPL", "ORA", "STP", "SLO", "NOP", "ORA", "ASL", "SLO", "CLC", "ORA", "NOP", "SLO", "NOP", "ORA", "ASL", "SLO", //1
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"JSR", "AND", "STP", "RLA", "BIT", "AND", "ROL", "RLA", "PLP", "AND", "ROL", "ANC", "BIT", "AND", "ROL", "RLA", //2
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"BMI", "AND", "STP", "RLA", "NOP", "AND", "ROL", "RLA", "SEC", "AND", "NOP", "RLA", "NOP", "AND", "ROL", "RLA", //3
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"RTI", "EOR", "STP", "SRE", "NOP", "EOR", "LSR", "SRE", "PHA", "EOR", "LSR", "ALR", "JMP", "EOR", "LSR", "SRE", //4
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"BVC", "EOR", "STP", "SRE", "NOP", "EOR", "LSR", "SRE", "CLI", "EOR", "NOP", "SRE", "NOP", "EOR", "LSR", "SRE", //5
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"RTS", "ADC", "STP", "RRA", "NOP", "ADC", "ROR", "RRA", "PLA", "ADC", "ROR", "ARR", "JMP", "ADC", "ROR", "RRA", //6
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"BVS", "ADC", "STP", "RRA", "NOP", "ADC", "ROR", "RRA", "SEI", "ADC", "NOP", "RRA", "NOP", "ADC", "ROR", "RRA", //7
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"NOP", "STA", "NOP", "SAX", "STY", "STA", "STX", "SAX", "DEY", "NOP", "TXA", "XAA", "STY", "STA", "STX", "SAX", //8
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"BCC", "STA", "STP", "AHX", "STY", "STA", "STX", "SAX", "TYA", "STA", "TXS", "TAS", "SHY", "STA", "SHX", "AXA", //9
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"LDY", "LDA", "LDX", "LAX", "LDY", "LDA", "LDX", "LAX", "TAY", "LDA", "TAX", "LAX", "LDY", "LDA", "LDX", "LAX", //A
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"BCS", "LDA", "STP", "LAX", "LDY", "LDA", "LDX", "LAX", "CLV", "LDA", "TSX", "LAS", "LDY", "LDA", "LDX", "LAX", //B
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"CPY", "CMP", "NOP", "DCP", "CPY", "CMP", "DEC", "DCP", "INY", "CMP", "DEX", "AXS", "CPY", "CMP", "DEC", "DCP", //C
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"BNE", "CMP", "STP", "DCP", "NOP", "CMP", "DEC", "DCP", "CLD", "CMP", "NOP", "DCP", "NOP", "CMP", "DEC", "DCP", //D
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"CPX", "SBC", "NOP", "ISC", "CPX", "SBC", "INC", "ISC", "INX", "SBC", "NOP", "SBC", "CPX", "SBC", "INC", "ISC", //E
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"BEQ", "SBC", "STP", "ISC", "NOP", "SBC", "INC", "ISC", "SED", "SBC", "NOP", "ISC", "NOP", "SBC", "INC", "ISC" //F
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};
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bool unofficial[256] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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false,false,true, true, true, false,false,true, false,false,false,true, true, false,false,true, //0
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false,false,true, true, true, false,false,true, false,false,true, true, true, false,false,true, //1
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false,false,true, true, false,false,false,true, false,false,false,true, false,false,false,true, //2
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false,false,true, true, true, false,false,true, false,false,true, true, true, false,false,true, //3
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false,false,true, true, true, false,false,true, false,false,false,true, false,false,false,true, //4
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false,false,true, true, true, false,false,true, false,false,true, true, true, false,false,true, //5
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false,false,true, true, true, false,false,true, false,false,false,true, false,false,false,true, //6
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false,false,true, true, true, false,false,true, false,false,true, true, true, false,false,true, //7
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true, false,true, true, false,false,false,true, false,true, false,true, false,false,false,true, //8
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false,false,true, true, false,false,false,true, false,false,false,true, true, false,true, true, //9
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false,false,false,true, false,false,false,true, false,false,false,true, false,false,false,true, //A
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false,false,true, true, false,false,false,true, false,false,false,true, false,false,false,true, //B
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false,false,true, true, false,false,false,true, false,false,false,true, false,false,false,true, //C
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false,false,true, true, true, false,false,true, false,false,true, true, true, false,false,true, //D
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false,false,true, true, false,false,false,true, false,false,false,true, false,false,false,true, //E
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false,false,true, true, true, false,false,true, false,false,true, true, true, false,false,true //F
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};
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typedef AddrMode M;
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AddrMode opMode[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //0
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//1
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M::Abs, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //2
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//3
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //4
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//5
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Ind, M::Abs, M::Abs, M::Abs, //6
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//7
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //8
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M::Rel, M::IndYW, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroY, M::ZeroY, M::Imp, M::AbsYW,M::Imp, M::AbsYW,M::AbsXW,M::AbsXW,M::AbsYW,M::AbsYW,//9
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //A
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M::Rel, M::IndY, M::None, M::IndY, M::ZeroX, M::ZeroX, M::ZeroY, M::ZeroY, M::Imp, M::AbsY, M::Imp, M::AbsY, M::AbsX, M::AbsX, M::AbsY, M::AbsY, //B
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //C
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//D
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //E
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//F
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};
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for(int i = 0; i < 256; i++) {
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if(useLowerCase) {
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string name = opName[i];
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std::transform(name.begin(), name.end(), name.begin(), ::tolower);
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DisassemblyInfo::OPName[i] = name + (unofficial[i] ? "* " : " ");
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} else {
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DisassemblyInfo::OPName[i] = opName[i] + (unofficial[i] ? "* " : " ");
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}
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DisassemblyInfo::IsUnofficialCode[i] = unofficial[i];
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DisassemblyInfo::OPMode[i] = opMode[i];
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switch(DisassemblyInfo::OPMode[i]) {
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case AddrMode::Abs:
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case AddrMode::AbsX:
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case AddrMode::AbsXW:
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case AddrMode::AbsY:
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case AddrMode::AbsYW:
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case AddrMode::Ind:
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DisassemblyInfo::OPSize[i] = 3;
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break;
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case AddrMode::Imm:
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case AddrMode::IndX:
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case AddrMode::IndY:
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case AddrMode::IndYW:
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case AddrMode::Rel:
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case AddrMode::Zero:
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case AddrMode::ZeroX:
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case AddrMode::ZeroY:
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DisassemblyInfo::OPSize[i] = 2;
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break;
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default:
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DisassemblyInfo::OPSize[i] = 1;
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break;
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}
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}
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}
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bool Disassembler::IsUnofficialOpCode(uint8_t opCode)
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{
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return DisassemblyInfo::IsUnofficialCode[opCode];
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}
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bool Disassembler::IsJump(uint8_t opCode)
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{
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return opCode == 0x10 || opCode == 0x30|| opCode == 0x50 || opCode == 0x70 || opCode == 0x90 || opCode == 0xB0 || opCode == 0xD0 || opCode == 0xF0 || opCode == 0x4C || opCode == 0x20;
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}
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bool Disassembler::IsUnconditionalJump(uint8_t opCode)
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{
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return opCode == 0x40 || opCode == 0x60 || opCode == 0x6C || opCode == 0x4C || opCode == 0x20;
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}
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void Disassembler::GetInfo(AddressTypeInfo &info, uint8_t** source, uint32_t &size, vector<shared_ptr<DisassemblyInfo>> **cache)
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{
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switch(info.Type) {
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case AddressType::InternalRam:
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*source = _memoryManager->GetInternalRAM();
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*cache = &_disassembleMemoryCache;
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size = 0x800;
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break;
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case AddressType::PrgRom:
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*source = _mapper->GetPrgRom();
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*cache = &_disassembleCache;
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size = _mapper->GetMemorySize(DebugMemoryType::PrgRom);
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break;
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case AddressType::WorkRam:
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*source = _mapper->GetWorkRam();
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*cache = &_disassembleWorkRamCache;
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size = _mapper->GetMemorySize(DebugMemoryType::WorkRam);
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break;
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case AddressType::SaveRam:
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*source = _mapper->GetSaveRam();
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*cache = &_disassembleSaveRamCache;
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size = _mapper->GetMemorySize(DebugMemoryType::SaveRam);
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break;
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}
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}
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uint32_t Disassembler::BuildCache(AddressTypeInfo &info, uint16_t cpuAddress, bool isSubEntryPoint)
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{
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if(info.Type == AddressType::InternalRam) {
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uint16_t memoryAddr = info.Address & 0x7FF;
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if(!_disassembleMemoryCache[memoryAddr]) {
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shared_ptr<DisassemblyInfo> disInfo(new DisassemblyInfo(_memoryManager->GetInternalRAM()+memoryAddr, isSubEntryPoint));
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_disassembleMemoryCache[memoryAddr] = disInfo;
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memoryAddr += disInfo->GetSize();
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} else if(isSubEntryPoint) {
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_disassembleMemoryCache[memoryAddr]->SetSubEntryPoint();
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}
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return memoryAddr;
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} else {
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vector<shared_ptr<DisassemblyInfo>> *cache;
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uint8_t *source;
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uint32_t size;
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GetInfo(info, &source, size, &cache);
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int32_t absoluteAddr = info.Address;
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if(info.Address >= 0) {
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DisassemblyInfo *disInfo = (*cache)[info.Address].get();
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if(!disInfo) {
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while(absoluteAddr < (int32_t)size && !(*cache)[absoluteAddr]) {
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bool isJump = IsUnconditionalJump(source[absoluteAddr]);
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disInfo = new DisassemblyInfo(source+absoluteAddr, isSubEntryPoint);
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isSubEntryPoint = false;
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(*cache)[absoluteAddr] = shared_ptr<DisassemblyInfo>(disInfo);
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absoluteAddr += disInfo->GetSize();
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if(isJump) {
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//Hit a jump/return instruction, can't assume that what follows is actual code, stop disassembling
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break;
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}
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}
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} else {
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if(isSubEntryPoint) {
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disInfo->SetSubEntryPoint();
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}
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uint8_t opCode = source[info.Address];
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if(IsJump(opCode)) {
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uint16_t jumpDest = disInfo->GetOpAddr(cpuAddress);
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if(jumpDest != cpuAddress) {
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AddressTypeInfo addressInfo;
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_debugger->GetAbsoluteAddressAndType(jumpDest, &addressInfo);
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const uint8_t jsrCode = 0x20;
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if(addressInfo.Address >= 0) {
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BuildCache(addressInfo, jumpDest, opCode == jsrCode);
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}
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}
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}
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absoluteAddr += disInfo->GetSize();
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}
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}
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return absoluteAddr;
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}
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}
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void Disassembler::InvalidateCache(AddressTypeInfo &info)
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{
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int32_t addr;
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vector<shared_ptr<DisassemblyInfo>> *cache = nullptr;
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switch(info.Type) {
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case AddressType::InternalRam:
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addr = info.Address & 0x7FF;
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cache = &_disassembleMemoryCache;
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break;
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case AddressType::WorkRam:
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addr = info.Address;
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cache = &_disassembleWorkRamCache;
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break;
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case AddressType::SaveRam:
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addr = info.Address;
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cache = &_disassembleSaveRamCache;
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break;
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}
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if(cache && addr >= 0) {
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for(int i = 1; i <= 2; i++) {
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int offsetAddr = (int)addr - i;
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if(offsetAddr >= 0) {
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if((*cache)[offsetAddr] != nullptr) {
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if((*cache)[offsetAddr]->GetSize() >= (uint32_t)i + 1) {
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//Invalidate any instruction that overlapped this address
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(*cache)[offsetAddr] = nullptr;
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}
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}
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}
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}
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(*cache)[addr] = nullptr;
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}
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}
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void Disassembler::RebuildPrgRomCache(uint32_t absoluteAddr, int32_t length)
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{
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for(int i = 1; i <= 2; i++) {
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int offsetAddr = (int)absoluteAddr - i;
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if(offsetAddr >= 0) {
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if(_disassembleCache[offsetAddr] != nullptr) {
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if(_disassembleCache[offsetAddr]->GetSize() >= (uint32_t)i + 1) {
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//Invalidate any instruction that overlapped this address
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_disassembleCache[offsetAddr] = nullptr;
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}
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}
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}
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}
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bool isSubEntryPoint = false;
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if(_disassembleCache[absoluteAddr]) {
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isSubEntryPoint = _disassembleCache[absoluteAddr]->IsSubEntryPoint();
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}
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for(int i = absoluteAddr, end = absoluteAddr + length; i < end; i++) {
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_disassembleCache[i] = nullptr;
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}
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uint16_t memoryAddr = _debugger->GetRelativeAddress(absoluteAddr, AddressType::PrgRom);
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AddressTypeInfo info = { (int32_t)absoluteAddr, AddressType::PrgRom };
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BuildCache(info, memoryAddr, isSubEntryPoint);
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}
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static const char* hexTable[256] = {
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"00", "01", "02", "03", "04", "05", "06", "07", "08", "09", "0A", "0B", "0C", "0D", "0E", "0F",
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"10", "11", "12", "13", "14", "15", "16", "17", "18", "19", "1A", "1B", "1C", "1D", "1E", "1F",
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"20", "21", "22", "23", "24", "25", "26", "27", "28", "29", "2A", "2B", "2C", "2D", "2E", "2F",
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"30", "31", "32", "33", "34", "35", "36", "37", "38", "39", "3A", "3B", "3C", "3D", "3E", "3F",
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"40", "41", "42", "43", "44", "45", "46", "47", "48", "49", "4A", "4B", "4C", "4D", "4E", "4F",
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"50", "51", "52", "53", "54", "55", "56", "57", "58", "59", "5A", "5B", "5C", "5D", "5E", "5F",
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"60", "61", "62", "63", "64", "65", "66", "67", "68", "69", "6A", "6B", "6C", "6D", "6E", "6F",
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"70", "71", "72", "73", "74", "75", "76", "77", "78", "79", "7A", "7B", "7C", "7D", "7E", "7F",
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"80", "81", "82", "83", "84", "85", "86", "87", "88", "89", "8A", "8B", "8C", "8D", "8E", "8F",
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"90", "91", "92", "93", "94", "95", "96", "97", "98", "99", "9A", "9B", "9C", "9D", "9E", "9F",
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"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "A8", "A9", "AA", "AB", "AC", "AD", "AE", "AF",
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"B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7", "B8", "B9", "BA", "BB", "BC", "BD", "BE", "BF",
|
|
"C0", "C1", "C2", "C3", "C4", "C5", "C6", "C7", "C8", "C9", "CA", "CB", "CC", "CD", "CE", "CF",
|
|
"D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7", "D8", "D9", "DA", "DB", "DC", "DD", "DE", "DF",
|
|
"E0", "E1", "E2", "E3", "E4", "E5", "E6", "E7", "E8", "E9", "EA", "EB", "EC", "ED", "EE", "EF",
|
|
"F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "F8", "F9", "FA", "FB", "FC", "FD", "FE", "FF"
|
|
};
|
|
|
|
static string emptyString;
|
|
void Disassembler::GetLine(string &out, string code, string comment, int32_t cpuAddress, int32_t absoluteAddress)
|
|
{
|
|
GetCodeLine(out, code, comment, cpuAddress, absoluteAddress, emptyString, emptyString, false, false);
|
|
}
|
|
|
|
void Disassembler::GetCodeLine(string &out, string &code, string &comment, int32_t cpuAddress, int32_t absoluteAddress, string &byteCode, string &addressing, bool speculativeCode, bool isIndented)
|
|
{
|
|
char buffer[1000];
|
|
int pos = 0;
|
|
char* ptrBuf = buffer;
|
|
int* ptrPos = &pos;
|
|
|
|
auto writeChar = [=](char c) -> void {
|
|
if(*ptrPos < 999) {
|
|
ptrBuf[(*ptrPos)++] = c;
|
|
}
|
|
};
|
|
|
|
auto writeHex = [=](const char* hex) -> void {
|
|
if(*ptrPos < 950) {
|
|
ptrBuf[(*ptrPos)++] = hex[0];
|
|
ptrBuf[(*ptrPos)++] = hex[1];
|
|
}
|
|
};
|
|
|
|
auto writeStr = [=](string &str) -> void {
|
|
uint32_t len = (uint32_t)str.size();
|
|
if(*ptrPos + len < 950) {
|
|
memcpy(ptrBuf + (*ptrPos), str.c_str(), len);
|
|
(*ptrPos) += len;
|
|
} else {
|
|
len = 950 - *ptrPos;
|
|
memcpy(ptrBuf + (*ptrPos), str.c_str(), len);
|
|
(*ptrPos) += len;
|
|
}
|
|
};
|
|
|
|
//Fields:
|
|
//Flags | CpuAddress | AbsAddr | ByteCode | Code | Addressing | Comment
|
|
if(cpuAddress >= 0) {
|
|
if(speculativeCode) {
|
|
writeChar(isIndented ? '6' : '2');
|
|
writeChar('\x1');
|
|
} else {
|
|
writeChar((_debugger->IsMarkedAsCode(cpuAddress) || absoluteAddress == -1) ? (isIndented ? '5' : '1') : (isIndented ? '4' : '0'));
|
|
writeChar('\x1');
|
|
}
|
|
writeHex(hexTable[(cpuAddress >> 8) & 0xFF]);
|
|
writeHex(hexTable[cpuAddress & 0xFF]);
|
|
writeChar('\x1');
|
|
} else {
|
|
writeChar('1');
|
|
writeChar('\x1');
|
|
writeChar('\x1');
|
|
}
|
|
|
|
if(absoluteAddress >= 0) {
|
|
if(absoluteAddress > 0xFFFFFF) {
|
|
writeHex(hexTable[(absoluteAddress >> 24) & 0xFF]);
|
|
}
|
|
if(absoluteAddress > 0xFFFF) {
|
|
writeHex(hexTable[(absoluteAddress >> 16) & 0xFF]);
|
|
}
|
|
writeHex(hexTable[(absoluteAddress >> 8) & 0xFF]);
|
|
writeHex(hexTable[absoluteAddress & 0xFF]);
|
|
}
|
|
|
|
writeChar('\x1');
|
|
writeStr(byteCode);
|
|
writeChar('\x1');
|
|
writeStr(code);
|
|
writeChar('\x1');
|
|
writeStr(addressing);
|
|
writeChar('\x1');
|
|
if(!comment.empty()) {
|
|
writeChar(';');
|
|
writeStr(comment);
|
|
}
|
|
writeChar('\x1');
|
|
ptrBuf[(*ptrPos)++] = 0;
|
|
|
|
out.append(buffer, pos - 1);
|
|
}
|
|
|
|
void Disassembler::GetSubHeader(string &out, DisassemblyInfo *info, string &label, uint16_t relativeAddr, uint16_t resetVector, uint16_t nmiVector, uint16_t irqVector)
|
|
{
|
|
if(info->IsSubEntryPoint()) {
|
|
if(label.empty()) {
|
|
GetLine(out);
|
|
GetLine(out, "__sub start__");
|
|
} else {
|
|
GetLine(out);
|
|
GetLine(out, "__" + label + "()__");
|
|
}
|
|
} else if(relativeAddr == resetVector) {
|
|
GetLine(out);
|
|
GetLine(out, "--reset--");
|
|
} else if(relativeAddr == irqVector) {
|
|
GetLine(out);
|
|
GetLine(out, "--irq--");
|
|
} else if(relativeAddr == nmiVector) {
|
|
GetLine(out);
|
|
GetLine(out, "--nmi--");
|
|
}
|
|
}
|
|
|
|
string Disassembler::GetCode(AddressTypeInfo &addressInfo, uint32_t endAddr, uint16_t memoryAddr, bool showEffectiveAddresses, bool showOnlyDiassembledCode, State& cpuState, shared_ptr<MemoryManager> memoryManager, shared_ptr<LabelManager> labelManager)
|
|
{
|
|
string output;
|
|
output.reserve(10000000);
|
|
|
|
int32_t dbRelativeAddr = 0;
|
|
int32_t dbAbsoluteAddr = 0;
|
|
string dbBuffer;
|
|
|
|
uint16_t resetVector = memoryManager->DebugReadWord(CPU::ResetVector);
|
|
uint16_t nmiVector = memoryManager->DebugReadWord(CPU::NMIVector);
|
|
uint16_t irqVector = memoryManager->DebugReadWord(CPU::IRQVector);
|
|
|
|
vector<shared_ptr<DisassemblyInfo>> *cache;
|
|
uint8_t *source;
|
|
uint32_t mask = addressInfo.Type == AddressType::InternalRam ? 0x7FF : 0xFFFFFFFF;
|
|
uint32_t size;
|
|
uint8_t* internalRam = _memoryManager->GetInternalRAM();
|
|
|
|
GetInfo(addressInfo, &source, size, &cache);
|
|
|
|
string unknownBlockHeader = showOnlyDiassembledCode ? "----" : "__unknown block__";
|
|
uint32_t addr = addressInfo.Address;
|
|
uint32_t byteCount = 0;
|
|
bool skippingCode = false;
|
|
shared_ptr<CodeDataLogger> cdl = _debugger->GetCodeDataLogger();
|
|
string label;
|
|
string commentString;
|
|
string commentLines;
|
|
shared_ptr<DisassemblyInfo> infoRef;
|
|
DisassemblyInfo* info;
|
|
bool speculativeCode;
|
|
string spaces = " ";
|
|
string effAddress;
|
|
string code;
|
|
string byteCode;
|
|
while(addr <= endAddr) {
|
|
labelManager->GetLabelAndComment(memoryAddr, label, commentString);
|
|
commentLines.clear();
|
|
speculativeCode = false;
|
|
|
|
if(commentString.find_first_of('\n') != string::npos) {
|
|
for(string &str : StringUtilities::Split(commentString, '\n')) {
|
|
GetLine(commentLines, "", str);
|
|
}
|
|
commentString.clear();
|
|
}
|
|
|
|
infoRef = (*cache)[addr&mask];
|
|
|
|
info = infoRef.get();
|
|
if(!info && (_debugger->CheckFlag(DebuggerFlags::DisassembleEverything) || _debugger->CheckFlag(DebuggerFlags::DisassembleEverythingButData) && !cdl->IsData(addr))) {
|
|
speculativeCode = true;
|
|
info = new DisassemblyInfo(source + (addr & mask), false);
|
|
}
|
|
|
|
if(info && addr + info->GetSize() <= endAddr) {
|
|
if(byteCount > 0) {
|
|
GetLine(output, dbBuffer, "", dbRelativeAddr, dbAbsoluteAddr);
|
|
byteCount = 0;
|
|
}
|
|
|
|
if(skippingCode) {
|
|
GetLine(output, unknownBlockHeader, "", (uint16_t)(memoryAddr - 1), addr - 1);
|
|
skippingCode = false;
|
|
}
|
|
|
|
GetSubHeader(output, info, label, memoryAddr, resetVector, nmiVector, irqVector);
|
|
output += commentLines;
|
|
if(!label.empty()) {
|
|
GetLine(output, label + ":");
|
|
}
|
|
|
|
byteCode.clear();
|
|
code.clear();
|
|
effAddress.clear();
|
|
info->GetEffectiveAddressString(effAddress, cpuState, memoryManager.get(), labelManager.get());
|
|
info->ToString(code, memoryAddr, memoryManager.get(), labelManager.get());
|
|
info->GetByteCode(byteCode);
|
|
|
|
GetCodeLine(output, code, commentString, memoryAddr, source != internalRam ? addr : -1, byteCode, effAddress, speculativeCode, true);
|
|
|
|
if(info->IsSubExitPoint()) {
|
|
GetLine(output, "__sub end__");
|
|
GetLine(output);
|
|
}
|
|
|
|
if(speculativeCode) {
|
|
//For unverified code, check if a verified instruction starts between the start of this instruction and its end.
|
|
//If so, we need to realign the disassembler to the start of the next verified instruction
|
|
for(uint32_t i = 0; i < info->GetSize(); i++) {
|
|
addr++;
|
|
memoryAddr++;
|
|
if(addr > endAddr || (*cache)[addr&mask]) {
|
|
//Verified code found, stop incrementing address counters
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
addr += info->GetSize();
|
|
memoryAddr += info->GetSize();
|
|
}
|
|
} else {
|
|
if((!label.empty() || !commentString.empty()) && skippingCode) {
|
|
GetLine(output, unknownBlockHeader, "", (uint16_t)(memoryAddr - 1), addr - 1);
|
|
skippingCode = false;
|
|
}
|
|
|
|
if(!skippingCode && showOnlyDiassembledCode) {
|
|
if(label.empty()) {
|
|
GetLine(output, "__unknown block__", "", memoryAddr, addr);
|
|
if(!commentString.empty()) {
|
|
GetLine(output, "", commentString);
|
|
}
|
|
} else {
|
|
GetLine(output, "__" + label + "__", "", memoryAddr, addr);
|
|
if(!commentString.empty()) {
|
|
GetLine(output, "", commentString);
|
|
}
|
|
output += commentLines;
|
|
}
|
|
skippingCode = true;
|
|
}
|
|
|
|
if(!showOnlyDiassembledCode) {
|
|
if(byteCount >= 8 || ((!label.empty() || !commentString.empty()) && byteCount > 0)) {
|
|
GetLine(output, dbBuffer, "", dbRelativeAddr, dbAbsoluteAddr);
|
|
byteCount = 0;
|
|
}
|
|
|
|
if(byteCount == 0) {
|
|
dbBuffer = ".db";
|
|
output += commentLines;
|
|
if(!label.empty()) {
|
|
GetLine(output, label + ":");
|
|
}
|
|
|
|
dbRelativeAddr = memoryAddr;
|
|
dbAbsoluteAddr = addr;
|
|
}
|
|
|
|
dbBuffer += " $" + HexUtilities::ToHex(source[addr&mask]);
|
|
|
|
if(!label.empty() || !commentString.empty()) {
|
|
GetLine(output, dbBuffer, commentString, dbRelativeAddr, dbAbsoluteAddr);
|
|
byteCount = 0;
|
|
} else {
|
|
byteCount++;
|
|
}
|
|
}
|
|
addr++;
|
|
memoryAddr++;
|
|
}
|
|
|
|
if(speculativeCode) {
|
|
delete info;
|
|
}
|
|
}
|
|
|
|
if(byteCount > 0) {
|
|
GetLine(output, dbBuffer, "", dbRelativeAddr, dbAbsoluteAddr);
|
|
}
|
|
|
|
if(skippingCode) {
|
|
GetLine(output, "----", "", (uint16_t)(memoryAddr - 1), addr - 1);
|
|
}
|
|
|
|
return output;
|
|
}
|
|
|
|
DisassemblyInfo Disassembler::GetDisassemblyInfo(AddressTypeInfo &info)
|
|
{
|
|
DisassemblyInfo* disassemblyInfo = nullptr;
|
|
switch(info.Type) {
|
|
case AddressType::InternalRam: disassemblyInfo = _disassembleMemoryCache[info.Address & 0x7FF].get(); break;
|
|
case AddressType::PrgRom: disassemblyInfo = _disassembleCache[info.Address].get(); break;
|
|
case AddressType::WorkRam: disassemblyInfo = _disassembleWorkRamCache[info.Address].get(); break;
|
|
case AddressType::SaveRam: disassemblyInfo = _disassembleSaveRamCache[info.Address].get(); break;
|
|
}
|
|
|
|
if(disassemblyInfo) {
|
|
return *disassemblyInfo;
|
|
} else {
|
|
return DisassemblyInfo();
|
|
}
|
|
} |