On late-G and H CPUs, starting a 1-byte sample just before the end of a DMC period can cause the sample to be fetched and played twice. This change fixes 2 issues related to this.
First, new research found that this bug is because there is normally at least a 1-APU cycle gap between the end of one DMC DMA and the start of the next DMC DMA on earlier CPUs, but these later CPUs remove that gap, allowing the aborted DMA behavior to occur sooner such that it can't be aborted.
But this means it actually affects any sample that is started at the end of a DMC period, not just ones that trigger the extra DMA. Mesen was previously only doing this in the case of 1-byte non-looping samples. This change fixes this issue. This was validated with AccuracyCoin's Implicit DMA Abort test and with dmc_dma_stop_test_v3 test F.
Second, when there are two DMC DMA's back to back while reading a joypad register, both of them should cause an extra clock of the joypads when using NES behavior (unless suppressed by the APU register activation bug). However, we were only seeing extra clocks with HVC-001 behavior (which is handled on every DMA cycle always) because Mesen only runs its halt cycle logic for the first of the two DMAs. This change makes ProcessPendingDma call itself in the case where we handle DMC DMA back to back so it can do this extra joypad clock if need be.
This second change was validated with dmc_dma_start_test_v2 test C, dmc_dma_implicit_stop_level_test, and a variant of apu_register_activation_test.
* Code: Add auto-formatting rules for C++ projects (clang-format) and enforce code style via "clang-format" and "dotnet format"
* fix ui format warnings
Fiskbit