mirror of
https://github.com/libretro/MesenCE.git
synced 2026-11-10 03:02:05 -10:00
654 lines
18 KiB
C++
654 lines
18 KiB
C++
#include "pch.h"
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#include "GBA/GbaCpu.h"
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#include "GBA/GbaMemoryManager.h"
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#include "GBA/GbaCpuMultiply.h"
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#include "Shared/Emulator.h"
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ArmOpCategory GbaCpu::_armCategory[0x1000];
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GbaCpu::Func GbaCpu::_armTable[0x1000];
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ArmOpCategory GbaCpu::GetArmOpCategory(uint32_t opCode)
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{
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uint16_t opType = ((opCode & 0x0FF00000) >> 16) | ((opCode & 0xF0) >> 4);
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return _armCategory[opType];
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}
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void GbaCpu::ArmBranchExchangeRegister()
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{
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//A lot of this behavior is not officially documented in the data sheet (and is similar to the behavior of MSR)
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//Passes png183's "branches" test: https://github.com/png183/gba-tests/blob/master/arm/
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uint8_t mask = (_opCode >> 16) & 0x0F;
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uint32_t value = R(_opCode & 0x0F);
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bool writeToSpsr = _opCode & (1 << 22);
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if((mask & 0x09) == 0x09) {
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GbaCpuFlags& flags = writeToSpsr ? GetSpsr() : _state.CPSR;
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flags.Thumb = (value & 0x01) != 0;
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} else {
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SetStatusFlags(writeToSpsr, mask, value);
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}
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uint8_t rd = (_opCode >> 12) & 0x0F;
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SetR(rd, value);
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}
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void GbaCpu::ArmBranch()
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{
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bool withLink = (_opCode & (1 << 24)) != 0;
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int32_t offset = (((int32_t)_opCode << 8) >> 6); //sign extend + shift right by 2
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if(withLink) {
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_state.R[14] = _state.R[15] - 4;
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}
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_state.R[15] += offset;
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_state.Pipeline.ReloadRequested = true;
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}
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void GbaCpu::ArmMsr()
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{
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//----_00i1_0d10_mmmm_1111_oooo_oooo_oooo
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//i: immediate
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//d: destination psr
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//o: operand
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//m: mask
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bool immediate = _opCode & (1 << 25);
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bool writeToSpsr = _opCode & (1 << 22);
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uint8_t mask = (_opCode >> 16) & 0x0F;
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if(writeToSpsr && (_state.CPSR.Mode == GbaCpuMode::User || _state.CPSR.Mode == GbaCpuMode::System)) {
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return;
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}
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uint32_t value;
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if(immediate) {
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value = _opCode & 0xFF;
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uint8_t shift = (_opCode >> 8) & 0x0F;
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if(shift) {
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value = RotateRight(value, shift * 2);
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}
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} else {
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value = R(_opCode & 0x0F);
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}
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SetStatusFlags(writeToSpsr, mask, value);
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}
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void GbaCpu::SetStatusFlags(bool writeToSpsr, uint8_t mask, uint32_t value)
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{
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if(writeToSpsr && (_state.CPSR.Mode == GbaCpuMode::User || _state.CPSR.Mode == GbaCpuMode::System)) {
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return;
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}
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GbaCpuFlags& flags = writeToSpsr ? GetSpsr() : _state.CPSR;
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if(mask & 0x08) {
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flags.Negative = value & (1 << 31);
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flags.Zero = value & (1 << 30);
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flags.Carry = value & (1 << 29);
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flags.Overflow = value & (1 << 28);
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}
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if(mask & 0x01) {
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if(writeToSpsr || _state.CPSR.Mode != GbaCpuMode::User) {
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if(!writeToSpsr) {
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SwitchMode((GbaCpuMode)(value & 0x1F));
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} else {
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flags.Mode = (GbaCpuMode)(value & 0x1F);
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}
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flags.Thumb = value & (1 << 5);
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flags.FiqDisable = value & (1 << 6);
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flags.IrqDisable = value & (1 << 7);
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}
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}
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}
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void GbaCpu::ArmMrs()
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{
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//----_0001_0s00_1111_dddd_0000_0000_0000
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//s: source psr
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//d: destination reg
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bool useSpsr = _opCode & (1 << 22);
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uint8_t rd = (_opCode >> 12) & 0x0F;
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SetR(rd, useSpsr ? GetSpsr().ToInt32() : _state.CPSR.ToInt32());
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}
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void GbaCpu::ArmDataProcessing()
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{
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//Data Processing
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//----_00io_ooos_nnnn_dddd_pppp_pppp_pppp
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//i: immediate
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//o: opcode
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//s: set flags
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//n: 1st operand reg
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//d: destination reg
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//p: 2nd operand
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bool immediate = (_opCode & (1 << 25)) != 0;
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uint8_t rn = (_opCode >> 16) & 0x0F;
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uint32_t op1 = R(rn);
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uint8_t dstReg = (_opCode >> 12) & 0x0F;
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bool updateFlags = (_opCode & (1 << 20)) != 0;
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uint32_t op2;
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bool carry = _state.CPSR.Carry;
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if(immediate) {
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uint8_t shift = (_opCode >> 8) & 0x0F;
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op2 = (_opCode & 0xFF);
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if(shift) {
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op2 = RotateRight(op2, shift * 2, carry);
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}
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} else {
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uint8_t shiftType = (_opCode >> 5) & 0x03;
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uint8_t shift;
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uint8_t rm = _opCode & 0x0F;
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op2 = R(rm);
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bool useRegValue = _opCode & (1 << 4);
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if(useRegValue) {
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//Shift amount in register
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Idle();
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uint8_t rs = (_opCode >> 8) & 0x0F;
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shift = R(rs) + (rs == 15 ? 4 : 0);
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if(rm == 15) {
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op2 += 4;
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}
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if(rn == 15) {
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op1 += 4;
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}
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} else {
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shift = (_opCode >> 7) & 0x1F;
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}
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switch(shiftType) {
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case 0: op2 = ShiftLsl(op2, shift, carry); break;
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case 1: op2 = ShiftLsr(op2, (useRegValue || shift) ? shift : 32, carry); break;
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case 2: op2 = ShiftAsr(op2, (useRegValue || shift) ? shift : 32, carry); break;
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case 3: op2 = (!useRegValue && shift == 0) ? ShiftRrx(op2, carry) : ShiftRor(op2, shift, carry); break;
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}
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}
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switch((ArmAluOperation)((_opCode >> 21) & 0x0F)) {
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case ArmAluOperation::And: SetR(dstReg, LogicalOp(op1 & op2, carry, updateFlags)); break;
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case ArmAluOperation::Eor: SetR(dstReg, LogicalOp(op1 ^ op2, carry, updateFlags)); break;
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case ArmAluOperation::Sub: SetR(dstReg, Sub(op1, op2, true, updateFlags)); break;
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case ArmAluOperation::Rsb: SetR(dstReg, Sub(op2, op1, true, updateFlags)); break;
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case ArmAluOperation::Add: SetR(dstReg, Add(op1, op2, false, updateFlags)); break;
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case ArmAluOperation::Adc: SetR(dstReg, Add(op1, op2, _state.CPSR.Carry, updateFlags)); break;
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case ArmAluOperation::Sbc: SetR(dstReg, Sub(op1, op2, _state.CPSR.Carry, updateFlags)); break;
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case ArmAluOperation::Rsc: SetR(dstReg, Sub(op2, op1, _state.CPSR.Carry, updateFlags)); break;
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case ArmAluOperation::Tst: LogicalOp(op1 & op2, carry, true); break;
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case ArmAluOperation::Teq: LogicalOp(op1 ^ op2, carry, true); break;
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case ArmAluOperation::Cmp: Sub(op1, op2, true, true); break;
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case ArmAluOperation::Cmn: Add(op1, op2, false, true); break;
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case ArmAluOperation::Orr: SetR(dstReg, LogicalOp(op1 | op2, carry, updateFlags)); break;
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case ArmAluOperation::Mov: SetR(dstReg, LogicalOp(op2, carry, updateFlags)); break;
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case ArmAluOperation::Bic: SetR(dstReg, LogicalOp(op1 & ~op2, carry, updateFlags)); break;
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case ArmAluOperation::Mvn: SetR(dstReg, LogicalOp(~op2, carry, updateFlags)); break;
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}
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if(dstReg == 15 && updateFlags) {
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GbaCpuFlags spsr = GetSpsr();
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SwitchMode(spsr.Mode);
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_state.CPSR = spsr;
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}
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}
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void GbaCpu::ArmMultiply()
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{
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//Multiply and Multiply-Accumulate (MUL, MLA)
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//----_0000_00as_dddd_nnnn_ssss_1001_mmmm
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uint8_t rd = (_opCode >> 16) & 0x0F;
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uint8_t rn = (_opCode >> 12) & 0x0F;
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uint8_t rs = (_opCode >> 8) & 0x0F;
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uint8_t rm = _opCode & 0x0F;
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bool updateFlags = (_opCode & (1 << 20)) != 0;
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bool multAndAcc = (_opCode & (1 << 21)) != 0;
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MultiplicationOutput output;
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if(multAndAcc) {
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uint32_t acc = R(rn);
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Idle();
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output = GbaCpuMultiply::mla(R(rm), R(rs), acc);
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} else {
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output = GbaCpuMultiply::mul(R(rm), R(rs));
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}
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Idle(output.CycleCount);
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uint32_t result = output.Output;
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if(rd != 15) {
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SetR(rd, result);
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}
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if(updateFlags) {
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_state.CPSR.Carry = output.Carry;
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_state.CPSR.Zero = result == 0;
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_state.CPSR.Negative = (result & (1 << 31));
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}
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}
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void GbaCpu::ArmMultiplyLong()
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{
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//Multiply Long and Multiply-Accumulate Long (MULL,MLAL)
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//----_0000_1uas_hhhh_llll_ssss_1001_mmmm
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uint8_t rh = (_opCode >> 16) & 0x0F;
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uint8_t rl = (_opCode >> 12) & 0x0F;
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uint8_t rs = (_opCode >> 8) & 0x0F;
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uint8_t rm = _opCode & 0x0F;
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bool updateFlags = (_opCode & (1 << 20)) != 0;
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bool multAndAcc = (_opCode & (1 << 21)) != 0;
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bool sign = (_opCode & (1 << 22)) != 0;
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uint32_t accLo = 0;
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uint32_t accHi = 0;
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if(multAndAcc) {
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accLo = R(rl);
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accHi = R(rh);
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Idle();
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}
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Idle();
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MultiplicationOutput output;
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if(sign) {
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if(multAndAcc) {
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output = GbaCpuMultiply::smlal(accLo, accHi, R(rm), R(rs));
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} else {
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output = GbaCpuMultiply::smull(R(rm), R(rs));
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}
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} else {
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if(multAndAcc) {
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output = GbaCpuMultiply::umlal(accLo, accHi, R(rm), R(rs));
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} else {
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output = GbaCpuMultiply::umull(R(rm), R(rs));
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}
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}
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Idle(output.CycleCount);
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uint64_t result = output.Output;
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if(rl != 15) {
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SetR(rl, (uint32_t)result);
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}
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if(rh != 15) {
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SetR(rh, (uint32_t)(result >> 32));
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}
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if(updateFlags) {
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_state.CPSR.Carry = output.Carry;
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_state.CPSR.Zero = result == 0;
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_state.CPSR.Negative = (result & ((uint64_t)1 << 63));
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}
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}
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void GbaCpu::ArmSingleDataTransfer()
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{
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//Single Data Transfer (LDR, STR)
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//----_01ip_ubwl_nnnn_dddd_oooo_oooo_oooo
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//i: immediate (when cleared)
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//p: post/pre: add offset after/before transfer
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//u: down/up: subtract/add offset from/to base
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//b: byte transfer
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//w: write-back: write address into base
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//l: store/load
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//n: base register
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//d: src/dst register
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//o: offset (immediate or register)
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bool immediate = (_opCode & (1 << 25)) == 0;
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bool pre = (_opCode & (1 << 24)) != 0;
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bool up = (_opCode & (1 << 23)) != 0;
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bool byte = (_opCode & (1 << 22)) != 0;
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bool writeBack = (_opCode & (1 << 21)) != 0;
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bool load = (_opCode & (1 << 20)) != 0;
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uint8_t rn = (_opCode >> 16) & 0x0F;
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uint8_t rd = (_opCode >> 12) & 0x0F;
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uint32_t addr = R(rn);
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int32_t offset;
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if(immediate) {
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offset = _opCode & 0xFFF;
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} else {
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uint8_t shiftType = (_opCode >> 5) & 0x03;
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uint8_t shift;
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uint8_t rm = _opCode & 0x0F;
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shift = (_opCode >> 7) & 0x1F;
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offset = R(rm);
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bool carry = _state.CPSR.Carry;
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switch(shiftType) {
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case 0: offset = ShiftLsl(offset, shift, carry); break;
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case 1: offset = ShiftLsr(offset, shift ? shift : 32, carry); break;
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case 2: offset = ShiftAsr(offset, shift ? shift : 32, carry); break;
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case 3: offset = shift == 0 ? ShiftRrx(offset, carry) : ShiftRor(offset, shift, carry); break;
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}
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}
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if(pre) {
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addr += up ? offset : -offset;
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}
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GbaAccessModeVal mode = byte ? GbaAccessMode::Byte : GbaAccessMode::Word;
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if(load) {
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SetR(rd, Read(mode, addr));
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Idle();
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} else {
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Write(mode, addr, R(rd) + (rd == 15 ? 4 : 0));
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}
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if(!pre) {
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addr += up ? offset : -offset;
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}
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if((rd != rn || !load) && (writeBack || !pre)) {
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SetR(rn, addr);
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}
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}
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void GbaCpu::ArmSignedHalfDataTransfer()
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{
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//Halfword and Signed Data Transfer (LDRH / STRH / LDRSB / LDRSH)
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//----_000p_uiwl_nnnn_dddd_0000_1sh1_mmmm
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bool pre = (_opCode & (1 << 24)) != 0;
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bool up = (_opCode & (1 << 23)) != 0;
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bool immediate = (_opCode & (1 << 22)) != 0;
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bool writeBack = (_opCode & (1 << 21)) != 0;
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bool load = (_opCode & (1 << 20)) != 0;
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uint8_t rn = (_opCode >> 16) & 0x0F;
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uint8_t rd = (_opCode >> 12) & 0x0F;
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bool sign = (_opCode & (1 << 6)) != 0;
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bool half = (_opCode & (1 << 5)) != 0;
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int32_t offset;
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if(immediate) {
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offset = ((_opCode >> 4) & 0xF0) | (_opCode & 0x0F);
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} else {
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uint8_t rm = _opCode & 0x0F;
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offset = (int32_t)R(rm);
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}
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uint32_t addr = R(rn);
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if(pre) {
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addr += up ? offset : -offset;
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}
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if(load) {
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if(half) {
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SetR(rd, Read(GbaAccessMode::HalfWord | (sign ? GbaAccessMode::Signed : 0), addr));
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} else {
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SetR(rd, Read(GbaAccessMode::Byte | (sign ? GbaAccessMode::Signed : 0), addr));
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}
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Idle();
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} else {
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uint32_t value = R(rd) + (rd == 15 ? 4 : 0);
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if(half) {
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Write(GbaAccessMode::HalfWord | (sign ? GbaAccessMode::Signed : 0), addr, value);
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} else {
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Write(GbaAccessMode::Byte | (sign ? GbaAccessMode::Signed : 0), addr, value);
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}
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}
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if(!pre) {
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addr += up ? offset : -offset;
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}
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if((rd != rn || !load) && (writeBack || !pre)) {
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SetR(rn, addr + (rn == 15 ? 4 : 0));
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}
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}
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void GbaCpu::ArmBlockDataTransfer()
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{
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//Block Data Transfer (LDM, STM)
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//----_100p_uswl_nnnn_rrrr_rrrr_rrrr_rrrr
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//p: post/pre: add offset after/before transfer
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//u: down/up: subtract/add offset from/to base
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//s: psr & force user bit
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//w: write-back: write address into base
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//l: store/load
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//n: base register
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//r: register list
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bool pre = (_opCode & (1 << 24)) != 0;
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bool up = (_opCode & (1 << 23)) != 0;
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bool psrForceUser = (_opCode & (1 << 22)) != 0;
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bool writeBack = (_opCode & (1 << 21)) != 0;
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bool load = (_opCode & (1 << 20)) != 0;
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uint8_t rn = (_opCode >> 16) & 0x0F;
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uint16_t regMask = (uint16_t)_opCode;
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uint32_t base = R(rn);
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uint32_t addr = base;
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uint8_t regCount = 0;
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for(int i = 0; i < 16; i++) {
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regCount += (regMask & (1 << i)) ? 1 : 0;
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}
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if(!regMask) {
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//Glitch when mask is empty - only R15 is stored/loaded, but address changes as if all 16 were written/loaded
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regCount = 16;
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regMask = 0x8000;
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}
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if(!up) {
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addr -= (regCount - (pre ? 0 : 1)) * 4;
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} else if(pre) {
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addr += 4;
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}
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if(writeBack && load) {
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SetR(rn, base + (regCount * (up ? 4 : -4)));
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}
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GbaCpuMode orgMode = _state.CPSR.Mode;
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if(psrForceUser && (!load || (load && !(regMask & 0x8000)))) {
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SwitchMode(GbaCpuMode::User);
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}
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bool firstReg = true;
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GbaAccessModeVal mode = GbaAccessMode::Word;
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for(int i = 0; i < 16; i++) {
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if(regMask & (1 << i)) {
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if(!load) {
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Write(mode, addr, R(i) + (i == 15 ? 4 : 0));
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}
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if(firstReg && writeBack) {
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//Write-back happens at this point, based on the gba-tests/arm test 522
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SetR(rn, base + (regCount * (up ? 4 : -4)));
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firstReg = false;
|
|
}
|
|
|
|
if(load) {
|
|
//LDM doesn't appear to be affected by the rotation that is usually applied to unaligned reads? based on gba-tests/arm test 508
|
|
SetR(i, Read(mode | GbaAccessMode::NoRotate, addr));
|
|
}
|
|
|
|
mode |= GbaAccessMode::Sequential;
|
|
addr += 4;
|
|
}
|
|
}
|
|
|
|
if(load) {
|
|
Idle();
|
|
}
|
|
|
|
SwitchMode(orgMode);
|
|
|
|
if(psrForceUser && load) {
|
|
if(regMask & 0x8000) {
|
|
GbaCpuFlags spsr = GetSpsr();
|
|
SwitchMode(spsr.Mode);
|
|
_state.CPSR = spsr;
|
|
}
|
|
|
|
//When LDM^ is used, if registers 8-14 are accessed on the next cycle,
|
|
//the result is ORed with the equivalent register in the user mode registers.
|
|
//This is a CPU bug that requires e.g a NOP after using LDM^ to avoid the issue.
|
|
_ldmGlitch = 2;
|
|
}
|
|
}
|
|
|
|
void GbaCpu::ArmSingleDataSwap()
|
|
{
|
|
//Single Data Swap (SWP)
|
|
//----_0001_0b00_nnnn_dddd_0000_1001_mmmm
|
|
bool byte = _opCode & (1 << 22);
|
|
uint8_t rn = (_opCode >> 16) & 0x0F;
|
|
uint8_t rd = (_opCode >> 12) & 0x0F;
|
|
uint8_t rm = _opCode & 0x0F;
|
|
|
|
uint32_t mode = byte ? GbaAccessMode::Byte : GbaAccessMode::Word;
|
|
#ifndef DUMMYCPU
|
|
_memoryManager->LockBus();
|
|
#endif
|
|
uint32_t src = R(rn);
|
|
uint32_t val = Read(mode, src);
|
|
Write(mode, src, rm == 15 ? (R(rm) + 4) : R(rm));
|
|
Idle();
|
|
#ifndef DUMMYCPU
|
|
_memoryManager->UnlockBus();
|
|
#endif
|
|
SetR(rd, val);
|
|
}
|
|
|
|
void GbaCpu::ArmSoftwareInterrupt()
|
|
{
|
|
ProcessException(GbaCpuMode::Supervisor, GbaCpuVector::SoftwareIrq);
|
|
}
|
|
|
|
void GbaCpu::ArmCoprocessorTransfer()
|
|
{
|
|
//MRC/MCR
|
|
//----_1110_oool_nnnn_dddd_pppp_rrr1_mmmm
|
|
bool load = _opCode & (1 << 20);
|
|
//uint8_t crn = (_opCode >> 16) & 0x0F;
|
|
uint8_t rd = (_opCode >> 12) & 0x0F;
|
|
//uint8_t crm = _opCode & 0x0F;
|
|
//uint8_t cpr = (_opCode >> 5) & 0x07;
|
|
uint8_t cp = (_opCode >> 8) & 0x0F;
|
|
//uint8_t cpOp = (_opCode >> 21) & 0x07;
|
|
|
|
if(cp != 14) {
|
|
//Any coprocessor except CP14 generates an undefined exception
|
|
#ifndef DUMMYCPU
|
|
ProcessException(GbaCpuMode::Undefined, GbaCpuVector::Undefined);
|
|
_emu->BreakIfDebugging(CpuType::Gba, BreakSource::GbaInvalidOpCode);
|
|
#endif
|
|
} else {
|
|
if(load) {
|
|
//MRC (CPU gets the previous value on the bus - nothing will actually put a value on the bus for CP14)
|
|
uint32_t value = _memoryManager->ReadCoprocessor();
|
|
if(rd == 15) {
|
|
//Reg 15 does not get modified, and only these 4 flags are updated instead
|
|
_state.CPSR.Negative = (value & (1 << 31));
|
|
_state.CPSR.Zero = (value & (1 << 30));
|
|
_state.CPSR.Carry = (value & (1 << 29));
|
|
_state.CPSR.Overflow = (value & (1 << 28));
|
|
} else {
|
|
_state.R[rd] = value;
|
|
}
|
|
} else {
|
|
//MCR (Updates value on the bus)
|
|
_memoryManager->WriteCoprocessor(_state.R[rd]);
|
|
}
|
|
Idle();
|
|
}
|
|
}
|
|
|
|
void GbaCpu::ArmInvalidOp()
|
|
{
|
|
#ifndef DUMMYCPU
|
|
ProcessException(GbaCpuMode::Undefined, GbaCpuVector::Undefined);
|
|
_emu->BreakIfDebugging(CpuType::Gba, BreakSource::GbaInvalidOpCode);
|
|
#endif
|
|
}
|
|
|
|
void GbaCpu::InitArmOpTable()
|
|
{
|
|
auto addEntry = [=](int i, Func func, ArmOpCategory category) {
|
|
_armTable[i] = func;
|
|
_armCategory[i] = category;
|
|
};
|
|
|
|
for(int i = 0; i < 0x1000; i++) {
|
|
addEntry(i, &GbaCpu::ArmInvalidOp, ArmOpCategory::InvalidOp);
|
|
}
|
|
|
|
//Data Processing / PSR Transfer (MRS, MSR)
|
|
//----_00??_????_----_----_----_????_----
|
|
for(int i = 0; i <= 0x3FF; i++) {
|
|
ArmAluOperation operation = (ArmAluOperation)((i >> 5) & 0x0F);
|
|
bool setConditionCodes = (i & 0x10) != 0;
|
|
if(!setConditionCodes && operation >= ArmAluOperation::Tst && operation <= ArmAluOperation::Cmn) {
|
|
if(i & 0x020) {
|
|
addEntry(0x000 | i, &GbaCpu::ArmMsr, ArmOpCategory::Msr);
|
|
} else {
|
|
addEntry(0x000 | i, &GbaCpu::ArmMrs, ArmOpCategory::Mrs);
|
|
}
|
|
} else {
|
|
addEntry(0x000 | i, &GbaCpu::ArmDataProcessing, ArmOpCategory::DataProcessing);
|
|
}
|
|
}
|
|
|
|
//Branch and Exchange (BX)
|
|
//----_0001_0?10_----_----_----_0??1_----
|
|
for(int i = 0; i <= 0x0F; i++) {
|
|
addEntry(0x101 | ((i & 0x03) << 1) | ((i & 0x0C) << 3), &GbaCpu::ArmBranchExchangeRegister, ArmOpCategory::BranchExchangeRegister);
|
|
}
|
|
|
|
//Branch and Branch with Link (B, BL)
|
|
//----_101?_????_----_----_----_????_----
|
|
for(int i = 0; i <= 0x1FF; i++) {
|
|
addEntry(0xA00 | i, &GbaCpu::ArmBranch, ArmOpCategory::Branch);
|
|
}
|
|
|
|
//Single Data Transfer (LDR, STR)
|
|
//----_01??_????_----_----_----_????_----
|
|
for(int i = 0; i <= 0x3FF; i++) {
|
|
addEntry(0x400 | i, &GbaCpu::ArmSingleDataTransfer, ArmOpCategory::SingleDataTransfer);
|
|
}
|
|
|
|
//Halfword and Signed Data Transfer (LDRH / STRH / LDRSB / LDRSH)
|
|
//----_000?_????_----_----_----_1??1_----
|
|
for(int i = 0; i <= 0x7F; i++) {
|
|
addEntry(((i & 0x7C) << 2) | ((i & 0x03) << 1) | 0x09, &GbaCpu::ArmSignedHalfDataTransfer, ArmOpCategory::SignedHalfDataTransfer);
|
|
}
|
|
|
|
//Block Data Transfer (LDM, STM)
|
|
//----_100?_????_----_----_----_????_----
|
|
for(int i = 0; i <= 0x1FF; i++) {
|
|
addEntry(0x800 | i, &GbaCpu::ArmBlockDataTransfer, ArmOpCategory::BlockDataTransfer);
|
|
}
|
|
|
|
//Multiply and Multiply-Accumulate (MUL, MLA)
|
|
//----_0000_0???_----_----_----_1001_----
|
|
for(int i = 0; i <= 0x07; i++) {
|
|
addEntry(0x009 | (i << 4), &GbaCpu::ArmMultiply, ArmOpCategory::Multiply);
|
|
}
|
|
|
|
//Multiply Long and Multiply-Accumulate Long (MULL,MLAL)
|
|
//----_0000_1???_----_----_----_1001_----
|
|
for(int i = 0; i <= 0x07; i++) {
|
|
addEntry(0x089 | (i << 4), &GbaCpu::ArmMultiplyLong, ArmOpCategory::MultiplyLong);
|
|
}
|
|
|
|
//Single Data Swap (SWP)
|
|
//----_0001_?0??_----_----_----_1001_----
|
|
for(int i = 0; i <= 0x07; i++) {
|
|
addEntry(0x109 | (i & 0x04) << 5 | (i & 0x03) << 4, &GbaCpu::ArmSingleDataSwap, ArmOpCategory::SingleDataSwap); //word
|
|
addEntry(0x149 | (i & 0x04) << 5 | (i & 0x03) << 4, &GbaCpu::ArmSingleDataSwap, ArmOpCategory::SingleDataSwap); //byte
|
|
}
|
|
|
|
for(int i = 0; i <= 0xFF; i++) {
|
|
addEntry(0xF00 + i, &GbaCpu::ArmSoftwareInterrupt, ArmOpCategory::SoftwareInterrupt);
|
|
}
|
|
|
|
//Coprocessor Register Transfers (MRC, MCR)
|
|
//----_1110_????_----_----_----_???1_----
|
|
for(int i = 0; i <= 0x7F; i++) {
|
|
addEntry(0xE01 | (i << 1), &GbaCpu::ArmCoprocessorTransfer, ArmOpCategory::CoprocessorTransfer);
|
|
}
|
|
}
|