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https://github.com/libretro/MesenCE.git
synced 2026-11-10 03:02:05 -10:00
SourMesen
142884b598
The NES (and AV Famicom) both ignore consecutive reads to 4016/4017 (when the reads on 2 consecutive CPU cycles). This implements that behavior when the corresponding console type is selected. These changes also simplify the DMA code, because a lot of extra code was in the DMA logic to simulate the same result. Moving this logic to the 4016/4017 reads makes the code simpler and allows it to work properly when a regular instruction reads from 4016/4017 twice in a row, too.
613 lines
23 KiB
C++
613 lines
23 KiB
C++
#include "pch.h"
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#include <random>
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#include <assert.h>
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#include "Utilities/Serializer.h"
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#include "Debugger/Debugger.h"
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#include "NES/NesCpu.h"
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#include "NES/NesPpu.h"
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#include "NES/APU/NesApu.h"
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#include "NES/NesMemoryManager.h"
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#include "NES/NesControlManager.h"
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#include "NES/NesConsole.h"
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#include "NES/NesTypes.h"
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#include "Shared/MessageManager.h"
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#include "Shared/EmuSettings.h"
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#include "Shared/Emulator.h"
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#include "Shared/MemoryOperationType.h"
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NesCpu::NesCpu(NesConsole* console)
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{
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_emu = console->GetEmulator();
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_console = console;
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_memoryManager = _console->GetMemoryManager();
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// clang-format off
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Func opTable[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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&NesCpu::BRK, &NesCpu::ORA, &NesCpu::HLT, &NesCpu::SLO, &NesCpu::NOP, &NesCpu::ORA, &NesCpu::ASL_Memory, &NesCpu::SLO, &NesCpu::PHP, &NesCpu::ORA, &NesCpu::ASL_Acc, &NesCpu::AAC, &NesCpu::NOP, &NesCpu::ORA, &NesCpu::ASL_Memory, &NesCpu::SLO, //0
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&NesCpu::BPL, &NesCpu::ORA, &NesCpu::HLT, &NesCpu::SLO, &NesCpu::NOP, &NesCpu::ORA, &NesCpu::ASL_Memory, &NesCpu::SLO, &NesCpu::CLC, &NesCpu::ORA, &NesCpu::NOP, &NesCpu::SLO, &NesCpu::NOP, &NesCpu::ORA, &NesCpu::ASL_Memory, &NesCpu::SLO, //1
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&NesCpu::JSR, &NesCpu::AND, &NesCpu::HLT, &NesCpu::RLA, &NesCpu::BIT, &NesCpu::AND, &NesCpu::ROL_Memory, &NesCpu::RLA, &NesCpu::PLP, &NesCpu::AND, &NesCpu::ROL_Acc, &NesCpu::AAC, &NesCpu::BIT, &NesCpu::AND, &NesCpu::ROL_Memory, &NesCpu::RLA, //2
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&NesCpu::BMI, &NesCpu::AND, &NesCpu::HLT, &NesCpu::RLA, &NesCpu::NOP, &NesCpu::AND, &NesCpu::ROL_Memory, &NesCpu::RLA, &NesCpu::SEC, &NesCpu::AND, &NesCpu::NOP, &NesCpu::RLA, &NesCpu::NOP, &NesCpu::AND, &NesCpu::ROL_Memory, &NesCpu::RLA, //3
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&NesCpu::RTI, &NesCpu::EOR, &NesCpu::HLT, &NesCpu::SRE, &NesCpu::NOP, &NesCpu::EOR, &NesCpu::LSR_Memory, &NesCpu::SRE, &NesCpu::PHA, &NesCpu::EOR, &NesCpu::LSR_Acc, &NesCpu::ASR, &NesCpu::JMP_Abs, &NesCpu::EOR, &NesCpu::LSR_Memory, &NesCpu::SRE, //4
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&NesCpu::BVC, &NesCpu::EOR, &NesCpu::HLT, &NesCpu::SRE, &NesCpu::NOP, &NesCpu::EOR, &NesCpu::LSR_Memory, &NesCpu::SRE, &NesCpu::CLI, &NesCpu::EOR, &NesCpu::NOP, &NesCpu::SRE, &NesCpu::NOP, &NesCpu::EOR, &NesCpu::LSR_Memory, &NesCpu::SRE, //5
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&NesCpu::RTS, &NesCpu::ADC, &NesCpu::HLT, &NesCpu::RRA, &NesCpu::NOP, &NesCpu::ADC, &NesCpu::ROR_Memory, &NesCpu::RRA, &NesCpu::PLA, &NesCpu::ADC, &NesCpu::ROR_Acc, &NesCpu::ARR, &NesCpu::JMP_Ind, &NesCpu::ADC, &NesCpu::ROR_Memory, &NesCpu::RRA, //6
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&NesCpu::BVS, &NesCpu::ADC, &NesCpu::HLT, &NesCpu::RRA, &NesCpu::NOP, &NesCpu::ADC, &NesCpu::ROR_Memory, &NesCpu::RRA, &NesCpu::SEI, &NesCpu::ADC, &NesCpu::NOP, &NesCpu::RRA, &NesCpu::NOP, &NesCpu::ADC, &NesCpu::ROR_Memory, &NesCpu::RRA, //7
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&NesCpu::NOP, &NesCpu::STA, &NesCpu::NOP, &NesCpu::SAX, &NesCpu::STY, &NesCpu::STA, &NesCpu::STX, &NesCpu::SAX, &NesCpu::DEY, &NesCpu::NOP, &NesCpu::TXA, &NesCpu::ANE, &NesCpu::STY, &NesCpu::STA, &NesCpu::STX, &NesCpu::SAX, //8
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&NesCpu::BCC, &NesCpu::STA, &NesCpu::HLT, &NesCpu::SHAZ, &NesCpu::STY, &NesCpu::STA, &NesCpu::STX, &NesCpu::SAX, &NesCpu::TYA, &NesCpu::STA, &NesCpu::TXS, &NesCpu::TAS, &NesCpu::SHY, &NesCpu::STA, &NesCpu::SHX, &NesCpu::SHAA,//9
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&NesCpu::LDY, &NesCpu::LDA, &NesCpu::LDX, &NesCpu::LAX, &NesCpu::LDY, &NesCpu::LDA, &NesCpu::LDX, &NesCpu::LAX, &NesCpu::TAY, &NesCpu::LDA, &NesCpu::TAX, &NesCpu::ATX, &NesCpu::LDY, &NesCpu::LDA, &NesCpu::LDX, &NesCpu::LAX, //A
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&NesCpu::BCS, &NesCpu::LDA, &NesCpu::HLT, &NesCpu::LAX, &NesCpu::LDY, &NesCpu::LDA, &NesCpu::LDX, &NesCpu::LAX, &NesCpu::CLV, &NesCpu::LDA, &NesCpu::TSX, &NesCpu::LAS, &NesCpu::LDY, &NesCpu::LDA, &NesCpu::LDX, &NesCpu::LAX, //B
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&NesCpu::CPY, &NesCpu::CPA, &NesCpu::NOP, &NesCpu::DCP, &NesCpu::CPY, &NesCpu::CPA, &NesCpu::DEC, &NesCpu::DCP, &NesCpu::INY, &NesCpu::CPA, &NesCpu::DEX, &NesCpu::AXS, &NesCpu::CPY, &NesCpu::CPA, &NesCpu::DEC, &NesCpu::DCP, //C
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&NesCpu::BNE, &NesCpu::CPA, &NesCpu::HLT, &NesCpu::DCP, &NesCpu::NOP, &NesCpu::CPA, &NesCpu::DEC, &NesCpu::DCP, &NesCpu::CLD, &NesCpu::CPA, &NesCpu::NOP, &NesCpu::DCP, &NesCpu::NOP, &NesCpu::CPA, &NesCpu::DEC, &NesCpu::DCP, //D
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&NesCpu::CPX, &NesCpu::SBC, &NesCpu::NOP, &NesCpu::ISB, &NesCpu::CPX, &NesCpu::SBC, &NesCpu::INC, &NesCpu::ISB, &NesCpu::INX, &NesCpu::SBC, &NesCpu::NOP, &NesCpu::SBC, &NesCpu::CPX, &NesCpu::SBC, &NesCpu::INC, &NesCpu::ISB, //E
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&NesCpu::BEQ, &NesCpu::SBC, &NesCpu::HLT, &NesCpu::ISB, &NesCpu::NOP, &NesCpu::SBC, &NesCpu::INC, &NesCpu::ISB, &NesCpu::SED, &NesCpu::SBC, &NesCpu::NOP, &NesCpu::ISB, &NesCpu::NOP, &NesCpu::SBC, &NesCpu::INC, &NesCpu::ISB //F
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};
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typedef NesAddrMode M;
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NesAddrMode addrMode[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //0
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//1
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M::Other,M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //2
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//3
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //4
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//5
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Ind, M::Abs, M::Abs, M::Abs, //6
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//7
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //8
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M::Rel, M::IndYW, M::None, M::Other, M::ZeroX, M::ZeroX, M::ZeroY, M::ZeroY, M::Imp, M::AbsYW,M::Imp, M::Other,M::Other,M::AbsXW,M::Other,M::Other,//9
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //A
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M::Rel, M::IndY, M::None, M::IndY, M::ZeroX, M::ZeroX, M::ZeroY, M::ZeroY, M::Imp, M::AbsY, M::Imp, M::AbsY, M::AbsX, M::AbsX, M::AbsY, M::AbsY, //B
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //C
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//D
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //E
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//F
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};
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// clang-format on
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memcpy(_opTable, opTable, sizeof(opTable));
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memcpy(_addrMode, addrMode, sizeof(addrMode));
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_instAddrMode = NesAddrMode::None;
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_state = {};
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_operand = 0;
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_spriteDmaTransfer = false;
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_spriteDmaOffset = 0;
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_needHalt = false;
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_ppuOffset = 0;
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_startClockCount = 6;
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_endClockCount = 6;
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_masterClock = 0;
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_dmcDmaRunning = false;
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_cpuWrite = false;
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_irqMask = 0;
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_state = {};
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_prevRunIrq = false;
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_runIrq = false;
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}
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void NesCpu::Reset(bool softReset, ConsoleRegion region)
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{
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_state.NmiFlag = false;
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_state.IrqFlag = 0;
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_spriteDmaTransfer = false;
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_spriteDmaOffset = 0;
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_needHalt = false;
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_dmcDmaRunning = false;
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_abortDmcDma = false;
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_isDmcDmaRead = false;
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_cpuWrite = false;
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_crashed = false;
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//Use _memoryManager->Read() directly to prevent clocking the PPU/APU when setting PC at reset
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_state.PC = _memoryManager->Read(NesCpu::ResetVector) | _memoryManager->Read(NesCpu::ResetVector + 1) << 8;
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if(softReset) {
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SetFlags(PSFlags::Interrupt);
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_state.SP -= 0x03;
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} else {
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//Used by NSF code to disable Frame Counter & DMC interrupts
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_irqMask = 0xFF;
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_state.A = 0;
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_state.SP = 0xFD;
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_state.X = 0;
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_state.Y = 0;
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_state.PS = PSFlags::Interrupt;
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_runIrq = false;
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}
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uint8_t ppuDivider;
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uint8_t cpuDivider;
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switch(region) {
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default:
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case ConsoleRegion::Ntsc:
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ppuDivider = 4;
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cpuDivider = 12;
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break;
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case ConsoleRegion::Pal:
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ppuDivider = 5;
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cpuDivider = 16;
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break;
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case ConsoleRegion::Dendy:
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ppuDivider = 5;
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cpuDivider = 15;
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break;
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}
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_state.CycleCount = (uint64_t)-1;
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_masterClock = 0;
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uint8_t cpuOffset = 0;
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if(_console->GetNesConfig().RandomizeCpuPpuAlignment) {
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std::random_device rd;
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std::mt19937 mt(rd());
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std::uniform_int_distribution<> distPpu(0, ppuDivider - 1);
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std::uniform_int_distribution<> distCpu(0, cpuDivider - 1);
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_ppuOffset = distPpu(mt);
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cpuOffset += distCpu(mt);
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string ppuAlignment = " PPU: " + std::to_string(_ppuOffset) + "/" + std::to_string(ppuDivider - 1);
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string cpuAlignment = " CPU: " + std::to_string(cpuOffset) + "/" + std::to_string(cpuDivider - 1);
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MessageManager::Log("CPU/PPU alignment -" + ppuAlignment + cpuAlignment);
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} else {
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_ppuOffset = 1;
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cpuOffset = 0;
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}
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_masterClock += cpuDivider + cpuOffset;
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//The CPU takes 8 cycles before it starts executing the ROM's code after a reset/power up
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for(int i = 0; i < 8; i++) {
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StartCpuCycle(true);
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EndCpuCycle(true);
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}
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}
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void NesCpu::Exec()
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{
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#ifndef DUMMYCPU
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_emu->ProcessInstruction<CpuType::Nes>();
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#endif
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uint8_t opCode = GetOPCode();
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_instAddrMode = _addrMode[opCode];
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_operand = FetchOperand();
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(this->*_opTable[opCode])();
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if(_prevRunIrq || _prevNeedNmi) {
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IRQ();
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}
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}
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void NesCpu::IRQ()
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{
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#ifndef DUMMYCPU
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uint16_t originalPc = PC();
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if(_console->GetRegion() == ConsoleRegion::Pal) {
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//On PAL, IRQ/NMI sequence also checks for DMA on the first read
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ProcessPendingDma(_state.PC, MemoryOperationType::ExecOpCode);
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}
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#endif
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DummyPcRead(); //fetch opcode (and discard it - $00 (BRK) is forced into the opcode register instead)
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DummyPcRead(); //read next instruction byte (actually the same as above, since PC increment is suppressed. Also discarded.)
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Push((uint16_t)(PC()));
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if(_needNmi) {
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_needNmi = false;
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Push((uint8_t)(PS() | PSFlags::Reserved));
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SetFlags(PSFlags::Interrupt);
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SetPC(MemoryReadWord(NesCpu::NMIVector));
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#ifndef DUMMYCPU
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_emu->ProcessInterrupt<CpuType::Nes>(originalPc, _state.PC, true);
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#endif
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} else {
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Push((uint8_t)(PS() | PSFlags::Reserved));
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SetFlags(PSFlags::Interrupt);
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SetPC(MemoryReadWord(NesCpu::IRQVector));
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#ifndef DUMMYCPU
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_emu->ProcessInterrupt<CpuType::Nes>(originalPc, _state.PC, false);
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#endif
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}
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}
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void NesCpu::BRK()
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{
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Push((uint16_t)(PC() + 1));
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uint8_t flags = PS() | PSFlags::Break | PSFlags::Reserved;
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if(_needNmi) {
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_needNmi = false;
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Push((uint8_t)flags);
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SetFlags(PSFlags::Interrupt);
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SetPC(MemoryReadWord(NesCpu::NMIVector));
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} else {
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Push((uint8_t)flags);
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SetFlags(PSFlags::Interrupt);
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SetPC(MemoryReadWord(NesCpu::IRQVector));
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}
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//Ensure we don't start an NMI right after running a BRK instruction (first instruction in IRQ handler must run first - needed for nmi_and_brk test)
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_prevNeedNmi = false;
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}
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void NesCpu::MemoryWrite(uint16_t addr, uint8_t value, MemoryOperationType operationType)
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{
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#ifdef DUMMYCPU
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LogMemoryOperation(addr, value, operationType);
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#else
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_cpuWrite = true;
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StartCpuCycle(false);
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_memoryManager->Write(addr, value, operationType);
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EndCpuCycle(false);
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_cpuWrite = false;
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#endif
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}
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uint8_t NesCpu::MemoryRead(uint16_t addr, MemoryOperationType operationType)
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{
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#ifdef DUMMYCPU
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uint8_t value = _memoryManager->DebugRead(addr);
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LogMemoryOperation(addr, value, operationType);
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return value;
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#else
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ProcessPendingDma(addr, operationType);
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StartCpuCycle(true);
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uint8_t value = _memoryManager->Read(addr, operationType);
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EndCpuCycle(true);
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return value;
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#endif
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}
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uint16_t NesCpu::FetchOperand()
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{
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switch(_instAddrMode) {
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case NesAddrMode::Acc:
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case NesAddrMode::Imp: DummyPcRead(); return 0;
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case NesAddrMode::Imm:
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case NesAddrMode::Rel: return GetImmediate();
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case NesAddrMode::Zero: return GetZeroAddr();
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case NesAddrMode::ZeroX: return GetZeroXAddr();
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case NesAddrMode::ZeroY: return GetZeroYAddr();
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case NesAddrMode::Ind: return GetIndAddr();
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case NesAddrMode::IndX: return GetIndXAddr();
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case NesAddrMode::IndY: return GetIndYAddr(false);
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case NesAddrMode::IndYW: return GetIndYAddr(true);
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case NesAddrMode::Abs: return GetAbsAddr();
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case NesAddrMode::AbsX: return GetAbsXAddr(false);
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case NesAddrMode::AbsXW: return GetAbsXAddr(true);
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case NesAddrMode::AbsY: return GetAbsYAddr(false);
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case NesAddrMode::AbsYW: return GetAbsYAddr(true);
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case NesAddrMode::Other: return 0; //Do nothing, op is handled specifically
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default: return 0;
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}
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}
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void NesCpu::EndCpuCycle(bool forRead)
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{
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_masterClock += forRead ? (_endClockCount + 1) : (_endClockCount - 1);
|
|
_console->GetPpu()->Run(_masterClock - _ppuOffset);
|
|
|
|
//"The internal signal goes high during φ1 of the cycle that follows the one where the edge is detected,
|
|
//and stays high until the NMI has been handled. "
|
|
_prevNeedNmi = _needNmi;
|
|
|
|
//"This edge detector polls the status of the NMI line during φ2 of each CPU cycle (i.e., during the
|
|
//second half of each cycle) and raises an internal signal if the input goes from being high during
|
|
//one cycle to being low during the next"
|
|
if(!_prevNmiFlag && _state.NmiFlag) {
|
|
_needNmi = true;
|
|
}
|
|
_prevNmiFlag = _state.NmiFlag;
|
|
|
|
//"it's really the status of the interrupt lines at the end of the second-to-last cycle that matters."
|
|
//Keep the irq lines values from the previous cycle. The before-to-last cycle's values will be used
|
|
_prevRunIrq = _runIrq;
|
|
_runIrq = ((_state.IrqFlag & _irqMask) > 0 && !CheckFlag(PSFlags::Interrupt));
|
|
}
|
|
|
|
void NesCpu::StartCpuCycle(bool forRead)
|
|
{
|
|
_masterClock += forRead ? (_startClockCount - 1) : (_startClockCount + 1);
|
|
_console->GetPpu()->Run(_masterClock - _ppuOffset);
|
|
_state.CycleCount++;
|
|
_console->ProcessCpuClock();
|
|
}
|
|
|
|
void NesCpu::ProcessPendingDma(uint16_t readAddress, MemoryOperationType opType)
|
|
{
|
|
if(!_needHalt) {
|
|
return;
|
|
}
|
|
|
|
if(_console->GetRegion() == ConsoleRegion::Pal && opType != MemoryOperationType::ExecOpCode) {
|
|
//On PAL, DMA can only start when the CPU attempts to read the opcode for the next instruction
|
|
//This also avoids the bit deletions that can happen because of DMA reads on NTSC
|
|
return;
|
|
}
|
|
|
|
uint16_t prevReadAddress = readAddress;
|
|
bool enableInternalRegReads = (readAddress & 0xFFE0) == 0x4000;
|
|
_needHalt = false;
|
|
|
|
StartCpuCycle(true);
|
|
_memoryManager->Read(readAddress, MemoryOperationType::DmaRead);
|
|
EndCpuCycle(true);
|
|
|
|
if(_abortDmcDma) {
|
|
_dmcDmaRunning = false;
|
|
_abortDmcDma = false;
|
|
|
|
if(!_spriteDmaTransfer) {
|
|
//If DMC DMA was cancelled and OAM DMA isn't about to start,
|
|
//stop processing DMA entirely. Otherwise, OAM DMA needs to run,
|
|
//so the DMA process has to continue.
|
|
_needDummyRead = false;
|
|
return;
|
|
}
|
|
}
|
|
|
|
uint16_t spriteDmaCounter = 0;
|
|
uint8_t spriteReadAddr = 0;
|
|
uint8_t readValue = 0;
|
|
|
|
auto processCycle = [this] {
|
|
//Sprite DMA cycles count as halt/dummy cycles for the DMC DMA when both run at the same time
|
|
if(_abortDmcDma) {
|
|
_dmcDmaRunning = false;
|
|
_abortDmcDma = false;
|
|
_needDummyRead = false;
|
|
_needHalt = false;
|
|
} else if(_needHalt) {
|
|
_needHalt = false;
|
|
} else if(_needDummyRead) {
|
|
_needDummyRead = false;
|
|
}
|
|
StartCpuCycle(true);
|
|
};
|
|
|
|
while(_dmcDmaRunning || _spriteDmaTransfer) {
|
|
bool getCycle = (_state.CycleCount & 0x01) == 0;
|
|
if(getCycle) {
|
|
if(_dmcDmaRunning && !_needHalt && !_needDummyRead) {
|
|
//DMC DMA is ready to read a byte (both halt and dummy read cycles were performed before this)
|
|
processCycle();
|
|
_isDmcDmaRead = true; //used by debugger to distinguish between dmc and oam/dummy dma reads
|
|
readValue = ProcessDmaRead(_console->GetApu()->GetDmcReadAddress(), prevReadAddress, enableInternalRegReads);
|
|
_isDmcDmaRead = false;
|
|
EndCpuCycle(true);
|
|
_dmcDmaRunning = false;
|
|
_abortDmcDma = false;
|
|
_console->GetApu()->SetDmcReadBuffer(readValue);
|
|
//On later CPUs, a DMC DMA may start immediately after another DMC DMA. We need to
|
|
//call ProcessPendingDma again to handle the behavior of the halt cycle. This
|
|
//allows the second DMA to clock the joypads again on NES-behavior consoles.
|
|
//Fixes dmc_dma_start_test_v2 case C with sample duplication turned on.
|
|
if(_needHalt) {
|
|
NoInlineProcessPendingDma(readAddress, opType);
|
|
}
|
|
} else if(_spriteDmaTransfer) {
|
|
//DMC DMA is not running, or not ready, run sprite DMA
|
|
processCycle();
|
|
readValue = ProcessDmaRead(_spriteDmaOffset * 0x100 + spriteReadAddr, prevReadAddress, enableInternalRegReads);
|
|
EndCpuCycle(true);
|
|
spriteReadAddr++;
|
|
spriteDmaCounter++;
|
|
} else {
|
|
//DMC DMA is running, but not ready (need halt/dummy read) and sprite DMA isn't runnnig, perform a dummy read
|
|
assert(_needHalt || _needDummyRead);
|
|
processCycle();
|
|
_memoryManager->Read(readAddress, MemoryOperationType::DmaRead);
|
|
EndCpuCycle(true);
|
|
}
|
|
} else {
|
|
if(_spriteDmaTransfer && (spriteDmaCounter & 0x01)) {
|
|
//Sprite DMA write cycle (only do this if a sprite dma read was performed last cycle)
|
|
processCycle();
|
|
_memoryManager->Write(0x2004, readValue, MemoryOperationType::DmaWrite);
|
|
EndCpuCycle(true);
|
|
spriteDmaCounter++;
|
|
if(spriteDmaCounter == 0x200) {
|
|
_spriteDmaTransfer = false;
|
|
}
|
|
} else {
|
|
//Align to read cycle before starting sprite DMA (or align to perform DMC read)
|
|
processCycle();
|
|
_memoryManager->Read(readAddress, MemoryOperationType::DmaRead);
|
|
EndCpuCycle(true);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
uint8_t NesCpu::ProcessDmaRead(uint16_t addr, uint16_t& prevReadAddress, bool enableInternalRegReads)
|
|
{
|
|
//This is to reproduce a CPU bug that can occur during DMA which can cause the 2A03 to read from
|
|
//its internal registers (4015, 4016, 4017) at the same time as the DMA unit reads a byte from
|
|
//the bus. This bug occurs if the CPU is halted while it's reading a value in the $4000-$401F range.
|
|
//
|
|
//This has a number of side effects:
|
|
// -It can cause a read of $4015 to occur without the program's knowledge, which would clear the frame counter's IRQ flag
|
|
// -It can cause additional bit deletions while reading the input (e.g more than the DMC glitch usually causes)
|
|
// -It can also *prevent* bit deletions from occurring at all in another scenario
|
|
// -It can replace/corrupt the byte that the DMA is reading, causing DMC to play the wrong sample
|
|
|
|
uint8_t val;
|
|
if(!enableInternalRegReads) {
|
|
if(addr >= 0x4015 && addr <= 0x401A) {
|
|
//The readable 2A03 registers ($4015-$4017 and, in test mode, $4018-$401A) can't be seen by DMA in this case.
|
|
val = _memoryManager->GetOpenBus();
|
|
} else {
|
|
val = _memoryManager->Read(addr, MemoryOperationType::DmaRead);
|
|
}
|
|
prevReadAddress = addr;
|
|
return val;
|
|
} else {
|
|
//This glitch causes the CPU to read from the internal APU/Input registers
|
|
//regardless of the address the DMA unit is trying to read
|
|
uint16_t internalAddr = 0x4000 | (addr & 0x1F);
|
|
bool isSameAddress = internalAddr == addr;
|
|
|
|
switch(internalAddr) {
|
|
case 0x4015:
|
|
//Reads to $4015 don't update the value on the external bus
|
|
//Only the CPU's internal bus is updated
|
|
val = _memoryManager->Read<NesCpuBusType::Internal>(internalAddr, MemoryOperationType::DmaRead);
|
|
if(!isSameAddress) {
|
|
//Also trigger a read from the actual address the CPU was supposed to read from (external bus)
|
|
_memoryManager->Read<NesCpuBusType::External>(addr, MemoryOperationType::DmaRead);
|
|
}
|
|
break;
|
|
|
|
case 0x4016:
|
|
case 0x4017:
|
|
val = _memoryManager->Read(internalAddr, MemoryOperationType::DmaRead);
|
|
|
|
if(!isSameAddress) {
|
|
//The DMA unit is reading from a different address, read from it too (external bus)
|
|
uint8_t obMask = ((NesControlManager*)_console->GetControlManager())->GetOpenBusMask(internalAddr - 0x4016);
|
|
uint8_t externalValue = _memoryManager->Read(addr, MemoryOperationType::DmaRead);
|
|
|
|
// Joypads stop driving the bus later than cartridge ROM, so joypad bits win on open bus.
|
|
_memoryManager->SetOpenBus<NesCpuBusType::External>((externalValue & obMask) | (val & ~obMask));
|
|
|
|
//The value seen by the CPU is the bus conflict between the driven joypad bits and the DMA read value.
|
|
//The DMA read may come from an address that is open bus and thus does not drive bits, which should not
|
|
//cause a bus conflict. However, because we read the joypad first before doing the DMA, the joypad read
|
|
//updated open bus, and so any open bus bits in the DMA read will match the joypad read value. So, even
|
|
//if we simulate a bus conflict on these bits, because they are the same, it's the same as taking the
|
|
//joypad's value.
|
|
//For this bus conflict, we keep the external value for all open bus pins on the 4016/4017 port, and we
|
|
//AND all other bits together
|
|
val = (externalValue & obMask) | ((val & ~obMask) & (externalValue & ~obMask));
|
|
}
|
|
break;
|
|
|
|
//TODO if test mode is enabled, handle test mode registers here (and consider making the test mode check earlier in this
|
|
//function check for whether test mode is actually enabled).
|
|
|
|
default:
|
|
val = _memoryManager->Read(addr, MemoryOperationType::DmaRead);
|
|
break;
|
|
}
|
|
|
|
prevReadAddress = internalAddr;
|
|
return val;
|
|
}
|
|
}
|
|
|
|
void NesCpu::RunDMATransfer(uint8_t offsetValue)
|
|
{
|
|
_spriteDmaTransfer = true;
|
|
_spriteDmaOffset = offsetValue;
|
|
_needHalt = true;
|
|
}
|
|
|
|
void NesCpu::StartDmcTransfer()
|
|
{
|
|
_dmcDmaRunning = true;
|
|
_needDummyRead = true;
|
|
_needHalt = true;
|
|
}
|
|
|
|
void NesCpu::StopDmcTransfer()
|
|
{
|
|
if(_dmcDmaRunning) {
|
|
if(_needHalt) {
|
|
//If interrupted before the halt cycle starts, cancel DMA completely
|
|
//This can happen when a write prevents the DMA from starting after being queued
|
|
_dmcDmaRunning = false;
|
|
_needDummyRead = false;
|
|
_needHalt = false;
|
|
} else {
|
|
//Abort DMA if possible (this only appears to be possible if done within the first cycle of DMA)
|
|
_abortDmcDma = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
void NesCpu::SetMasterClockDivider(ConsoleRegion region)
|
|
{
|
|
switch(region) {
|
|
default:
|
|
case ConsoleRegion::Ntsc:
|
|
_startClockCount = 6;
|
|
_endClockCount = 6;
|
|
break;
|
|
|
|
case ConsoleRegion::Pal:
|
|
_startClockCount = 8;
|
|
_endClockCount = 8;
|
|
break;
|
|
|
|
case ConsoleRegion::Dendy:
|
|
_startClockCount = 7;
|
|
_endClockCount = 8;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void NesCpu::HLT()
|
|
{
|
|
//Freeze the CPU, implemented by jumping back and re-executing this op infinitely (for performance reasons)
|
|
_state.PC -= 1;
|
|
|
|
//Prevent IRQ/NMI
|
|
_prevRunIrq = false;
|
|
_prevNeedNmi = false;
|
|
|
|
#if !defined(DUMMYCPU)
|
|
if(!_crashed) {
|
|
_crashed = true;
|
|
MessageManager::DisplayMessage("Error", "GameCrash", "Invalid OP code - CPU crashed.");
|
|
_emu->BreakIfDebugging(CpuType::Nes, BreakSource::NesBreakOnCpuCrash);
|
|
|
|
if(!_emu->IsDebugging() && _console->GetRomFormat() == RomFormat::Nsf) {
|
|
//For NSF files, reset cpu if it ever crashes
|
|
_emu->Reset();
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void NesCpu::Serialize(Serializer& s)
|
|
{
|
|
SV(_state.PC);
|
|
SV(_state.SP);
|
|
SV(_state.PS);
|
|
SV(_state.A);
|
|
SV(_state.X);
|
|
SV(_state.Y);
|
|
SV(_state.CycleCount);
|
|
|
|
if(s.GetFormat() != SerializeFormat::Map) {
|
|
//Hide these entries from the Lua API
|
|
SV(_state.NmiFlag);
|
|
SV(_state.IrqFlag);
|
|
SV(_dmcDmaRunning);
|
|
SV(_abortDmcDma);
|
|
SV(_spriteDmaTransfer);
|
|
SV(_needDummyRead);
|
|
SV(_needHalt);
|
|
SV(_startClockCount);
|
|
SV(_endClockCount);
|
|
SV(_ppuOffset);
|
|
SV(_masterClock);
|
|
SV(_prevNeedNmi);
|
|
SV(_prevNmiFlag);
|
|
SV(_needNmi);
|
|
SV(_crashed);
|
|
}
|
|
} |