2017-08-26 19:45:16 +00:00
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2019-03-21 11:48:05 +00:00
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// PC-9821 PCIバス
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2017-08-26 19:45:16 +00:00
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#if defined(SUPPORT_PC9821)
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2018-09-27 14:35:54 +00:00
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#if defined(SUPPORT_PCI)
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#define PCI_DEVICES_MAX 32
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#define PCI_PCMC_82434LX 0
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#define PCI_PCMC_82441FX 1
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#define PCI_PCMC_WILDCAT 2
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#define PCI_GETCFGREG_B(reg, ofs) (*((UINT8*)((reg) + (ofs))))
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#define PCI_GETCFGREG_W(reg, ofs) (*((UINT16*)((reg) + (ofs))))
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#define PCI_GETCFGREG_D(reg, ofs) (*((UINT32*)((reg) + (ofs))))
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#define PCI_SETCFGREG_B(reg, ofs, value) (PCI_GETCFGREG_B(reg, ofs) = value)
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#define PCI_SETCFGREG_W(reg, ofs, value) (PCI_GETCFGREG_W(reg, ofs) = value)
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#define PCI_SETCFGREG_D(reg, ofs, value) (PCI_GETCFGREG_D(reg, ofs) = value)
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#define PCI_SETCFGREG_B_MASK(reg, ofs, value, mask) (PCI_GETCFGREG_B(reg, ofs) = (PCI_GETCFGREG_B(reg, ofs) & mask) | (value & ~mask))
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#define PCI_SETCFGREG_W_MASK(reg, ofs, value, mask) (PCI_GETCFGREG_W(reg, ofs) = (PCI_GETCFGREG_W(reg, ofs) & mask) | (value & ~mask))
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#define PCI_SETCFGREG_D_MASK(reg, ofs, value, mask) (PCI_GETCFGREG_D(reg, ofs) = (PCI_GETCFGREG_D(reg, ofs) & mask) | (value & ~mask))
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2019-03-21 11:48:05 +00:00
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// コンフィギュレーションレジスタ変更時に呼ばれる。
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2018-09-27 14:35:54 +00:00
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typedef void (*PCIREGWCB)(UINT32 devNumber, UINT8 funcNumber, UINT8 cfgregOffset, UINT8 sizeinbytes, UINT32 value);
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#pragma pack(1)
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2019-03-21 11:48:05 +00:00
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// PCI IRQ ルーティングテーブル エントリ
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2017-08-26 19:45:16 +00:00
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typedef struct {
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2018-09-27 14:35:54 +00:00
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UINT8 busnumber;
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UINT8 devicenumber;
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UINT8 link4intA;
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UINT16 irqmap4intA;
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UINT8 link4intB;
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UINT16 irqmap4intB;
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UINT8 link4intC;
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UINT16 irqmap4intC;
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UINT8 link4intD;
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UINT16 irqmap4intD;
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UINT8 slot;
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UINT8 reserved;
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} _PCIPNP_IRQTBL_ENTRY, *PCIPNP_IRQTBL_ENTRY;
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#pragma pack()
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2019-03-21 11:48:05 +00:00
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// PCI IRQ ルーティングテーブル
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2018-09-27 14:35:54 +00:00
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typedef struct {
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UINT16 datacount;
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union{
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_PCIPNP_IRQTBL_ENTRY data[PCI_DEVICES_MAX];
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UINT8 data8[PCI_DEVICES_MAX * sizeof(_PCIPNP_IRQTBL_ENTRY)];
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};
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} _PCIPNP_IRQTBL, *PCIPNP_IRQTBL;
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// Configuration Space Header
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typedef struct {
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UINT16 vendorID;
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UINT16 deviceID;
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UINT16 command;
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UINT16 status;
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UINT8 revisionID;
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UINT8 classcode[3];
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UINT8 cachelinesize;
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UINT8 latencytimer;
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UINT8 headertype;
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UINT8 BIST;
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UINT32 baseaddrregs[6];
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UINT32 cardbusCISptr;
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UINT16 subsysventorID;
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UINT16 subsysID;
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UINT32 expROMbaseaddr;
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UINT16 capsptr;
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UINT8 reserved1[3];
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UINT32 reserved2;
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UINT8 interruptline;
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UINT8 interruptpin;
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UINT8 min_gnt;
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UINT8 max_lat;
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} _PCICSH, *PCICSH;
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2019-03-21 11:48:05 +00:00
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// PCIデバイス
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2018-09-27 14:35:54 +00:00
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typedef struct {
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UINT8 enable;
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PCIREGWCB regwfn;
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2019-03-21 11:48:05 +00:00
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UINT8 slot; // PCIスロット番号(オンボードは0)
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UINT8 skipirqtbl; // 0でない場合はルーティングテーブルに登録しない
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2018-09-27 14:35:54 +00:00
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union{
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UINT8 cfgreg8[0x100];
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_PCICSH header; // Type 00h Configuration Space Header
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};
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2019-03-21 11:48:05 +00:00
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// ビットを立てたところはリードオンリ
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2018-09-27 14:35:54 +00:00
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union{
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UINT8 cfgreg8rom[0x100];
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_PCICSH headerrom; // Type 00h Configuration Space Header
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};
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} _PCIDEVICE, *PCIDEVICE;
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// PCI
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typedef struct {
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UINT8 enable;
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UINT8 reg_cse; // CONFIGURATION SPACE ENABLE REGISTER
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UINT8 reg_trc; // TURBO-RESET CONTROL REGISTER
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UINT8 reg_fwd; // FORWARD REGISTER
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UINT8 reg_cms; // Configuration Mechanism Select
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UINT32 reg32_caddr; // CONFIGURATION ADDRESS REGISTER
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2019-03-21 11:48:05 +00:00
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_PCIDEVICE devices[PCI_DEVICES_MAX]; // PCIデバイス
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2017-08-26 19:45:16 +00:00
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UINT8 membankd0;
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2018-09-27 14:35:54 +00:00
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UINT8 membankd8;
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UINT8 biosrom[0x8000];
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UINT8 biosromtmp[0x8000];
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OEMCHAR biosname[16];
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UINT8 usebios32;
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UINT32 bios32svcdir;
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UINT32 bios32entrypoint;
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_PCIPNP_IRQTBL biosdata;
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UINT16 allirqbitmap;
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UINT8 unkreg[4][256];
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UINT8 unkreg_bank1;
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UINT8 unkreg_bank2;
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2017-08-26 19:45:16 +00:00
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} _PCIDEV, *PCIDEV;
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2018-09-27 14:35:54 +00:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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void IOOUTCALL pcidev_w8_0xcfc(UINT port, UINT8 value);
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void IOOUTCALL pcidev_w16_0xcfc(UINT port, UINT16 value);
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void IOOUTCALL pcidev_w32(UINT port, UINT32 value);
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UINT8 IOOUTCALL pcidev_r8_0xcfc(UINT port);
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UINT16 IOOUTCALL pcidev_r16_0xcfc(UINT port);
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UINT32 IOOUTCALL pcidev_r32(UINT port);
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void pcidev_basereset();
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void pcidev_reset(const NP2CFG *pConfig);
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void pcidev_bind(void);
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void pcidev_updateRoutingTable();
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void pcidev_updateBIOS32data();
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#ifdef __cplusplus
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}
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#endif
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#else
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typedef struct {
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UINT32 base;
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UINT8 membankd0;
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} _PCIDEV, *PCIDEV;
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2017-08-26 19:45:16 +00:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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void IOOUTCALL pcidev_w32(UINT port, UINT32 value);
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UINT32 IOOUTCALL pcidev_r32(UINT port);
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void pcidev_reset(const NP2CFG *pConfig);
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void pcidev_bind(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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2018-09-27 14:35:54 +00:00
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#endif
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