From 00bd1c1978456ef216d851d7c9601f6a0686db5a Mon Sep 17 00:00:00 2001
From: jpd002 <jpd002@b36208d7-6611-0410-8bec-b1987f11c4a2>
Date: Wed, 28 Mar 2007 00:43:39 +0000
Subject: [PATCH] git-svn-id: http://svn.purei.org/purei/trunk@137
 b36208d7-6611-0410-8bec-b1987f11c4a2

---
 Source/MipsAssemblerDefinitions.cpp | 37 ++++++++++++++++++++
 tests/SLTU.xml                      | 54 +++++++++++++++++++++++++++++
 2 files changed, 91 insertions(+)
 create mode 100644 tests/SLTU.xml

diff --git a/Source/MipsAssemblerDefinitions.cpp b/Source/MipsAssemblerDefinitions.cpp
index fc845d46..f808cb60 100644
--- a/Source/MipsAssemblerDefinitions.cpp
+++ b/Source/MipsAssemblerDefinitions.cpp
@@ -45,6 +45,41 @@ namespace MipsAssemblerDefinitions
         AssemblerFunctionType m_Assembler;
     };
 
+    //RdRsRt Parser
+    //-----------------------------
+    struct RdRsRt
+    {
+        typedef void (CMIPSAssembler::*AssemblerFunctionType) (unsigned int, unsigned int, unsigned int);
+
+        RdRsRt(AssemblerFunctionType Assembler) :
+        m_Assembler(Assembler)
+        {
+            
+        }
+
+        void operator ()(tokenizer<>& Tokens, tokenizer<>::iterator& itToken, CMIPSAssembler* pAssembler)
+        {
+            unsigned int nRT, nRS, nRD;
+
+            if(itToken == Tokens.end()) throw exception();
+            nRD = CMIPSAssembler::GetRegisterIndex((*(++itToken)).c_str());
+
+            if(itToken == Tokens.end()) throw exception();
+            nRS = CMIPSAssembler::GetRegisterIndex((*(++itToken)).c_str());
+
+            if(itToken == Tokens.end()) throw exception();
+            nRT = CMIPSAssembler::GetRegisterIndex((*(++itToken)).c_str());
+
+            if(nRT == -1) throw exception();
+            if(nRS == -1) throw exception();
+            if(nRD == -1) throw exception();
+
+            bind(m_Assembler, pAssembler, _1, _2, _3)(nRD, nRS, nRT);
+        }
+
+        AssemblerFunctionType m_Assembler;
+    };
+
     //RtImm Parser
     //-----------------------------
     struct RtImm
@@ -134,6 +169,7 @@ namespace MipsAssemblerDefinitions
     SpecInstruction<RtRsImm>    Instruction_ADDIU   = SpecInstruction<RtRsImm>("ADDIU", RtRsImm(&CMIPSAssembler::ADDIU));
     SpecInstruction<RtImm>      Instruction_LUI     = SpecInstruction<RtImm>("LUI", RtImm(&CMIPSAssembler::LUI));
     SpecInstruction<RtRsSa>     Instruction_SLL     = SpecInstruction<RtRsSa>("SLL", RtRsSa(&CMIPSAssembler::SLL));
+    SpecInstruction<RdRsRt>     Instruction_SLTU    = SpecInstruction<RdRsRt>("SLTU", RdRsRt(&CMIPSAssembler::SLTU));
     SpecInstruction<RtRsSa>     Instruction_SRA     = SpecInstruction<RtRsSa>("SRA", RtRsSa(&CMIPSAssembler::SRA));
 
     Instruction* g_Instructions[] = 
@@ -141,6 +177,7 @@ namespace MipsAssemblerDefinitions
         &Instruction_ADDIU,
         &Instruction_LUI,
         &Instruction_SLL,
+        &Instruction_SLTU,
         &Instruction_SRA,
         NULL,
     };
diff --git a/tests/SLTU.xml b/tests/SLTU.xml
new file mode 100644
index 00000000..9ca16a89
--- /dev/null
+++ b/tests/SLTU.xml
@@ -0,0 +1,54 @@
+<Test>
+	<Inputs>
+
+		<!-- Less Than -->
+		<ValueSet InputId="0">
+			<Register Name="T0" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
+			<Register Name="T1" Value0="0x00000001" />
+		</ValueSet>
+
+		<!-- Greater Than -->
+		<ValueSet InputId="1">
+			<Register Name="T0" Value0="0x00000001" />
+			<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
+		</ValueSet>
+
+		<!-- Equal -->
+		<ValueSet InputId="2">
+			<Register Name="T0" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
+			<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
+		</ValueSet>
+
+	</Inputs>
+
+	<Instances>
+
+		<Instance Id="0">
+			SLTU T2, T1, T0
+		</Instance>
+
+	</Instances>
+
+	<Outputs>
+
+		<ValueSet InputId="0" InstanceId="0">
+			<Register Name="T0" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
+			<Register Name="T1" Value0="0x00000001" />
+			<Register Name="T2" Value0="0x00000001" />
+		</ValueSet>
+
+		<ValueSet InputId="1" InstanceId="0">
+			<Register Name="T0" Value0="0x00000001" />
+			<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
+			<Register Name="T2" Value0="0x00000000" />
+		</ValueSet>
+
+		<ValueSet InputId="2" InstanceId="0">
+			<Register Name="T0" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
+			<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
+			<Register Name="T2" Value0="0x00000000" />
+		</ValueSet>
+		
+	</Outputs>
+
+</Test>