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More conversion done for cubemastah.elf.

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git-svn-id: http://svn.purei.org/purei/trunk@216 b36208d7-6611-0410-8bec-b1987f11c4a2
This commit is contained in:
jpd002 2008-01-07 04:05:17 +00:00
parent c2460b8d3f
commit 8b26b04f8b
12 changed files with 220 additions and 72 deletions
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10
Source/COP_FPU.cpp
View File

@ -288,13 +288,9 @@ void CCOP_FPU::MOV_S()
//07
void CCOP_FPU::NEG_S()
{
CCodeGen::Begin(m_pB);
{
CFPU::PushSingle(&m_pCtx->m_State.nCOP10[m_nFS * 2]);
CFPU::Neg();
CFPU::PullSingle(&m_pCtx->m_State.nCOP10[m_nFD * 2]);
}
CCodeGen::End();
m_codeGen->FP_PushSingle(offsetof(CMIPS, m_State.nCOP10[m_nFS * 2]));
m_codeGen->FP_Neg();
m_codeGen->FP_PullSingle(offsetof(CMIPS, m_State.nCOP10[m_nFD * 2]));
}
//18

103
Source/CodeGen.cpp
View File

@ -1418,7 +1418,7 @@ void CCodeGen::Cmp64(CONDITION nCondition)
}
}
void CCodeGen::DivS()
void CCodeGen::Div_Base(const MultFunction& function)
{
if(FitsPattern<RelativeConstant>())
{
@ -1435,10 +1435,29 @@ void CCodeGen::DivS()
LoadRelativeInRegister(lowRegister, ops.first);
LoadConstantInRegister(tempRegister, ops.second);
m_Assembler.Cdq();
m_Assembler.IdivEd(CX86Assembler::MakeRegisterAddress(m_nRegisterLookupEx[tempRegister]));
function(CX86Assembler::MakeRegisterAddress(m_nRegisterLookupEx[tempRegister]));
FreeRegister(tempRegister);
PushReg(highRegister);
PushReg(lowRegister);
}
else if(FitsPattern<RelativeRelative>())
{
RelativeRelative::PatternValue ops(GetPattern<RelativeRelative>());
//We need eax and edx for this
assert(!m_nRegisterAllocated[REGISTER_EAX] && !m_nRegisterAllocated[REGISTER_EDX]);
m_nRegisterAllocated[REGISTER_EAX] = true;
m_nRegisterAllocated[REGISTER_EDX] = true;
unsigned int lowRegister = REGISTER_EAX;
unsigned int highRegister = REGISTER_EDX;
LoadRelativeInRegister(lowRegister, ops.first);
m_Assembler.Cdq();
function(CX86Assembler::MakeIndRegOffAddress(g_nBaseRegister, ops.second));
PushReg(highRegister);
PushReg(lowRegister);
}
@ -1448,6 +1467,16 @@ void CCodeGen::DivS()
}
}
void CCodeGen::Div()
{
Div_Base(bind(&CX86Assembler::DivEd, &m_Assembler, _1));
}
void CCodeGen::DivS()
{
Div_Base(bind(&CX86Assembler::IdivEd, &m_Assembler, _1));
}
void CCodeGen::Lookup(uint32* table)
{
if(FitsPattern<SingleRegister>())
@ -1551,15 +1580,15 @@ _done:
void CCodeGen::Mult()
{
Mult_Base(bind(&CX86Assembler::MulEd, &m_Assembler, _1));
Mult_Base(bind(&CX86Assembler::MulEd, &m_Assembler, _1), false);
}
void CCodeGen::MultS()
{
Mult_Base(bind(&CX86Assembler::ImulEd, &m_Assembler, _1));
Mult_Base(bind(&CX86Assembler::ImulEd, &m_Assembler, _1), true);
}
void CCodeGen::Mult_Base(const MultFunction& multFunction)
void CCodeGen::Mult_Base(const MultFunction& multFunction, bool isSigned)
{
if(FitsPattern<CommutativeRelativeConstant>())
{
@ -1596,6 +1625,21 @@ void CCodeGen::Mult_Base(const MultFunction& multFunction)
PushReg(highRegister);
PushReg(lowRegister);
}
else if(FitsPattern<ConstantConstant>())
{
ConstantConstant::PatternValue ops(GetPattern<ConstantConstant>());
INTEGER64 result;
if(isSigned)
{
result.q = static_cast<int32>(ops.first) * static_cast<int32>(ops.second);
}
else
{
result.q = static_cast<uint32>(ops.first) * static_cast<uint32>(ops.second);
}
PushCst(result.d1);
PushCst(result.d0);
}
else
{
assert(0);
@ -2031,6 +2075,25 @@ void CCodeGen::Sra64(uint8 nAmount)
}
}
void CCodeGen::Srl()
{
if(FitsPattern<RelativeRelative>())
{
RelativeRelative::PatternValue ops = GetPattern<RelativeRelative>();
unsigned int shiftAmount = AllocateRegister(REGISTER_SHIFTAMOUNT);
unsigned int resultRegister = AllocateRegister();
LoadRelativeInRegister(resultRegister, ops.first);
LoadRelativeInRegister(shiftAmount, ops.second);
m_Assembler.ShrEd(CX86Assembler::MakeRegisterAddress(m_nRegisterLookupEx[resultRegister]));
FreeRegister(shiftAmount);
PushReg(resultRegister);
}
else
{
assert(0);
}
}
void CCodeGen::Srl(uint8 nAmount)
{
if(FitsPattern<SingleRegister>())
@ -2044,7 +2107,7 @@ void CCodeGen::Srl(uint8 nAmount)
}
else if(FitsPattern<SingleRelative>())
{
UnaryRelativeSelfCallAsRegister(bind(&CCodeGen::Srl, nAmount));
UnaryRelativeSelfCallAsRegister(bind(&CCodeGen::Srl, this, nAmount));
}
else
{
@ -2414,7 +2477,33 @@ void CCodeGen::Cmp64Eq()
}
else
{
assert(0);
uint32 value[4];
uint32 valueType[4];
for(int i = 3; i >= 0; i--)
{
valueType[i] = m_Shadow.Pull();
value[i] = m_Shadow.Pull();
}
unsigned int resultRegister = AllocateRegister(REGISTER_HASLOW);
unsigned int tempRegister = AllocateRegister(REGISTER_HASLOW);
EmitLoad(valueType[0], value[0], resultRegister);
EmitOp(Op_Cmp, valueType[2], value[2], resultRegister);
m_Assembler.SeteEb(CX86Assembler::MakeByteRegisterAddress(m_nRegisterLookupEx[resultRegister]));
EmitLoad(valueType[1], value[1], tempRegister);
EmitOp(Op_Cmp, valueType[3], value[3], tempRegister);
m_Assembler.SeteEb(CX86Assembler::MakeByteRegisterAddress(m_nRegisterLookupEx[tempRegister]));
m_Assembler.AndEd(m_nRegisterLookupEx[resultRegister],
CX86Assembler::MakeRegisterAddress(m_nRegisterLookupEx[tempRegister]));
m_Assembler.MovzxEb(m_nRegisterLookupEx[resultRegister],
CX86Assembler::MakeByteRegisterAddress(m_nRegisterLookupEx[resultRegister]));
FreeRegister(tempRegister);
PushReg(resultRegister);
}
}

8
Source/CodeGen.h
View File

@ -102,6 +102,7 @@ public:
static void Call(void*, unsigned int, bool);
static void Cmp(CONDITION);
static void Cmp64(CONDITION);
void Div();
void DivS();
void Lookup(uint32*);
static void Lzc();
@ -116,7 +117,8 @@ public:
static void Shl64(uint8);
static void Sra(uint8);
static void Sra64(uint8);
static void Srl(uint8);
void Srl();
void Srl(uint8);
static void Srl64();
static void Srl64(uint8);
static void Sub();
@ -136,6 +138,7 @@ public:
void FP_Mul();
void FP_Div();
void FP_Cmp(CONDITION);
void FP_Neg();
void SetStream(Framework::CStream*);
static CX86Assembler m_Assembler;
@ -262,7 +265,8 @@ private:
typedef std::tr1::function<void (const CX86Assembler::CAddress&)> MultFunction;
void Mult_Base(const MultFunction&);
void Div_Base(const MultFunction&);
void Mult_Base(const MultFunction&, bool);
static void StreamWriteByte(uint8);
static void StreamWriteAt(unsigned int, uint8);

18
Source/CodeGen_FPU.cpp
View File

@ -391,3 +391,21 @@ void CCodeGen::FP_Cmp(CCodeGen::CONDITION condition)
assert(0);
}
}
void CCodeGen::FP_Neg()
{
if(FitsPattern<SingleFpSingleRelative>())
{
SingleFpSingleRelative::PatternValue op = GetPattern<SingleFpSingleRelative>();
XMMREGISTER resultRegister = AllocateXmmRegister();
m_Assembler.PxorVo(resultRegister,
CX86Assembler::MakeXmmRegisterAddress(resultRegister));
m_Assembler.SubssEd(resultRegister,
CX86Assembler::MakeIndRegOffAddress(g_nBaseRegister, op));
FP_PushSingleReg(resultRegister);
}
else
{
assert(0);
}
}

31
Source/MA_EE.cpp
View File

@ -69,27 +69,24 @@ void CMA_EE::PullVector(unsigned int nReg)
//1E
void CMA_EE::LQ()
{
ComputeMemAccessAddr();
ComputeMemAccessAddrEx();
//Load the word
m_pB->PushRef(m_pCtx);
m_pB->Call(reinterpret_cast<void*>(&CCacheBlock::GetWordProxy), 1, true);
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[0]);
m_pB->AddImm(4);
for(unsigned int i = 0; i < 4; i++)
{
m_codeGen->PushRef(m_pCtx);
m_codeGen->PushIdx(1);
m_codeGen->Call(reinterpret_cast<void*>(&CCacheBlock::GetWordProxy), 2, true);
m_pB->PushRef(m_pCtx);
m_pB->Call(reinterpret_cast<void*>(&CCacheBlock::GetWordProxy), 1, true);
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[1]);
m_pB->AddImm(4);
m_codeGen->PullRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[i]));
m_pB->PushRef(m_pCtx);
m_pB->Call(reinterpret_cast<void*>(&CCacheBlock::GetWordProxy), 1, true);
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[2]);
m_pB->AddImm(4);
if(i != 3)
{
m_codeGen->PushCst(4);
m_codeGen->Add();
}
}
m_pB->PushRef(m_pCtx);
m_pB->Call(reinterpret_cast<void*>(&CCacheBlock::GetWordProxy), 2, true);
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[3]);
m_codeGen->PullTop();
}
//1F

49
Source/MA_MIPSIV.cpp
View File

@ -581,16 +581,17 @@ void CMA_MIPSIV::LWR()
//27
void CMA_MIPSIV::LWU()
{
ComputeMemAccessAddr();
ComputeMemAccessAddrEx();
//Load the word
m_pB->PushRef(m_pCtx);
m_pB->Call(reinterpret_cast<void*>(&CCacheBlock::GetWordProxy), 2, true);
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[0]);
m_codeGen->PushRef(m_pCtx);
m_codeGen->PushIdx(1);
m_codeGen->Call(reinterpret_cast<void*>(&CCacheBlock::GetWordProxy), 2, true);
m_codeGen->PullRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));
//Zero extend the value
m_pB->PushImm(0);
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[1]);
m_codeGen->PushCst(0);
m_codeGen->PullRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[1]));
m_codeGen->PullTop();
}
//28
@ -784,7 +785,7 @@ void CMA_MIPSIV::SLL()
//02
void CMA_MIPSIV::SRL()
{
Template_ShiftCst32()(&CCodeGen::Srl);
Template_ShiftCst32()(bind(&CCodeGen::Srl, m_codeGen, _1));
}
//03
@ -806,11 +807,7 @@ void CMA_MIPSIV::SLLV()
//06
void CMA_MIPSIV::SRLV()
{
m_pB->PushAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[0]);
m_pB->PushAddr(&m_pCtx->m_State.nGPR[m_nRS].nV[0]);
m_pB->Srl();
SignExtendTop32(m_nRD);
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRD].nV[0]);
Template_ShiftVar32()(bind(&CCodeGen::Srl, m_codeGen));
}
//07
@ -971,33 +968,13 @@ void CMA_MIPSIV::MULTU()
//1A
void CMA_MIPSIV::DIV()
{
m_codeGen->PushRel(offsetof(CMIPS, m_State.nGPR[m_nRS].nV[0]));
m_codeGen->PushRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));
m_codeGen->DivS();
m_codeGen->SeX();
m_codeGen->PullRel(offsetof(CMIPS, m_State.nLO[1]));
m_codeGen->PullRel(offsetof(CMIPS, m_State.nLO[0]));
m_codeGen->SeX();
m_codeGen->PullRel(offsetof(CMIPS, m_State.nHI[1]));
m_codeGen->PullRel(offsetof(CMIPS, m_State.nHI[0]));
Template_Div32()(bind(&CCodeGen::DivS, m_codeGen));
}
//1B
void CMA_MIPSIV::DIVU()
{
m_pB->PushAddr(&m_pCtx->m_State.nGPR[m_nRS].nV[0]);
m_pB->PushAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[0]);
m_pB->Div();
m_pB->SeX32();
m_pB->PullAddr(&m_pCtx->m_State.nLO[1]);
m_pB->PullAddr(&m_pCtx->m_State.nLO[0]);
m_pB->SeX32();
m_pB->PullAddr(&m_pCtx->m_State.nHI[1]);
m_pB->PullAddr(&m_pCtx->m_State.nHI[0]);
Template_Div32()(bind(&CCodeGen::Div, m_codeGen));
}
//20

16
Source/MA_MIPSIV.h
View File

@ -70,8 +70,14 @@ protected:
struct Template_ShiftCst32
{
typedef void (*OperationFunctionType)(uint8);
void operator()(OperationFunctionType);
typedef std::tr1::function<void (uint8)> OperationFunctionType;
void operator()(const OperationFunctionType&) const;
};
struct Template_ShiftVar32
{
typedef std::tr1::function<void ()> OperationFunctionType;
void operator()(const OperationFunctionType&) const;
};
struct Template_Mult32
@ -80,6 +86,12 @@ protected:
void operator()(const OperationFunctionType&, unsigned int) const;
};
struct Template_Div32
{
typedef std::tr1::function<void ()> OperationFunctionType;
void operator()(const OperationFunctionType&) const;
};
struct Template_MovEqual
{
void operator()(bool) const;

30
Source/MA_MIPSIV_Templates.cpp
View File

@ -8,6 +8,8 @@ using namespace std;
void CMA_MIPSIV::Template_LoadUnsigned32::operator()(void* pProxyFunction)
{
//TODO: Need to check if this used correctly... LBU, LHU and LW uses this (why LW? and why sign extend on LBU and LHU?)
ComputeMemAccessAddrEx();
m_codeGen->PushRef(m_pCtx);
@ -21,7 +23,7 @@ void CMA_MIPSIV::Template_LoadUnsigned32::operator()(void* pProxyFunction)
m_codeGen->PullTop();
}
void CMA_MIPSIV::Template_ShiftCst32::operator()(OperationFunctionType Function)
void CMA_MIPSIV::Template_ShiftCst32::operator()(const OperationFunctionType& Function) const
{
m_codeGen->PushRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));
Function(m_nSA);
@ -31,6 +33,17 @@ void CMA_MIPSIV::Template_ShiftCst32::operator()(OperationFunctionType Function)
m_codeGen->PullRel(offsetof(CMIPS, m_State.nGPR[m_nRD].nV[0]));
}
void CMA_MIPSIV::Template_ShiftVar32::operator()(const OperationFunctionType& function) const
{
m_codeGen->PushRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));
m_codeGen->PushRel(offsetof(CMIPS, m_State.nGPR[m_nRS].nV[0]));
function();
m_codeGen->SeX();
m_codeGen->PullRel(offsetof(CMIPS, m_State.nGPR[m_nRD].nV[1]));
m_codeGen->PullRel(offsetof(CMIPS, m_State.nGPR[m_nRD].nV[0]));
}
void CMA_MIPSIV::Template_Mult32::operator()(const OperationFunctionType& Function, unsigned int unit) const
{
size_t lo[2];
@ -78,6 +91,21 @@ void CMA_MIPSIV::Template_Mult32::operator()(const OperationFunctionType& Functi
}
}
void CMA_MIPSIV::Template_Div32::operator()(const OperationFunctionType& function) const
{
m_codeGen->PushRel(offsetof(CMIPS, m_State.nGPR[m_nRS].nV[0]));
m_codeGen->PushRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));
function();
m_codeGen->SeX();
m_codeGen->PullRel(offsetof(CMIPS, m_State.nLO[1]));
m_codeGen->PullRel(offsetof(CMIPS, m_State.nLO[0]));
m_codeGen->SeX();
m_codeGen->PullRel(offsetof(CMIPS, m_State.nHI[1]));
m_codeGen->PullRel(offsetof(CMIPS, m_State.nHI[0]));
}
void CMA_MIPSIV::Template_MovEqual::operator()(bool isEqual) const
{
m_codeGen->PushRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));

12
Source/MipsExecutor.cpp
View File

@ -181,6 +181,18 @@ void CMipsExecutor::PartitionFunction(uint32 functionAddress)
{
partitionPoints.insert(address + 4);
}
//Check if there's a block already exising that this address
if(address != endAddress)
{
CBasicBlock* possibleBlock = FindBlockStartingAt(address);
if(possibleBlock != NULL)
{
assert(possibleBlock->GetEndAddress() <= endAddress);
//Add its beginning and end in the partition points
partitionPoints.insert(possibleBlock->GetBeginAddress());
partitionPoints.insert(possibleBlock->GetEndAddress() + 4);
}
}
}
uint32 currentPoint = 0;

5
Source/X86Assembler.cpp
View File

@ -258,6 +258,11 @@ void CX86Assembler::Cdq()
WriteByte(0x99);
}
void CX86Assembler::DivEd(const CAddress& address)
{
WriteEvOp(0xF7, 0x06, false, address);
}
void CX86Assembler::IdivEd(const CAddress& address)
{
WriteEvOp(0xF7, 0x07, false, address);

3
Source/X86Assembler.h
View File

@ -122,6 +122,7 @@ public:
void CmpId(const CAddress&, uint32);
void CmpIq(const CAddress&, uint64);
void Cdq();
void DivEd(const CAddress&);
void IdivEd(const CAddress&);
void ImulEd(const CAddress&);
void JaeJb(LABEL);
@ -196,6 +197,8 @@ public:
SSE_CMP_ORD = 7,
};
void PxorVo(XMMREGISTER, const CAddress&);
void MovssEd(const CAddress&, XMMREGISTER);
void MovssEd(XMMREGISTER, const CAddress&);
void AddssEd(XMMREGISTER, const CAddress&);

7
Source/X86Assembler_Fpu.cpp
View File

@ -133,6 +133,13 @@ void CX86Assembler::Cvttss2siEd(REGISTER registerId, const CAddress& address)
WriteEvGvOp(0x2C, false, address, registerId);
}
void CX86Assembler::PxorVo(XMMREGISTER registerId, const CAddress& address)
{
WriteByte(0x66);
WriteByte(0x0F);
WriteEdVdOp(0xEF, address, registerId);
}
void CX86Assembler::WriteStOp(uint8 opcode, uint8 subOpcode, uint8 stackId)
{
CAddress address;