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git-svn-id: http://svn.purei.org/purei/trunk@149 b36208d7-6611-0410-8bec-b1987f11c4a2

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This commit is contained in:
jpd002 2007-04-27 15:40:36 +00:00
parent 1205201c88
commit e7126f3c3b
6 changed files with 262 additions and 12 deletions
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89
Source/CodeGen.cpp
View File

@ -974,6 +974,40 @@ void CCodeGen::Add64()
PushReg(nRegister1);
PushReg(nRegister2);
}
else if(\
(m_Shadow.GetAt(0) == CONSTANT) && \
(m_Shadow.GetAt(2) == CONSTANT) && \
(m_Shadow.GetAt(4) == RELATIVE) && \
(m_Shadow.GetAt(6) == RELATIVE))
{
uint32 nRelative1, nRelative2;
uint32 nConstant1, nConstant2;
uint32 nRegister1, nRegister2;
m_Shadow.Pull();
nConstant2 = m_Shadow.Pull();
m_Shadow.Pull();
nConstant1 = m_Shadow.Pull();
m_Shadow.Pull();
nRelative2 = m_Shadow.Pull();
m_Shadow.Pull();
nRelative1 = m_Shadow.Pull();
nRegister1 = AllocateRegister();
nRegister2 = AllocateRegister();
LoadRelativeInRegister(nRegister1, nRelative1);
LoadRelativeInRegister(nRegister2, nRelative2);
//add reg1, const1
X86_RegImmOp(nRegister1, nConstant1, 0x00);
//adc reg2, const2
X86_RegImmOp(nRegister2, nConstant2, 0x02);
PushReg(nRegister1);
PushReg(nRegister2);
}
else
{
assert(0);
@ -2055,6 +2089,43 @@ void CCodeGen::Sra(uint8 nAmount)
}
}
void CCodeGen::Sra64(uint8 nAmount)
{
if(
(m_Shadow.GetAt(0) == RELATIVE) && \
(m_Shadow.GetAt(2) == RELATIVE))
{
uint32 nRelative1, nRelative2;
m_Shadow.Pull();
nRelative2 = m_Shadow.Pull();
m_Shadow.Pull();
nRelative1 = m_Shadow.Pull();
nAmount &= 0x3F;
if(nAmount == 32)
{
PushRel(nRelative2);
SeX();
}
else if(nAmount > 32)
{
PushRel(nRelative2);
Sra(nAmount - 32);
SeX();
}
else
{
assert(0);
}
}
else
{
assert(0);
}
}
void CCodeGen::Srl(uint8 nAmount)
{
if(m_Shadow.GetAt(0) == REGISTER)
@ -2760,3 +2831,21 @@ bool CCodeGen::IsTopContRelCstPair64()
return false;
}
}
void CCodeGen::X86_RegImmOp(unsigned int nRegister, uint32 nConstant, unsigned int nOp)
{
assert(nOp < 8);
assert(nRegister < 8);
if(GetMinimumConstantSize(nConstant) == 1)
{
//op reg, Immediate
m_pBlock->StreamWrite(3, 0x83, 0xC0 | (nOp << 3) | (m_nRegisterLookup[nRegister]), (uint8)nConstant);
}
else
{
//op reg, Immediate
m_pBlock->StreamWrite(2, 0x81, 0xC0 | (nOp << 3) | (m_nRegisterLookup[nRegister]));
m_pBlock->StreamWriteWord(nConstant);
}
}

5
Source/CodeGen.h
View File

@ -62,6 +62,7 @@ public:
static void Shl64();
static void Shl64(uint8);
static void Sra(uint8);
static void Sra64(uint8);
static void Srl(uint8);
static void Srl64();
static void Srl64(uint8);
@ -179,7 +180,9 @@ private:
static void Cmp64Lt(bool, bool);
static void Cmp64Cont(CONDITION);
static bool m_nBlockStarted;
static void X86_RegImmOp(unsigned int, uint32, unsigned int);
static bool m_nBlockStarted;
static CArrayStack<uint32> m_Shadow;
#ifdef AMD64

37
Source/MA_MIPSIV.cpp
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@ -637,18 +637,20 @@ void CMA_MIPSIV::BGTZL()
//19
void CMA_MIPSIV::DADDIU()
{
//First 32-bits half
m_pB->PushAddr(&m_pCtx->m_State.nGPR[m_nRS].nV[0]);
m_pB->PushImm((int16)m_nImmediate);
m_pB->AddC();
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[0]);
CCodeGen::Begin(m_pB);
{
CCodeGen::PushRel(offsetof(CMIPS, m_State.nGPR[m_nRS].nV[0]));
CCodeGen::PushRel(offsetof(CMIPS, m_State.nGPR[m_nRS].nV[1]));
//2nd 32-bits half
m_pB->PushAddr(&m_pCtx->m_State.nGPR[m_nRS].nV[1]);
m_pB->PushImm((m_nImmediate & 0x8000) == 0 ? 0x00000000 : 0xFFFFFFFF);
m_pB->Add();
m_pB->Add();
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[1]);
CCodeGen::PushCst(static_cast<int16>(m_nImmediate));
CCodeGen::PushCst((m_nImmediate & 0x8000) == 0 ? 0x00000000 : 0xFFFFFFFF);
CCodeGen::Add64();
CCodeGen::PullRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[1]));
CCodeGen::PullRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));
}
CCodeGen::End();
}
//1A
@ -2091,6 +2093,18 @@ void CMA_MIPSIV::DSRL32()
//3F
void CMA_MIPSIV::DSRA32()
{
CCodeGen::Begin(m_pB);
{
CCodeGen::PushRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));
CCodeGen::PushRel(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[1]));
CCodeGen::Sra64(m_nSA + 32);
CCodeGen::PullRel(offsetof(CMIPS, m_State.nGPR[m_nRD].nV[1]));
CCodeGen::PullRel(offsetof(CMIPS, m_State.nGPR[m_nRD].nV[0]));
}
CCodeGen::End();
/*
//1st 32-bits
m_pB->PushAddr(&m_pCtx->m_State.nGPR[m_nRT].nV[1]);
m_pB->SraImm(m_nSA);
@ -2101,6 +2115,7 @@ void CMA_MIPSIV::DSRA32()
//Write the result
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRD].nV[1]);
m_pB->PullAddr(&m_pCtx->m_State.nGPR[m_nRD].nV[0]);
*/
}
//////////////////////////////////////////////////

4
Source/MipsAssemblerDefinitions.cpp
View File

@ -273,6 +273,8 @@ namespace MipsAssemblerDefinitions
SpecInstruction<RsImm> Instruction_BGEZ = SpecInstruction<RsImm>("BGEZ", RsImm(&CMIPSAssembler::BGEZ));
SpecInstruction<RsImm> Instruction_BLEZ = SpecInstruction<RsImm>("BLEZ", RsImm(&CMIPSAssembler::BLEZ));
SpecInstruction<RsRtImm> Instruction_BNE = SpecInstruction<RsRtImm>("BNE", RsRtImm(&CMIPSAssembler::BNE));
SpecInstruction<RtRsImm> Instruction_DADDIU = SpecInstruction<RtRsImm>("DADDIU", RtRsImm(&CMIPSAssembler::DADDIU));
SpecInstruction<RtRsSa> Instruction_DSRA32 = SpecInstruction<RtRsSa>("DSRA32", RtRsSa(&CMIPSAssembler::DSRA32));
SpecInstruction<RtOfsBase> Instruction_LHU = SpecInstruction<RtOfsBase>("LHU", RtOfsBase(&CMIPSAssembler::LHU));
SpecInstruction<RtImm> Instruction_LUI = SpecInstruction<RtImm>("LUI", RtImm(&CMIPSAssembler::LUI));
SpecInstruction<RtOfsBase> Instruction_LW = SpecInstruction<RtOfsBase>("LW", RtOfsBase(&CMIPSAssembler::LW));
@ -291,6 +293,8 @@ namespace MipsAssemblerDefinitions
&Instruction_BGEZ,
&Instruction_BLEZ,
&Instruction_BNE,
&Instruction_DADDIU,
&Instruction_DSRA32,
&Instruction_LHU,
&Instruction_LUI,
&Instruction_LW,

65
tests/DADDIU.xml Normal file
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@ -0,0 +1,65 @@
<Test>
<Inputs>
<ValueSet InputId="0">
<Register Name="T0" Value0="0x00000000" Value1="0xFFFFFFFF" />
<Register Name="T1" Value0="0xDEADBEEF" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="1">
<Register Name="T0" Value0="0x00000001" />
<Register Name="T1" Value0="0x0EADBEEF" />
</ValueSet>
</Inputs>
<Instances>
<Instance Id="0">
DADDIU T1, T0, 0x0000
</Instance>
<Instance Id="1">
DADDIU T1, T0, 0x7FFF
</Instance>
<Instance Id="2">
DADDIU T1, T0, 0x8000
</Instance>
<Instance Id="3">
DADDIU T1, T0, 0xFFFF
</Instance>
</Instances>
<Outputs>
<ValueSet InputId="0" InstanceId="0">
<Register Name="T0" Value0="0x00000000" Value1="0xFFFFFFFF" />
<Register Name="T1" Value0="0x00000000" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="0" InstanceId="1">
<Register Name="T0" Value0="0x00000000" Value1="0xFFFFFFFF" />
<Register Name="T1" Value0="0x00007FFF" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="0" InstanceId="3">
<Register Name="T0" Value0="0x00000000" Value1="0xFFFFFFFF" />
<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFE" />
</ValueSet>
<ValueSet InputId="1" InstanceId="2">
<Register Name="T0" Value0="0x00000001" />
<Register Name="T1" Value0="0xFFFF8001" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="1" InstanceId="3">
<Register Name="T0" Value0="0x00000001" />
<Register Name="T1" Value0="0x00000000" />
</ValueSet>
</Outputs>
</Test>

74
tests/DSRA32.xml Normal file
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@ -0,0 +1,74 @@
<Test>
<Inputs>
<ValueSet InputId="0">
<Register Name="T0" Value0="0x808080FF" Value1="0x808080FF" />
<Register Name="T1" Value0="0xDEADBEEF" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="1">
<Register Name="T0" Value0="0x808080FF" Value1="0x008080FF" />
<Register Name="T1" Value0="0xDEADBEEF" Value1="0xFFFFFFFF" />
</ValueSet>
</Inputs>
<Instances>
<Instance Id="0">
DSRA32 T1, T0, 0
</Instance>
<Instance Id="1">
DSRA32 T1, T0, 4
</Instance>
<Instance Id="2">
DSRA32 T1, T0, 8
</Instance>
<Instance Id="3">
DSRA32 T1, T0, 16
</Instance>
<Instance Id="4">
DSRA32 T1, T0, 32
</Instance>
</Instances>
<Outputs>
<ValueSet InputId="0" InstanceId="0">
<Register Name="T0" Value0="0x808080FF" Value1="0x808080FF" />
<Register Name="T1" Value0="0x808080FF" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="0" InstanceId="1">
<Register Name="T0" Value0="0x808080FF" Value1="0x808080FF" />
<Register Name="T1" Value0="0xF808080F" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="0" InstanceId="2">
<Register Name="T0" Value0="0x808080FF" Value1="0x808080FF" />
<Register Name="T1" Value0="0xFF808080" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="0" InstanceId="3">
<Register Name="T0" Value0="0x808080FF" Value1="0x808080FF" />
<Register Name="T1" Value0="0xFFFF8080" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="0" InstanceId="4">
<Register Name="T0" Value0="0x808080FF" Value1="0x808080FF" />
<Register Name="T1" Value0="0x808080FF" Value1="0xFFFFFFFF" />
</ValueSet>
<ValueSet InputId="1" InstanceId="3">
<Register Name="T0" Value0="0x808080FF" Value1="0x008080FF" />
<Register Name="T1" Value0="0x00000080" />
</ValueSet>
</Outputs>
</Test>