mirror of
https://github.com/libretro/Play-.git
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295 lines
8.4 KiB
C++
295 lines
8.4 KiB
C++
#include "VuBasicBlock.h"
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#include "MA_VU.h"
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#include "offsetof_def.h"
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#include "MemoryUtils.h"
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#include "Vpu.h"
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CVuBasicBlock::CVuBasicBlock(CMIPS& context, uint32 begin, uint32 end)
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: CBasicBlock(context, begin, end)
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{
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}
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void CVuBasicBlock::CompileRange(CMipsJitter* jitter)
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{
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assert((m_begin & 0x07) == 0);
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assert(((m_end + 4) & 0x07) == 0);
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auto arch = static_cast<CMA_VU*>(m_context.m_pArch);
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uint32 fixedEnd = m_end;
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bool needsPcAdjust = false;
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//Make sure the delay slot instruction is present in the block.
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//CVuExecutor can sometimes cut the blocks in a way that removes the delay slot instruction for branches.
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{
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uint32 addressLo = fixedEnd - 4;
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uint32 addressHi = fixedEnd - 0;
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uint32 opcodeLo = m_context.m_pMemoryMap->GetInstruction(addressLo);
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uint32 opcodeHi = m_context.m_pMemoryMap->GetInstruction(addressHi);
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//Check for LOI
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if((opcodeHi & 0x80000000) == 0)
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{
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auto branchType = arch->IsInstructionBranch(&m_context, addressLo, opcodeLo);
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if(branchType == MIPS_BRANCH_NORMAL)
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{
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fixedEnd += 8;
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needsPcAdjust = true;
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}
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}
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}
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auto integerBranchDelayInfo = GetIntegerBranchDelayInfo(fixedEnd);
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bool hasPendingXgKick = false;
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const auto clearPendingXgKick =
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[&]()
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{
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assert(hasPendingXgKick);
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EmitXgKick(jitter);
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hasPendingXgKick = false;
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};
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for(uint32 address = m_begin; address <= fixedEnd; address += 8)
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{
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uint32 relativePipeTime = (address - m_begin) / 8;
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uint32 addressLo = address + 0;
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uint32 addressHi = address + 4;
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uint32 opcodeLo = m_context.m_pMemoryMap->GetInstruction(addressLo);
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uint32 opcodeHi = m_context.m_pMemoryMap->GetInstruction(addressHi);
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auto loOps = arch->GetAffectedOperands(&m_context, addressLo, opcodeLo);
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auto hiOps = arch->GetAffectedOperands(&m_context, addressHi, opcodeHi);
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//No upper instruction writes to Q
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assert(hiOps.syncQ == false);
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//No lower instruction reads Q
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assert(loOps.readQ == false);
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bool loIsXgKick = (opcodeLo & ~(0x1F << 11)) == 0x800006FC;
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if(loOps.syncQ)
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{
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VUShared::FlushPipeline(VUShared::g_pipeInfoQ, jitter);
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}
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if(hiOps.readQ)
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{
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VUShared::CheckPipeline(VUShared::g_pipeInfoQ, jitter, relativePipeTime);
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}
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uint8 savedReg = 0;
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if(hiOps.writeF != 0)
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{
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assert(hiOps.writeF != loOps.writeF);
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if(
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(hiOps.writeF == loOps.readF0) ||
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(hiOps.writeF == loOps.readF1)
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)
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{
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savedReg = hiOps.writeF;
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jitter->MD_PushRel(offsetof(CMIPS, m_State.nCOP2[savedReg]));
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jitter->MD_PullRel(offsetof(CMIPS, m_State.nCOP2VF_PreUp));
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}
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}
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if(address == integerBranchDelayInfo.saveRegAddress)
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{
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// grab the value of the delayed reg to use in the conditional branch later
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jitter->PushRel(offsetof(CMIPS, m_State.nCOP2VI[integerBranchDelayInfo.regIndex]));
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jitter->PullRel(offsetof(CMIPS, m_State.savedIntReg));
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}
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arch->SetRelativePipeTime(relativePipeTime);
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arch->CompileInstruction(addressHi, jitter, &m_context);
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if(savedReg != 0)
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{
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jitter->MD_PushRel(offsetof(CMIPS, m_State.nCOP2[savedReg]));
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jitter->MD_PullRel(offsetof(CMIPS, m_State.nCOP2VF_UpRes));
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jitter->MD_PushRel(offsetof(CMIPS, m_State.nCOP2VF_PreUp));
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jitter->MD_PullRel(offsetof(CMIPS, m_State.nCOP2[savedReg]));
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}
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if(address == integerBranchDelayInfo.useRegAddress)
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{
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// set the target from the saved value
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jitter->PushRel(offsetof(CMIPS, m_State.nCOP2VI[integerBranchDelayInfo.regIndex]));
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jitter->PullRel(offsetof(CMIPS, m_State.savedIntRegTemp));
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jitter->PushRel(offsetof(CMIPS, m_State.savedIntReg));
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jitter->PullRel(offsetof(CMIPS, m_State.nCOP2VI[integerBranchDelayInfo.regIndex]));
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}
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//If there's a pending XGKICK and the current lower instruction is
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//an XGKICK, make sure we flush the pending one first
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if(loIsXgKick && hasPendingXgKick)
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{
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clearPendingXgKick();
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}
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arch->CompileInstruction(addressLo, jitter, &m_context);
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if(address == integerBranchDelayInfo.useRegAddress)
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{
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// put the target value back
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jitter->PushRel(offsetof(CMIPS, m_State.savedIntRegTemp));
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jitter->PullRel(offsetof(CMIPS, m_State.nCOP2VI[integerBranchDelayInfo.regIndex]));
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}
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if(savedReg != 0)
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{
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jitter->MD_PushRel(offsetof(CMIPS, m_State.nCOP2VF_UpRes));
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jitter->MD_PullRel(offsetof(CMIPS, m_State.nCOP2[savedReg]));
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}
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if(hasPendingXgKick)
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{
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clearPendingXgKick();
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}
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if(loIsXgKick)
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{
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assert(!hasPendingXgKick);
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hasPendingXgKick = true;
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}
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//Sanity check
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assert(jitter->IsStackEmpty());
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}
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if(hasPendingXgKick)
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{
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clearPendingXgKick();
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}
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assert(!hasPendingXgKick);
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//Increment pipeTime
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{
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uint32 timeInc = ((fixedEnd - m_begin) / 8) + 1;
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jitter->PushRel(offsetof(CMIPS, m_State.pipeTime));
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jitter->PushCst(timeInc);
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jitter->Add();
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jitter->PullRel(offsetof(CMIPS, m_State.pipeTime));
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}
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//Adjust PC to make sure we don't execute the delay slot at the next block
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if(needsPcAdjust)
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{
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jitter->PushCst(MIPS_INVALID_PC);
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jitter->PushRel(offsetof(CMIPS, m_State.nDelayedJumpAddr));
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jitter->BeginIf(Jitter::CONDITION_EQ);
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{
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jitter->PushCst(fixedEnd + 0x4);
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jitter->PullRel(offsetof(CMIPS, m_State.nDelayedJumpAddr));
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}
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jitter->EndIf();
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}
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}
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bool CVuBasicBlock::IsConditionalBranch(uint32 opcodeLo)
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{
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//Conditional branches are in the contiguous opcode range 0x28 -> 0x2F inclusive
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uint32 id = (opcodeLo >> 25) & 0x7F;
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return (id >= 0x28) && (id < 0x30);
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}
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CVuBasicBlock::INTEGER_BRANCH_DELAY_INFO CVuBasicBlock::GetIntegerBranchDelayInfo(uint32 fixedEnd) const
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{
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// Test if the block ends with a conditional branch instruction where the condition variable has been
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// set in the prior instruction.
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// In this case, the pipeline shortcut fails and we need to use the value from 4 instructions previous.
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// If the relevant set instruction is not part of this block, use initial value of the integer register.
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INTEGER_BRANCH_DELAY_INFO result;
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auto arch = static_cast<CMA_VU*>(m_context.m_pArch);
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uint32 adjustedEnd = fixedEnd - 4;
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// Check if we have a conditional branch instruction.
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uint32 branchOpcodeAddr = adjustedEnd - 8;
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uint32 branchOpcodeLo = m_context.m_pMemoryMap->GetInstruction(branchOpcodeAddr);
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if(IsConditionalBranch(branchOpcodeLo))
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{
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// We have a conditional branch instruction. Now we need to check that the condition register is not written
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// by the previous instruction.
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uint32 priorOpcodeAddr = adjustedEnd - 16;
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uint32 priorOpcodeLo = m_context.m_pMemoryMap->GetInstruction(priorOpcodeAddr);
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auto priorLoOps = arch->GetAffectedOperands(&m_context, priorOpcodeAddr, priorOpcodeLo);
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if((priorLoOps.writeI != 0) && !priorLoOps.branchValue)
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{
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auto branchLoOps = arch->GetAffectedOperands(&m_context, branchOpcodeAddr, branchOpcodeLo);
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if(
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(branchLoOps.readI0 == priorLoOps.writeI) ||
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(branchLoOps.readI1 == priorLoOps.writeI)
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)
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{
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//Check if our block is a "special" loop. Disable delayed integer processing if it's the case
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//TODO: Handle that case better
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bool isSpecialLoop = CheckIsSpecialIntegerLoop(fixedEnd, priorLoOps.writeI);
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if(!isSpecialLoop)
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{
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// we need to use the value of intReg 4 steps prior or use initial value.
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result.regIndex = priorLoOps.writeI;
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result.saveRegAddress = std::max(adjustedEnd - 5 * 8, m_begin);
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result.useRegAddress = adjustedEnd - 8;
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}
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}
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}
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}
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return result;
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}
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bool CVuBasicBlock::CheckIsSpecialIntegerLoop(uint32 fixedEnd, unsigned int regI) const
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{
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//This checks for a pattern where all instructions within a block
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//modifies an integer register except for one branch instruction that
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//tests that integer register
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//Required by BGDA that has that kind of loop inside its VU microcode
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auto arch = static_cast<CMA_VU*>(m_context.m_pArch);
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uint32 length = (fixedEnd - m_begin) / 8;
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if(length != 4) return false;
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for(uint32 index = 0; index <= length; index++)
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{
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uint32 address = m_begin + (index * 8);
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uint32 opcodeLo = m_context.m_pMemoryMap->GetInstruction(address);
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if(index == (length - 1))
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{
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assert(IsConditionalBranch(opcodeLo));
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uint32 branchTarget = arch->GetInstructionEffectiveAddress(&m_context, address, opcodeLo);
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if(branchTarget != m_begin) return false;
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}
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else
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{
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auto loOps = arch->GetAffectedOperands(&m_context, address, opcodeLo);
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if(loOps.writeI != regI) return false;
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}
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}
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return true;
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}
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void CVuBasicBlock::EmitXgKick(CMipsJitter* jitter)
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{
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//Push context
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jitter->PushCtx();
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//Push value
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jitter->PushRel(offsetof(CMIPS, m_State.xgkickAddress));
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//Compute Address
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jitter->PushCst(CVpu::VU_XGKICK);
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jitter->Call(reinterpret_cast<void*>(&MemoryUtils_SetWordProxy), 3, false);
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}
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