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https://github.com/libretro/beetle-lynx-libretro.git
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Remove huc6270/backup
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twinaphex
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@ -1,448 +0,0 @@
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#ifndef __PCE_VDC_H
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#define __PCE_VDC_H
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#include "mednafen/lepacker.h"
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#define VDC_PIXEL_OUT_MASK 0x01FF
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// This bit will be set for a non-sprite pixel if the BG layer is disabled(via ToggleLayer()),
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#define VDC_BGDISABLE_OUT_MASK 0x0200
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// HSync and VSync out bits are only valid when the EX bits in VDC's CR
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// are set so that the VDC will output sync signals rather than
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// input them. If it is not configured in this manner, the bit(s) shall always be 0.
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#define VDC_HSYNC_OUT_MASK 0x2000
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#define VDC_VSYNC_OUT_MASK 0x4000
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// The DISP bit can either denote active display area(1 = active, 0 = inactive),
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// colorburst insertion period(0 = insert colorburst, 1 = not in colorburst period; may not be emulated correctly),
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// or "internal horizontal synchronous signal"(may not be emulated correctly), depending on the TE
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// bits in the VDC's CR.
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#define VDC_DISP_OUT_MASK 0x8000
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#define VDC_REGSETP(_reg, _data, _msb) { _reg &= 0xFF << ((_msb) ? 0 : 8); _reg |= (_data) << ((_msb) ? 8 : 0); }
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#define VDC_REGGETP(_reg, _msb) ((_reg >> ((_msb) ? 8 : 0)) & 0xFF)
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static const unsigned int vram_inc_tab[4] = { 1, 32, 64, 128 };
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#define VDC_IS_BSY (pending_read || pending_write)
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typedef struct
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{
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uint32 x;
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uint32 flags;
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uint8 palette_index;
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uint16 pattern_data[4];
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} SPRLE;
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typedef struct
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{
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// In the case the VDC access doesn't cause a VRAM read/write, only ReadCount/WriteCount will be set to 0.
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uint32 ReadStart;
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uint32 ReadCount;
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uint32 WriteStart;
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uint32 WriteCount;
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} VDC_SimulateResult;
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class VDC
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{
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public:
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// The VRAM size is specified in 16-bit words.
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VDC(bool nospritelimit, uint32 par_VRAM_Size);
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~VDC();
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#if 0
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void *operator new(size_t bcount)
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{
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void *ret = calloc(1, bcount);
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return(ret);
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}
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void operator delete(void *ptr)
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{
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free(ptr);
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}
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#endif
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int32 Reset(void) MDFN_WARN_UNUSED_RESULT;
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// ResetSimulate(), SimulateWrite(), and SimulateRead() are intended to handle VRAM read/write breakpoints.
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// SimulateWrite() and SimulateRead() will return the VRAM address that will EVENTUALLY be written(upper 32-bits) and/or read(lower 32-bits) to
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// due to the access, or 0xFFFFFFFF in the upper or lower 32-bits if no VRAM access of that type occurs.
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//
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// The feature is intended to support block moves to VRAM in a single instruction. It may not function properly if the address passed to SimulateRead()
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// or SimulateWrite() alternates(even if just once) between the data port high byte and control port between calls to ResetSimulate()
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// Call to reset simulation state.
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INLINE void ResetSimulate(void)
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{
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Simulate_MAWR = MAWR;
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Simulate_MARR = MARR;
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Simulate_select = select;
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Simulate_CR = CR;
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Simulate_LENR = LENR;
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}
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INLINE void SimulateRead(uint32 A, VDC_SimulateResult *result)
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{
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result->ReadCount = 0;
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result->WriteCount = 0;
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result->ReadStart = 0;
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result->WriteStart = 0;
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if((A & 0x3) == 0x3 && Simulate_select == 0x02)
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{
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Simulate_MARR += vram_inc_tab[(Simulate_CR >> 11) & 0x3];
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result->ReadStart = Simulate_MARR;
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result->ReadCount = 1;
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}
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}
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INLINE void SimulateWrite(uint32 A, uint8 V, VDC_SimulateResult *result)
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{
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result->ReadCount = 0;
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result->WriteCount = 0;
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result->ReadStart = 0;
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result->WriteStart = 0;
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const unsigned int msb = A & 1;
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switch(A & 0x3)
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{
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case 0x00: Simulate_select = V & 0x1F;
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break;
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case 0x02:
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case 0x03:
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switch(Simulate_select)
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{
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case 0x00: VDC_REGSETP(Simulate_MAWR, V, msb);
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break;
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case 0x01: VDC_REGSETP(Simulate_MARR, V, msb);
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Simulate_MARR += vram_inc_tab[(Simulate_CR >> 11) & 0x3];
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result->ReadStart = Simulate_MARR;
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result->ReadCount = 1;
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break;
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case 0x02: if(msb)
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{
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result->WriteStart = Simulate_MAWR;
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result->WriteCount = 1;
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Simulate_MAWR += vram_inc_tab[(Simulate_CR >> 11) & 0x3];
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}
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break;
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case 0x12: VDC_REGSETP(Simulate_LENR, V, msb);
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if(msb)
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{
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result->ReadStart = SOUR;
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result->ReadCount = Simulate_LENR + 1;
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if(DCR & 0x4)
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result->ReadStart = (result->ReadStart - (result->ReadCount - 1)) & 0xFFFF;
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result->WriteStart = DESR;
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result->WriteCount = Simulate_LENR + 1;
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if(DCR & 0x8)
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result->WriteStart = (result->WriteStart - (result->WriteCount - 1)) & 0xFFFF;
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}
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break;
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}
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break;
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}
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}
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int32 HSync(bool);
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int32 VSync(bool);
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void Write(uint32 A, uint8 V, int32 &next_event);
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uint8 Read(uint32 A, int32 &next_event, bool peek = FALSE);
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void Write16(bool A, uint16 V);
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uint16 Read16(bool A, bool peek = FALSE);
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int32 Run(int32 clocks, /*bool hs, bool vs,*/ uint16 *pixels, bool skip);
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void FixTileCache(uint16);
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bool ToggleLayer(int);
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void RunDMA(int32, bool force_completion = FALSE);
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void RunSATDMA(int32, bool force_completion = FALSE);
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void IncRCR(void);
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void DoVBIRQTest(void);
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void HDS_Start(void);
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void StateExtra(MDFN::LEPacker &sl_packer, bool load);
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int StateAction(StateMem *sm, int load, int data_only, const char *sname);
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// Peek(VRAM/SAT) and Poke(VRAM/SAT) work in 16-bit VRAM word units.
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INLINE uint16 PeekVRAM(uint16 Address)
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{
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if(Address < VRAM_Size)
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return(VRAM[Address]);
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else
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return(0);
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}
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INLINE uint16 PeekSAT(uint8 Address)
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{
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return(SAT[Address]);
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}
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INLINE void PokeVRAM(uint16 Address, const uint16 Data)
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{
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if(Address < VRAM_Size)
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{
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VRAM[Address] = Data;
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FixTileCache(Address);
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}
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}
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INLINE void PokeSAT(uint8 Address, const uint16 Data)
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{
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SAT[Address] = Data;
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}
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// Register enums for GetRegister() and SetRegister()
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enum
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{
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GSREG_MAWR = 0,
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GSREG_MARR,
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GSREG_CR,
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GSREG_RCR,
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GSREG_BXR,
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GSREG_BYR,
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GSREG_MWR,
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GSREG_HSR,
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GSREG_HDR,
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GSREG_VSR,
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GSREG_VDR,
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GSREG_VCR,
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GSREG_DCR,
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GSREG_SOUR,
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GSREG_DESR,
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GSREG_LENR,
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GSREG_DVSSR,
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GSREG_SELECT,
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GSREG_STATUS,
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__GSREG_COUNT
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};
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// Pass NULL if you don't want more information about the special meaning of the value in the specified
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// register. Otherwise, pass a buffer of at least 256 bytes in size.
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uint32 GetRegister(const unsigned int id, char *special, const uint32 special_len);
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void SetRegister(const unsigned int id, const uint32 value);
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#ifdef WANT_DEBUGGER
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bool DoGfxDecode(uint32 *target, const uint32 *color_table, const uint32 TransparentColor, bool DecodeSprites,
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int32 w, int32 h, int32 scroll);
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#endif
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INLINE bool PeekIRQ(void)
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{
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return((bool)(status & 0x3F));
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}
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INLINE void SetIRQHook(void (*irqh)(bool))
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{
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IRQHook = irqh;
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}
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INLINE void SetWSHook(bool (*wsh)(int32))
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{
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WSHook = wsh;
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}
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private:
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int TimeFromHDSStartToBYRLatch(void);
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int TimeFromBYRLatchToBXRLatch(void);
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enum
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{
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HPHASE_HDS = 0,
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HPHASE_HDS_PART2,
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HPHASE_HDS_PART3,
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HPHASE_HDW,
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HPHASE_HDW_FINAL,
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HPHASE_HDE,
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HPHASE_HSW,
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HPHASE_COUNT
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};
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enum
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{
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VPHASE_VDS = 0,
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VPHASE_VDW,
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VPHASE_VCR,
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VPHASE_VSW,
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VPHASE_COUNT
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};
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int VRAM_Size; // = 0x8000;
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int VRAM_SizeMask; // = VRAM_Size - 1; //0x7FFF;
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int VRAM_BGTileNoMask; // = VRAM_SizeMask / 16; //0x7FF;
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void (*IRQHook)(bool);
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bool (*WSHook)(int32);
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void DoWaitStates(void);
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void CheckAndCommitPending(void);
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INLINE int32 CalcNextEvent(void)
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{
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int32 next_event = HPhaseCounter;
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if(sat_dma_counter > 0 && sat_dma_counter < next_event)
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next_event = sat_dma_counter;
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if(sprite_cg_fetch_counter > 0 && sprite_cg_fetch_counter < next_event)
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next_event = sprite_cg_fetch_counter;
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if(DMARunning)
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{
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assert(VDMA_CycleCounter < 2);
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int32 next_vram_dma_event = ((LENR + 1) * 4) - (DMAReadWrite * 2) - VDMA_CycleCounter;
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assert(next_vram_dma_event > 0);
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if(next_vram_dma_event > 0 && next_vram_dma_event < next_event)
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next_event = next_vram_dma_event;
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//printf("Next VRAM DMA event: %d(LENR = %d)\n", next_vram_dma_event, LENR);
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}
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assert(next_event > 0);
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return(next_event);
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}
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bool in_exhsync, in_exvsync;
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void CalcWidthStartEnd(uint32 &display_width, uint32 &start, uint32 &end);
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void DrawBG(uint16 *target, int enabled);
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void DrawSprites(uint16 *target, int enabled);
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void FetchSpriteData(void);
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uint8 Simulate_select;
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uint16 Simulate_MAWR;
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uint16 Simulate_MARR;
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uint16 Simulate_CR;
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uint16 Simulate_LENR;
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int32 sat_dma_counter;
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uint8 select;
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uint16 MAWR; // Memory Address Write Register
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uint16 MARR; // Memory Address Read Register
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uint16 CR; // Control Register
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uint16 CR_cache; // Cache for BG/SPR enable
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uint16 RCR; // Raster Compare Register
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uint16 BXR; // Background X-Scroll Register
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uint16 BYR; // Background Y-Scroll Register
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uint16 MWR; // Memory Width Register
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uint16 HSR; // Horizontal Sync Register
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uint16 HDR; // Horizontal Display Register
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uint16 VSR;
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uint16 VDR;
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uint16 VCR;
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uint16 DCR;
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uint16 SOUR;
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uint16 DESR;
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uint16 LENR;
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uint16 DVSSR;
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// Internal SAT DMA transfer variables.
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//uint16 SAT_SOUR;
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//uint16 SAT_DESR;
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//uint16 SAT_LENR;
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int32 VDMA_CycleCounter;
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uint32 RCRCount;
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bool pending_read;
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uint16 pending_read_addr;
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uint16 read_buffer;
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uint8 write_latch; // LSB
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bool pending_write;
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uint16 pending_write_addr;
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uint16 pending_write_latch;
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uint8 status;
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uint16 SAT[0x100];
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uint16 VRAM[65536]; //VRAM_Size];
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union
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{
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uint64 bg_tile_cache64[65536 / 16][8]; // Tile, y, x
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uint8 bg_tile_cache[65536 / 16][8][8];
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};
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uint16 DMAReadBuffer;
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bool DMAReadWrite;
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bool DMARunning;
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bool DMAPending;
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bool SATBPending;
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bool burst_mode;
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uint32 BG_YOffset; // Reloaded from BYR at start of display area?
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uint32 BG_XOffset; // Reloaded from BXR at each scanline, methinks.
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uint32 HSW_cache, HDS_cache, HDW_cache, HDE_cache;
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uint32 VDS_cache;
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uint32 VSW_cache;
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uint32 VDW_cache;
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uint32 VCR_cache;
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uint16 MWR_cache;
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uint32 BG_YMoo;
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bool NeedRCRInc, NeedVBIRQTest, NeedSATDMATest, NeedBGYInc;
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int HPhase, VPhase;
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int32 HPhaseCounter, VPhaseCounter;
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int32 sprite_cg_fetch_counter;
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int32 mystery_counter;
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bool mystery_phase;
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uint16 linebuf[1024 + 512];
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uint32 pixel_desu;
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int32 pixel_copy_count;
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uint32 userle; // User layer enable.
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bool unlimited_sprites;
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int active_sprites;
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SPRLE SpriteList[64 * 2]; // (see unlimited_sprites option, *2 to accommodate 32-pixel-width sprites ) //16];
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};
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#endif
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@ -1,4 +0,0 @@
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#ifndef _MEDNAFEN_MOVIE_H
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#define _MEDNAFEN_MOVIE_H
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#endif
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