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https://github.com/libretro/beetle-pce-fast-libretro.git
synced 2024-11-26 17:40:40 +00:00
176 lines
3.5 KiB
C
176 lines
3.5 KiB
C
#ifndef _PCE_VDC_H
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#define _PCE_VDC_H
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#include "../git.h"
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#include "huc6280.h"
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#define REGSETP(_reg, _data, _msb) { _reg &= 0xFF << ((_msb) ? 0 : 8); _reg |= (_data) << ((_msb) ? 8 : 0); }
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#define REGGETP(_reg, _msb) ((_reg >> ((_msb) ? 8 : 0)) & 0xFF)
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#ifdef __cplusplus
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extern "C" {
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#endif
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static const uint8 vram_inc_tab[4] = { 1, 32, 64, 128 };
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typedef struct
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{
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uint8 priority[2];
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uint16 winwidths[2];
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uint8 st_mode;
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} vpc_t;
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extern vpc_t vpc;
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static const int VRAM_Size = 0x8000;
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static const int VRAM_SizeMask = 0x8000 - 1; //0x7FFF;
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static const int VRAM_BGTileNoMask = (0x8000 - 1) / 16; //0x7FF;
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typedef struct
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{
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uint8 CR;
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bool lc263; // 263 line count if set, 262 if not
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bool bw; // Black and White
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uint8 dot_clock; // Dot Clock(5, 7, or 10 MHz = 0, 1, 2)
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uint16 color_table[0x200];
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uint16 color_table_cache[0x200];
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uint16 ctaddress;
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} vce_t;
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extern vce_t vce;
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typedef struct
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{
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int16 y;
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uint16 height;
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uint16 x;
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uint16 no;
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uint16 flags;
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bool cgmode;
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} SAT_Cache_t;
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typedef struct
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{
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uint32 display_counter;
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int32 sat_dma_slcounter;
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uint8 select;
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uint16 MAWR; // Memory Address Write Register
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uint16 MARR; // Memory Address Read Register
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uint16 CR; // Control Register
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uint16 RCR; // Raster Compare Register
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uint16 BXR; // Background X-Scroll Register
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uint16 BYR; // Background Y-Scroll Register
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uint16 MWR; // Memory Width Register
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uint16 HSR; // Horizontal Sync Register
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uint16 HDR; // Horizontal Display Register
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uint16 VSR;
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uint16 VDR;
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uint16 VCR;
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uint16 DCR;
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uint16 SOUR;
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uint16 DESR;
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uint16 LENR;
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uint16 SATB;
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uint32 RCRCount;
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uint16 read_buffer;
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uint8 write_latch;
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uint8 status;
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uint16 DMAReadBuffer;
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bool DMAReadWrite;
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bool DMARunning;
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bool SATBPending;
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bool burst_mode;
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uint32 BG_YOffset;
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uint32 BG_XOffset;
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int SAT_Cache_Valid; // 64 through 128, depending on the number of 32-pixel-wide sprites.
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SAT_Cache_t SAT_Cache[128]; //64];
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uint16 SAT[0x100];
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uint16 VRAM[65536]; //VRAM_Size];
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uint64 bg_tile_cache[4096 * 8]; // Tile, y, x
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uint8 spr_tile_cache[1024][16][16]; // Tile, y, x
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uint8 spr_tile_clean[1024]; //VRAM_Size / 64];
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} vdc_t;
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extern vdc_t *vdc;
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void VDC_SetPixelFormat(const uint8* CustomColorMap, const uint32 CustomColorMapLen);
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void VDC_RunFrame(EmulateSpecStruct *espec, bool IsHES);
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void VDC_SetLayerEnableMask(uint64 mask);
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DECLFW(VDC_Write);
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DECLFR(VCE_Read);
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static INLINE uint8 VDC_Read(unsigned int A)
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{
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uint8 ret = 0;
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int msb = A & 1;
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int chip = 0;
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A &= 0x3;
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switch(A)
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{
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case 0x0:
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ret = vdc->status;
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vdc->status &= ~0x3F;
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HuC6280_IRQEnd(MDFN_IQIRQ1); // Clear VDC IRQ line
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break;
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case 0x2:
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case 0x3:
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ret = REGGETP(vdc->read_buffer, msb);
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if(vdc->select == 0x2) // VRR - VRAM Read Register
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{
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if(msb)
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{
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vdc->MARR += vram_inc_tab[(vdc->CR >> 11) & 0x3];
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vdc->read_buffer = vdc->VRAM[vdc->MARR & VRAM_SizeMask];
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}
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}
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break;
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}
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if(A == 1)
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{
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if(vce.dot_clock > 0)
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ret = 0x40;
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}
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return(ret);
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}
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DECLFW(VCE_Write);
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void VDC_Init(void) MDFN_COLD;
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void VDC_Close(void) MDFN_COLD;
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void VDC_Reset(void) MDFN_COLD;
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void VDC_Power(void) MDFN_COLD;
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int VDC_StateAction(StateMem *sm, int load, int data_only);
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void MDFN_FASTCALL VDC_Write_ST(uint32 A, uint8 V);
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#ifdef __cplusplus
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}
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#endif
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#endif
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