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https://github.com/libretro/beetle-psx-libretro.git
synced 2024-11-23 16:59:49 +00:00
Update cpu.cpp
This commit is contained in:
twinaphex
parent
09f1f88a67
commit
12f99e491a
@ -345,20 +345,20 @@ INLINE void PS_CPU::WriteMemory(int32_t ×tamp, uint32_t address, uint32_t v
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}
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else
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{
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if(BIU & 0x800) // Instruction cache is enabled/active
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if(BIU & BIU_ENABLE_ICACHE_S1) // Instruction cache is enabled/active
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{
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if(BIU & 0x4) // TAG test mode.
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if(BIU & (BIU_TAG_TEST_MODE | BIU_INVALIDATE_MODE | BIU_LOCK_MODE))
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{
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// TODO: Respect written value.
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__ICache *ICI = &ICache[((address & 0xFF0) >> 2)];
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const uint8_t valid_bits = 0x00;
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const uint8 valid_bits = (BIU & BIU_TAG_TEST_MODE) ? ((value << ((address & 0x3) * 8)) & 0x0F) : 0x00;
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__ICache* const ICI = &ICache[((address & 0xFF0) >> 2)];
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ICI[0].TV = ((valid_bits & 0x01) ? 0x00 : 0x02) | ((BIU & 0x800) ? 0x0 : 0x1);
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ICI[1].TV = ((valid_bits & 0x02) ? 0x00 : 0x02) | ((BIU & 0x800) ? 0x0 : 0x1);
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ICI[2].TV = ((valid_bits & 0x04) ? 0x00 : 0x02) | ((BIU & 0x800) ? 0x0 : 0x1);
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ICI[3].TV = ((valid_bits & 0x08) ? 0x00 : 0x02) | ((BIU & 0x800) ? 0x0 : 0x1);
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//
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// Set validity bits and tag.
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//
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for(unsigned i = 0; i < 4; i++)
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ICI[i].TV = ((valid_bits & (1U << i)) ? 0x00 : 0x02) | (address & 0xFFFFFFF0) | (i << 2);
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}
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else if(!(BIU & 0x1))
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else
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{
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ICache[(address & 0xFFC) >> 2].Data = value << ((address & 0x3) * 8);
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}
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@ -375,6 +375,75 @@ INLINE void PS_CPU::WriteMemory(int32_t ×tamp, uint32_t address, uint32_t v
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}
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}
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INLINE uint32 PS_CPU::ReadInstruction(pscpu_timestamp_t ×tamp, uint32 address)
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{
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uint32 instr = ICache[(address & 0xFFC) >> 2].Data;
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if(ICache[(address & 0xFFC) >> 2].TV != address)
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{
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ReadAbsorb[ReadAbsorbWhich] = 0;
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ReadAbsorbWhich = 0;
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// FIXME: Handle executing out of scratchpad.
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if(address >= 0xA0000000 || !(BIU & 0x800))
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{
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instr = LoadU32_LE((uint32_t *)&FastMap[address >> FAST_MAP_SHIFT][address]);
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if (!psx_cpu_overclock)
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{
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// Approximate best-case cache-disabled time, per PS1 tests
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// (executing out of 0xA0000000+); it can be 5 in
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// *some* sequences of code(like a lot of sequential "nop"s,
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// probably other simple instructions too).
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timestamp += 4;
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}
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}
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else
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{
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__ICache *ICI = &ICache[((address & 0xFF0) >> 2)];
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const uint32_t *FMP = (uint32_t *)&FastMap[(address &~ 0xF) >> FAST_MAP_SHIFT][address &~ 0xF];
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// | 0x2 to simulate (in)validity bits.
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ICI[0x00].TV = (address &~ 0xF) | 0x00 | 0x2;
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ICI[0x01].TV = (address &~ 0xF) | 0x04 | 0x2;
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ICI[0x02].TV = (address &~ 0xF) | 0x08 | 0x2;
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ICI[0x03].TV = (address &~ 0xF) | 0x0C | 0x2;
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// When overclock is enabled, remove code cache fetch latency
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if (!psx_cpu_overclock)
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timestamp += 3;
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switch(address & 0xC)
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{
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case 0x0:
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if (!psx_cpu_overclock)
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timestamp++;
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ICI[0x00].TV &= ~0x2;
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ICI[0x00].Data = LoadU32_LE(&FMP[0]);
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case 0x4:
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if (!psx_cpu_overclock)
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timestamp++;
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ICI[0x01].TV &= ~0x2;
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ICI[0x01].Data = LoadU32_LE(&FMP[1]);
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case 0x8:
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if (!psx_cpu_overclock)
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timestamp++;
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ICI[0x02].TV &= ~0x2;
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ICI[0x02].Data = LoadU32_LE(&FMP[2]);
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case 0xC:
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if (!psx_cpu_overclock)
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timestamp++;
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ICI[0x03].TV &= ~0x2;
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ICI[0x03].Data = LoadU32_LE(&FMP[3]);
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break;
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}
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instr = ICache[(address & 0xFFC) >> 2].Data;
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}
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}
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return instr;
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}
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uint32_t PS_CPU::Exception(uint32_t code, uint32_t PC, const uint32 NP, const uint32_t NPM, const uint32_t instr)
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{
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const bool AfterBranchInstr = !(NPM & 0x1);
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@ -383,12 +452,6 @@ uint32_t PS_CPU::Exception(uint32_t code, uint32_t PC, const uint32 NP, const ui
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assert(code < 16);
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if(code != EXCEPTION_INT && code != EXCEPTION_BP && code != EXCEPTION_SYSCALL)
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{
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PSX_DBG(PSX_DBG_WARNING, "Exception: %08x @ PC=0x%08x(IBDS=%d) -- IPCache=0x%02x -- IPEND=0x%02x -- SR=0x%08x ; IRQC_Status=0x%04x -- IRQC_Mask=0x%04x\n", code, PC, BranchTaken, IPCache, (CP0.CAUSE >> 8) & 0xFF, CP0.SR,
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::IRQ_GetRegister(IRQ_GSREG_STATUS, NULL, 0), ::IRQ_GetRegister(IRQ_GSREG_MASK, NULL, 0));
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}
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if(CP0.SR & (1 << 22)) // BEV
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handler = 0xBFC00180;
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@ -488,8 +551,9 @@ int32_t PS_CPU::RunReal(int32_t timestamp_in)
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}
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#endif
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// We can't fold this into the ICache[] != PC handling, since the lower 2 bits of TV
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// are already used for cache management purposes and it assumes that the lower 2 bits of PC will be 0.
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//
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// Instruction fetch
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//
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if(MDFN_UNLIKELY(PC & 0x3))
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{
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// This will block interrupt processing, but since we're going more for keeping broken homebrew/hacks from working
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@ -499,75 +563,17 @@ int32_t PS_CPU::RunReal(int32_t timestamp_in)
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goto OpDone;
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}
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instr = ICache[(PC & 0xFFC) >> 2].Data;
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instr = ReadInstruction(timestamp, PC);
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if(ICache[(PC & 0xFFC) >> 2].TV != PC)
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{
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ReadAbsorb[ReadAbsorbWhich] = 0;
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ReadAbsorbWhich = 0;
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// FIXME: Handle executing out of scratchpad.
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if(PC >= 0xA0000000 || !(BIU & 0x800))
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{
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instr = LoadU32_LE((uint32_t *)&FastMap[PC >> FAST_MAP_SHIFT][PC]);
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if (!psx_cpu_overclock)
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{
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// Approximate best-case cache-disabled time, per PS1 tests
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// (executing out of 0xA0000000+); it can be 5 in
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// *some* sequences of code(like a lot of sequential "nop"s,
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// probably other simple instructions too).
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timestamp += 4;
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}
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}
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else
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{
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__ICache *ICI = &ICache[((PC & 0xFF0) >> 2)];
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const uint32_t *FMP = (uint32_t *)&FastMap[(PC &~ 0xF) >> FAST_MAP_SHIFT][PC &~ 0xF];
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// | 0x2 to simulate (in)validity bits.
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ICI[0x00].TV = (PC &~ 0xF) | 0x00 | 0x2;
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ICI[0x01].TV = (PC &~ 0xF) | 0x04 | 0x2;
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ICI[0x02].TV = (PC &~ 0xF) | 0x08 | 0x2;
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ICI[0x03].TV = (PC &~ 0xF) | 0x0C | 0x2;
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// When overclock is enabled, remove code cache fetch latency
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if (!psx_cpu_overclock)
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timestamp += 3;
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switch(PC & 0xC)
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{
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case 0x0:
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if (!psx_cpu_overclock)
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timestamp++;
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ICI[0x00].TV &= ~0x2;
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ICI[0x00].Data = LoadU32_LE(&FMP[0]);
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case 0x4:
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if (!psx_cpu_overclock)
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timestamp++;
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ICI[0x01].TV &= ~0x2;
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ICI[0x01].Data = LoadU32_LE(&FMP[1]);
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case 0x8:
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if (!psx_cpu_overclock)
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timestamp++;
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ICI[0x02].TV &= ~0x2;
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ICI[0x02].Data = LoadU32_LE(&FMP[2]);
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case 0xC:
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if (!psx_cpu_overclock)
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timestamp++;
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ICI[0x03].TV &= ~0x2;
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ICI[0x03].Data = LoadU32_LE(&FMP[3]);
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break;
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}
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instr = ICache[(PC & 0xFFC) >> 2].Data;
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}
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}
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//printf("PC=%08x, SP=%08x - op=0x%02x - funct=0x%02x - instr=0x%08x\n", PC, GPR[29], instr >> 26, instr & 0x3F, instr);
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//for(int i = 0; i < 32; i++)
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// printf("%02x : %08x\n", i, GPR[i]);
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//printf("\n");
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//
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// Instruction decode
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//
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opf = instr & 0x3F;
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if(instr & (0x3F << 26))
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@ -575,18 +581,10 @@ int32_t PS_CPU::RunReal(int32_t timestamp_in)
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opf |= IPCache;
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#if 0
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{
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uint32_t tmp = (ReadAbsorb[ReadAbsorbWhich] + 0x7FFFFFFF) >> 31;
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ReadAbsorb[ReadAbsorbWhich] -= tmp;
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timestamp = timestamp + 1 - tmp;
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}
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#else
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if(ReadAbsorb[ReadAbsorbWhich])
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ReadAbsorb[ReadAbsorbWhich]--;
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else
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timestamp++;
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#endif
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#define DO_LDS() { GPR[LDWhich] = LDValue; ReadAbsorb[LDWhich] = LDAbsorb; ReadFudge = LDWhich; ReadAbsorbWhich |= LDWhich & 0x1F; LDWhich = 0x20; }
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#define BEGIN_OPF(name) { op_##name:
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@ -160,6 +160,8 @@ class PS_CPU
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template<typename T> T ReadMemory(int32_t ×tamp, uint32_t address, bool DS24 = false, bool LWC_timing = false);
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template<typename T> void WriteMemory(int32_t ×tamp, uint32_t address, uint32_t value, bool DS24 = false);
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uint32 ReadInstruction(pscpu_timestamp_t ×tamp, uint32 address);
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// Mednafen debugger stuff follows:
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public:
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void SetCPUHook(void (*cpuh)(const int32_t timestamp, uint32_t pc), void (*addbt)(uint32_t from, uint32_t to, bool exception));
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