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https://github.com/libretro/beetle-psx-libretro.git
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272 lines
7.2 KiB
C
272 lines
7.2 KiB
C
/***************************************************************************
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* Copyright (C) 2016 by iCatButler *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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/**************************************************************************
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* pgxp_gte.c
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* PGXP - Parallel/Precision Geometry Xform Pipeline
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*
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* Created on: 12 Mar 2016
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* Author: iCatButler
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***************************************************************************/
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#include <string.h>
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#include <math.h>
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#include "pgxp_gte.h"
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#include "pgxp_main.h"
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#include "pgxp_value.h"
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#include "pgxp_mem.h"
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#include "pgxp_debug.h"
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#include "pgxp_cpu.h"
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#include "pgxp_gpu.h"
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// GTE registers
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PGXP_value GTE_data_reg_mem[32];
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PGXP_value GTE_ctrl_reg_mem[32];
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PGXP_value* GTE_data_reg = GTE_data_reg_mem;
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PGXP_value* GTE_ctrl_reg = GTE_ctrl_reg_mem;
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void PGXP_InitGTE()
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{
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memset(GTE_data_reg_mem, 0, sizeof(GTE_data_reg_mem));
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memset(GTE_ctrl_reg_mem, 0, sizeof(GTE_ctrl_reg_mem));
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}
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// Instruction register decoding
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#define op(_instr) (_instr >> 26) // The op part of the instruction register
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#define func(_instr) ((_instr) & 0x3F) // The funct part of the instruction register
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#define sa(_instr) ((_instr >> 6) & 0x1F) // The sa part of the instruction register
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#define rd(_instr) ((_instr >> 11) & 0x1F) // The rd part of the instruction register
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#define rt(_instr) ((_instr >> 16) & 0x1F) // The rt part of the instruction register
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#define rs(_instr) ((_instr >> 21) & 0x1F) // The rs part of the instruction register
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#define imm(_instr) (_instr & 0xFFFF) // The immediate part of the instruction register
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#define SX0 (GTE_data_reg[ 12 ].x)
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#define SY0 (GTE_data_reg[ 12 ].y)
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#define SX1 (GTE_data_reg[ 13 ].x)
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#define SY1 (GTE_data_reg[ 13 ].y)
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#define SX2 (GTE_data_reg[ 14 ].x)
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#define SY2 (GTE_data_reg[ 14 ].y)
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#define SXY0 (GTE_data_reg[ 12 ])
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#define SXY1 (GTE_data_reg[ 13 ])
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#define SXY2 (GTE_data_reg[ 14 ])
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#define SXYP (GTE_data_reg[ 15 ])
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void PGXP_pushSXYZ2f(float _x, float _y, float _z, unsigned int _v)
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{
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static unsigned int uCount = 0;
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low_value temp;
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// push values down FIFO
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SXY0 = SXY1;
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SXY1 = SXY2;
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SXY2.x = _x;
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SXY2.y = _y;
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SXY2.z = (PGXP_GetModes() & PGXP_TEXTURE_CORRECTION) ? _z : 1.f;
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SXY2.value = _v;
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SXY2.flags = VALID_ALL;
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SXY2.count = uCount++;
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// cache value in GPU plugin
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temp.word = _v;
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if(PGXP_GetModes() & PGXP_VERTEX_CACHE)
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PGXP_CacheVertex(temp.x, temp.y, &SXY2);
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else
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PGXP_CacheVertex(0, 0, NULL);
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#ifdef GTE_LOG
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GTE_LOG("PGXP_PUSH (%f, %f) %u %u|", SXY2.x, SXY2.y, SXY2.flags, SXY2.count);
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#endif
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}
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void PGXP_pushSXYZ2s(s64 _x, s64 _y, s64 _z, u32 v)
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{
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float fx = (float)(_x) / (float)(1 << 16);
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float fy = (float)(_y) / (float)(1 << 16);
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float fz = (float)(_z);
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//if(Config.PGXP_GTE)
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PGXP_pushSXYZ2f(fx, fy, fz, v);
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}
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#define VX(n) (psxRegs.CP2D.p[ n << 1 ].sw.l)
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#define VY(n) (psxRegs.CP2D.p[ n << 1 ].sw.h)
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#define VZ(n) (psxRegs.CP2D.p[ (n << 1) + 1 ].sw.l)
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int PGXP_NLCIP_valid(u32 sxy0, u32 sxy1, u32 sxy2)
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{
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Validate(&SXY0, sxy0);
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Validate(&SXY1, sxy1);
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Validate(&SXY2, sxy2);
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if (((SXY0.flags & SXY1.flags & SXY2.flags & VALID_01) == VALID_01))// && Config.PGXP_GTE && (Config.PGXP_Mode > 0))
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return 1;
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return 0;
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}
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float PGXP_NCLIP()
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{
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float nclip = ((SX0 * SY1) + (SX1 * SY2) + (SX2 * SY0) - (SX0 * SY2) - (SX1 * SY0) - (SX2 * SY1));
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// ensure fractional values are not incorrectly rounded to 0
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float nclipAbs = fabs(nclip);
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if (( 0.1f < nclipAbs) && (nclipAbs < 1.f))
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nclip += (nclip < 0.f ? -1 : 1);
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//float AX = SX1 - SX0;
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//float AY = SY1 - SY0;
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//float BX = SX2 - SX0;
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//float BY = SY2 - SY0;
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//// normalise A and B
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//float mA = sqrt((AX*AX) + (AY*AY));
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//float mB = sqrt((BX*BX) + (BY*BY));
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//// calculate AxB to get Z component of C
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//float CZ = ((AX * BY) - (AY * BX)) * (1 << 12);
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return nclip;
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}
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static PGXP_value PGXP_MFC2_int(u32 reg)
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{
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switch (reg)
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{
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case 15:
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GTE_data_reg[reg] = SXYP = SXY2;
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break;
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}
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return GTE_data_reg[reg];
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}
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static void PGXP_MTC2_int(PGXP_value value, u32 reg)
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{
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switch(reg)
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{
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case 15:
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// push FIFO
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SXY0 = SXY1;
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SXY1 = SXY2;
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SXY2 = value;
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SXYP = SXY2;
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break;
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case 31:
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return;
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}
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GTE_data_reg[reg] = value;
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}
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////////////////////////////////////
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// Data transfer tracking
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////////////////////////////////////
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void MFC2(int reg) {
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psx_value val;
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val.d = GTE_data_reg[reg].value;
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switch (reg) {
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case 1:
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case 3:
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case 5:
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case 8:
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case 9:
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case 10:
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case 11:
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GTE_data_reg[reg].value = (s32)val.sw.l;
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GTE_data_reg[reg].y = 0.f;
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break;
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case 7:
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case 16:
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case 17:
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case 18:
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case 19:
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GTE_data_reg[reg].value = (u32)val.w.l;
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GTE_data_reg[reg].y = 0.f;
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break;
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case 15:
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GTE_data_reg[reg] = SXY2;
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break;
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case 28:
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case 29:
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// psxRegs.CP2D.p[reg].d = LIM(IR1 >> 7, 0x1f, 0, 0) | (LIM(IR2 >> 7, 0x1f, 0, 0) << 5) | (LIM(IR3 >> 7, 0x1f, 0, 0) << 10);
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break;
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}
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}
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void PGXP_GTE_MFC2(u32 instr, u32 rtVal, u32 rdVal)
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{
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// CPU[Rt] = GTE_D[Rd]
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Validate(>E_data_reg[rd(instr)], rdVal);
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//MFC2(rd(instr));
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CPU_reg[rt(instr)] = GTE_data_reg[rd(instr)];
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CPU_reg[rt(instr)].value = rtVal;
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}
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void PGXP_GTE_MTC2(u32 instr, u32 rdVal, u32 rtVal)
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{
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// GTE_D[Rd] = CPU[Rt]
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Validate(&CPU_reg[rt(instr)], rtVal);
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PGXP_MTC2_int(CPU_reg[rt(instr)], rd(instr));
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GTE_data_reg[rd(instr)].value = rdVal;
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}
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void PGXP_GTE_CFC2(u32 instr, u32 rtVal, u32 rdVal)
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{
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// CPU[Rt] = GTE_C[Rd]
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Validate(>E_ctrl_reg[rd(instr)], rdVal);
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CPU_reg[rt(instr)] = GTE_ctrl_reg[rd(instr)];
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CPU_reg[rt(instr)].value = rtVal;
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}
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void PGXP_GTE_CTC2(u32 instr, u32 rdVal, u32 rtVal)
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{
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// GTE_C[Rd] = CPU[Rt]
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Validate(&CPU_reg[rt(instr)], rtVal);
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GTE_ctrl_reg[rd(instr)] = CPU_reg[rt(instr)];
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GTE_ctrl_reg[rd(instr)].value = rdVal;
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}
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////////////////////////////////////
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// Memory Access
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////////////////////////////////////
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void PGXP_GTE_LWC2(u32 instr, u32 rtVal, u32 addr)
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{
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// GTE_D[Rt] = Mem[addr]
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PGXP_value val;
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ValidateAndCopyMem(&val, addr, rtVal);
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PGXP_MTC2_int(val, rt(instr));
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}
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void PGXP_GTE_SWC2(u32 instr, u32 rtVal, u32 addr)
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{
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// Mem[addr] = GTE_D[Rt]
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Validate(>E_data_reg[rt(instr)], rtVal);
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WriteMem(>E_data_reg[rt(instr)], addr);
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}
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