mirror of
https://github.com/libretro/beetle-psx-libretro.git
synced 2024-11-24 01:09:51 +00:00
447 lines
11 KiB
TableGen
447 lines
11 KiB
TableGen
class DagOp;
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def add : DagOp;
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def sub : DagOp;
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def and : DagOp;
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def or : DagOp;
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def nor : DagOp;
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def xor : DagOp;
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def mul : DagOp; // word * word -> dword
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def div : DagOp; // word / word -> word
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def mod : DagOp; // word % word -> word
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def shl : DagOp;
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def shra : DagOp;
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def shrl : DagOp;
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def signext : DagOp;
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def zeroext : DagOp;
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def eq : DagOp;
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def ge : DagOp;
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def gt : DagOp;
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def le : DagOp;
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def lt : DagOp;
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def neq : DagOp;
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def branch : DagOp;
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def copreg : DagOp;
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def copcreg : DagOp;
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def gpr : DagOp;
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def hi : DagOp;
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def lo : DagOp;
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def check_overflow : DagOp;
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def pcd : DagOp;
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def raise : DagOp;
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def load : DagOp;
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def store : DagOp;
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def block : DagOp;
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def if : DagOp;
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def let : DagOp;
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def rlet: DagOp;
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def set : DagOp;
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def when : DagOp;
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def unsigned : DagOp;
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def signed : DagOp;
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// Special traps
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def break : DagOp;
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def syscall : DagOp;
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def copfun : DagOp;
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class Exception;
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def ArithmeticOverflow : Exception;
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class BaseInst<bits<6> op, string disasm, dag eval> {
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bits<6> Opcode = op;
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string Disasm = disasm;
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dag Eval = eval;
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}
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class IType<bits<6> op, string disasm, dag eval> : BaseInst<op, disasm, eval> {
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// 31-26: op
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// 25-21: rs
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// 20-16: rt
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// 15-0: imm
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}
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class RIType<bits<6> op, bits<5> funct, string disasm, dag eval> : BaseInst<op, disasm, eval> {
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// 31-26: op
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// 25-21: rs
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// 20-16: funct
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// 15-0: imm
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bits<5> Function = funct;
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}
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class JType<bits<6> op, string disasm, dag eval> : BaseInst<op, disasm, eval> {
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// 31-26: op
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// 25-0: imm
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}
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class RType<bits<6> funct, string disasm, dag eval> : BaseInst<0b000000, disasm, eval> {
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// 31-26: op
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// 25-21: rs
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// 20-16: rt
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// 15-11: rd
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// 10-6: shamt
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// 5-0: funct
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bits<6> Function = funct;
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}
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class SType<bits<6> funct, string disasm, dag eval> : BaseInst<0b000000, disasm, eval> {
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// 31-26: op
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// 25-6: code
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// 5-0: funct
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bits<6> Function = funct;
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}
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class CFType<bits<6> op, bits<5> funct, string disasm, dag eval> : BaseInst<op, disasm, eval> {
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// 31-26: op
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// 27-26: cop
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// 25-21: funct
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// 20-16: rt
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// 15-11: rd
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// 24-0: cofun
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bits<5> Function = funct;
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}
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multiclass CFDef<bits<6> op, bits<5> funct, string disasm, dag eval> {
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def : CFType<!add(op, 0b000000), funct, disasm, eval>;
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def : CFType<!add(op, 0b000001), funct, disasm, eval>;
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def : CFType<!add(op, 0b000010), funct, disasm, eval>;
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def : CFType<!add(op, 0b000011), funct, disasm, eval>;
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}
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def ADD : RType<0b100000, "add %$rd, %$rs, %$rt",
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(block
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(check_overflow (add (gpr $rs), (gpr $rt))),
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(set (gpr $rd), (add (gpr $rs), (gpr $rt))))
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>;
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def ADDI : IType<0b001000, "addi %$rt, %$rs, $eimm",
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(let $eimm, (signext 16, $imm),
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(block
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(check_overflow (add (gpr $rs), $eimm)),
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(set (gpr $rt), (add (gpr $rs), $eimm))))
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>;
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def ADDIU : IType<0b001001, "addiu %$rt, %$rs, $eimm",
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(let $eimm, (signext 16, $imm),
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(set (gpr $rt), (add (gpr $rs), $eimm)))
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>;
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def ADDU : RType<0b100001, "addu %$rd, %$rs, %$rt",
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(set (gpr $rd), (add (gpr $rs), (gpr $rt)))
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>;
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def AND : RType<0b100100, "and %$rd, %$rs, %$rt",
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(set (gpr $rd), (and (gpr $rs), (gpr $rt)))
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>;
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def ANDI : IType<0b001100, "andi %$rt, %$rs, $eimm",
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(let $eimm, (zeroext 16, $imm),
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(set (gpr $rt), (and (gpr $rs), $eimm)))
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>;
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def BEQ : IType<0b000100, "beq %$rs, %$rt, $target",
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(let $target, (add (pcd), (signext 18, (shl $imm, 2))),
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(when (eq (unsigned (gpr $rs)), (unsigned (gpr $rt))),
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(branch $target)))
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>;
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def BGEZ : RIType<0b000001, 0b00001, "bgez %$rs, $target",
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(let $target, (add (pcd), (signext 18, (shl $imm, 2))),
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(when (ge (signed (gpr $rs)), 0),
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(branch $target)))
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>;
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def BGEZAL : RIType<0b000001, 0b10001, "bgezal %$rs, $target",
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(block
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(set (gpr 31), (pcd)),
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(let $target, (add (pcd), (signext 18, (shl $imm, 2))),
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(when (ge (signed (gpr $rs)), 0),
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(branch $target))))
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>;
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// This isn't really RIType, but that lets us constrain rt
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def BGTZ : RIType<0b000111, 0b00000, "bgtz %$rs, $target",
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(let $target, (add (pcd), (signext 18, (shl $imm, 2))),
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(when (gt (signed (gpr $rs)), 0),
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(branch $target)))
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>;
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// This isn't really RIType, but that lets us constrain rt
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def BLEZ : RIType<0b000110, 0b00000, "blez %$rs, $target",
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(let $target, (add (pcd), (signext 18, (shl $imm, 2))),
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(when (le (signed (gpr $rs)), 0),
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(branch $target)))
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>;
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def BLTZ : RIType<0b000001, 0b00000, "bltz %$rs, $target",
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(let $target, (add (pcd), (signext 18, (shl $imm, 2))),
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(when (lt (signed (gpr $rs)), 0),
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(branch $target)))
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>;
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def BLTZAL : RIType<0b000001, 0b10000, "bltzal %$rs, $target",
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(block
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(set (gpr 31), (pcd)),
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(let $target, (add (pcd), (signext 18, (shl $imm, 2))),
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(when (lt (signed (gpr $rs)), 0),
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(branch $target))))
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>;
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def BNE : IType<0b000101, "bne %$rs, %$rt, $target",
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(let $target, (add (pcd), (signext 18, (shl $imm, 2))),
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(when (neq (gpr $rs), (gpr $rt)),
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(branch $target)))
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>;
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def BREAK : SType<0b001101, "break $code",
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(break $code)
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>;
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defm CFCz : CFDef<0b010000, 0b00010, "cfc$cop %$rt, $rd",
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(set (gpr $rt), (copcreg $cop, $rd))
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>;
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// HACK! This should be special cased.
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multiclass COPzType<string disasm, dag eval> {
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defm : CFDef<0b010000, 0b10000, disasm, eval>;
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defm : CFDef<0b010000, 0b10001, disasm, eval>;
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defm : CFDef<0b010000, 0b10010, disasm, eval>;
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defm : CFDef<0b010000, 0b10011, disasm, eval>;
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defm : CFDef<0b010000, 0b10100, disasm, eval>;
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defm : CFDef<0b010000, 0b10101, disasm, eval>;
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defm : CFDef<0b010000, 0b10110, disasm, eval>;
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defm : CFDef<0b010000, 0b10111, disasm, eval>;
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defm : CFDef<0b010000, 0b11000, disasm, eval>;
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defm : CFDef<0b010000, 0b11001, disasm, eval>;
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defm : CFDef<0b010000, 0b11010, disasm, eval>;
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defm : CFDef<0b010000, 0b11011, disasm, eval>;
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defm : CFDef<0b010000, 0b11100, disasm, eval>;
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defm : CFDef<0b010000, 0b11101, disasm, eval>;
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defm : CFDef<0b010000, 0b11110, disasm, eval>;
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defm : CFDef<0b010000, 0b11111, disasm, eval>;
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}
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defm COPz : COPzType<"cop$cop $cofun",
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(copfun $cop, $cofun)
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>;
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defm CTCz : CFDef<0b010000, 0b00110, "ctc$cop %$rt, $rd",
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(set (copcreg $cop, $rd), (gpr $rt))
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>;
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def DIV : RType<0b011010, "div %$rs, %$rt",
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(block
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(set (lo), (div (gpr $rs), (gpr $rt))),
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(set (hi), (mod (gpr $rs), (gpr $rt))))
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>;
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def DIVU : RType<0b011011, "divu %$rs, %$rt",
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(block
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(set (lo), (div (unsigned (gpr $rs)), (unsigned (gpr $rt)))),
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(set (hi), (mod (unsigned (gpr $rs)), (unsigned (gpr $rt)))))
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>;
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def J : JType<0b000010, "j $target",
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(let $target, (add (and (pcd), 0xF0000000), (zeroext 28, (shl $imm, 2))),
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(branch $target))
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>;
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def JAL : JType<0b000011, "jal $target",
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(block
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(set (gpr 31), (add (pcd), 4)),
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(let $target, (add (and (pcd), 0xF0000000), (zeroext 28, (shl $imm, 2))),
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(branch $target)))
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>;
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def JALR : RType<0b001001, "jalr %$rd, %$rs",
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(block
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(set (gpr $rd), (add (pcd), 4)),
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(branch (unsigned (gpr $rs))))
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>;
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def JR : RType<0b001000, "jr %$rs",
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(branch (unsigned (gpr $rs)))
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>;
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def LB : IType<0b100000, "lb %$rt, $offset(%$rs)",
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(let $offset, (signext 16, $imm),
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(set (gpr $rt), (signext 8, (load 8, (unsigned (add (gpr $rs), $offset))))))
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>;
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def LBU : IType<0b100100, "lbu %$rt, $offset(%$rs)",
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(let $offset, (signext 16, $imm),
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(set (gpr $rt), (zeroext 8, (load 8, (unsigned (add (gpr $rs), $offset))))))
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>;
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def LH : IType<0b100001, "lh %$rt, $offset(%$rs)",
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(let $offset, (signext 16, $imm),
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(set (gpr $rt), (signext 16, (load 16, (unsigned (add (gpr $rs), $offset))))))
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>;
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def LHU : IType<0b100101, "lhu %$rt, $offset(%$rs)",
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(let $offset, (signext 16, $imm),
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(set (gpr $rt), (zeroext 16, (load 16, (add (gpr $rs), $offset)))))
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>;
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def LUI : IType<0b001111, "lui %$rt, $imm",
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(set (gpr $rt), (shl $imm, 16))
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>;
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def LW : IType<0b100011, "lw %$rt, $offset(%$rs)",
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(let $offset, (signext 16, $imm),
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(set (gpr $rt), (load 32, (unsigned (add (gpr $rs), $offset)))))
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>;
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// XXX: LWCz instruction
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// XXX: LWL instruction
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// XXX: LWR instruction
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defm MFCz : CFDef<0b010000, 0b00000, "mfc$cop %$rt, $rd",
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(set (gpr $rt), (copreg $cop, $rd))
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>;
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def MFHI : RType<0b010000, "mfhi %$rd",
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(set (gpr $rd), (hi))
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>;
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def MFLO : RType<0b010010, "mflo %$rd",
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(set (gpr $rd), (lo))
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>;
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defm MTCz : CFDef<0b010000, 0b00100, "mtc$cop %$rt, $rd",
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(set (copreg $cop, $rd), (gpr $rt))
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>;
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def MTHI : RType<0b010001, "mthi %$rd",
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(set (hi), (gpr $rd))
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>;
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def MTLO : RType<0b010011, "mtlo %$rd",
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(set (lo), (gpr $rd))
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>;
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def MULT : RType<0b011000, "mult %$rs, %$rt",
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(rlet $_t, (mul (gpr $rs), (gpr $rt)),
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(set (lo), (and $_t, 0xFFFFFFFF)),
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(set (hi), (shrl $_t, 32)))
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>;
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def MULTU : RType<0b011001, "multu %$rs, %$rt",
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(rlet $_t, (mul (unsigned (gpr $rs)), (unsigned (gpr $rt))),
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(set (lo), (and $_t, 0xFFFFFFFF)),
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(set (hi), (shrl $_t, 32)))
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>;
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def NOR : RType<0b100111, "nor %$rd, %$rs, %$rt",
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(set (gpr $rd), (nor (gpr $rs), (gpr $rt)))
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>;
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def OR : RType<0b100101, "or %$rd, %$rs, %$rt",
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(set (gpr $rd), (or (gpr $rs), (gpr $rt)))
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>;
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def ORI : IType<0b001101, "ori %$rt, %$rs, $eimm",
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(let $eimm, (zeroext 16, $imm),
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(set (gpr $rt), (or (gpr $rs), $eimm)))
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>;
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def SB : IType<0b101000, "sb %$rt, $offset(%$rs)",
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(let $offset, (signext 16, $imm),
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(store 8, (unsigned (add (gpr $rs), $offset)), (gpr $rt)))
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>;
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def SH : IType<0b101001, "sh %$rt, $offset(%$rs)",
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(let $offset, (signext 16, $imm),
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(store 16, (unsigned (add (gpr $rs), $offset)), (gpr $rt)))
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>;
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def SLL : RType<0b000000, "sll %$rd, %$rt, $shamt",
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(set (gpr $rd), (shl (gpr $rt), $shamt))
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>;
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def SLLV : RType<0b000100, "sllv %$rd, %$rt, %$rs",
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(set (gpr $rd), (shl (gpr $rt), (gpr $rs)))
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>;
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def SLT : RType<0b101010, "slt %$rd, %$rs, %$rt",
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(if (lt (signed (gpr $rs)), (signed (gpr $rt))),
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(set (gpr $rd), 1),
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(set (gpr $rd), 0))
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>;
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def SLTI : IType<0b001010, "slti %$rt, %$rs, $eimm",
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(let $eimm, (signext 16, $imm),
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(if (lt (signed (gpr $rs)), $eimm),
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(set (gpr $rt), 1),
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(set (gpr $rt), 0)))
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>;
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def SLTIU : IType<0b001011, "sltiu %$rt, %$rs, $eimm",
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(let $eimm, (unsigned (signext 16, $imm)),
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(if (lt (unsigned (gpr $rs)), $eimm),
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(set (gpr $rt), 1),
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(set (gpr $rt), 0)))
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>;
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def SLTU : RType<0b101011, "sltu %$rd, %$rs, %$rt",
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(if (lt (unsigned (gpr $rs)), (unsigned (gpr $rt))),
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(set (gpr $rd), 1),
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(set (gpr $rd), 0))
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>;
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def SRA : RType<0b000011, "sra %$rd, %$rt, $shamt",
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(set (gpr $rd), (shra (gpr $rt), $shamt))
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>;
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def SRAV : RType<0b000111, "srav %$rd, %$rt, $shamt",
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(set (gpr $rd), (shra (gpr $rt), (gpr $rs)))
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>;
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def SRL : RType<0b000010, "srl %$rd, %$rt, $shamt",
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(set (gpr $rd), (shrl (gpr $rt), $shamt))
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>;
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def SRLV : RType<0b000110, "srlv %$rd, %$rt, $shamt",
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(set (gpr $rd), (shrl (gpr $rt), (gpr $rs)))
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>;
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def SUB : RType<0b100010, "sub %$rd, %$rs, %$rt",
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(block
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(check_overflow (sub (gpr $rs), (gpr $rt))),
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(set (gpr $rd), (sub (gpr $rs), (gpr $rt))))
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>;
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def SUBU : RType<0b100011, "subu %$rd, %$rs, %$rt",
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(set (gpr $rd), (sub (gpr $rs), (gpr $rt)))
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>;
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def SW : IType<0b101011, "sw %$rt, $offset(%$rs)",
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(let $offset, (signext 16, $imm),
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(store 32, (unsigned (add (gpr $rs), $offset)), (gpr $rt)))
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>;
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// XXX: SWCz instruction
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// XXX: SWL instruction
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// XXX: SWR instruction
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def SYSCALL : SType<0b001100, "syscall $code",
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(syscall $code)
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>;
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def XOR : RType<0b100110, "xor %$rd, %$rs, %$rt",
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(set (gpr $rd), (xor (gpr $rs), (gpr $rt)))
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>;
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def XORI : IType<0b001110, "xori %$rt, %$rs, $eimm",
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(let $eimm, (zeroext 16, $imm),
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(set (gpr $rt), (xor (gpr $rs), $eimm)))
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>;
|