libretro/beetle-wswan-libretro
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Cleanups

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This commit is contained in:
libretroadmin 2023-02-27 17:56:04 +01:00
parent 02a85863f3
commit 64652b4724
6 changed files with 120 additions and 114 deletions
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4
mednafen/wswan/eeprom.c
View File

@ -253,7 +253,7 @@ int WSwan_EEPROMStateAction(StateMem *sm, int load, int data_only)
};
if(!MDFNSS_StateAction(sm, load, data_only, StateRegs, "EEPR", false))
return(0);
return 0;
return(1);
return 1;
}

12
mednafen/wswan/interrupt.c
View File

@ -14,7 +14,6 @@ static uint32 IVector_Cache;
static void RecalcInterrupt(void)
{
unsigned i;
IOn_Cache = false;
IOn_Which = 0;
IVector_Cache = 0;
@ -44,10 +43,13 @@ void WSwan_InterruptWrite(uint32 A, uint8 V)
switch(A)
{
case 0xB0:
IVectorBase = V; RecalcInterrupt();
IVectorBase = V;
RecalcInterrupt();
break;
case 0xB2:
IEnable = V; IStatus &= IEnable; RecalcInterrupt();
IEnable = V;
IStatus &= IEnable;
RecalcInterrupt();
break;
case 0xB6:
IStatus &= ~V;
@ -96,10 +98,10 @@ int WSwan_InterruptStateAction(StateMem *sm, int load, int data_only)
};
if(!MDFNSS_StateAction(sm, load, data_only, StateRegs, "INTR", false))
return(0);
return 0;
if(load)
RecalcInterrupt();
return(1);
return 1;
}

5
mednafen/wswan/rtc.c
View File

@ -122,7 +122,6 @@ int WSwan_RTCStateAction(StateMem *sm, int load, int data_only)
};
if(!MDFNSS_StateAction(sm, load, data_only, StateRegs, "RTC", false))
return(0);
return(1);
return 0;
return 1;
}

20
mednafen/wswan/sound.c
View File

@ -60,25 +60,22 @@ static uint32 last_ts;
#define MK_SAMPLE_CACHE \
{ \
int sample; \
sample = (((wsRAM[((SampleRAMPos << 6) + (sample_pos[ch] >> 1) + (ch << 4)) ] >> ((sample_pos[ch] & 1) ? 4 : 0)) & 0x0F)); \
int sample = (((wsRAM[((SampleRAMPos << 6) + (sample_pos[ch] >> 1) + (ch << 4)) ] >> ((sample_pos[ch] & 1) ? 4 : 0)) & 0x0F)); \
sample_cache[ch][0] = sample * ((volume[ch] >> 4) & 0x0F); \
sample_cache[ch][1] = sample * ((volume[ch] >> 0) & 0x0F); \
}
#define MK_SAMPLE_CACHE_NOISE \
{ \
int sample; \
sample = ((nreg & 1) ? 0xF : 0x0); \
int sample = ((nreg & 1) ? 0xF : 0x0); \
sample_cache[ch][0] = sample * ((volume[ch] >> 4) & 0x0F); \
sample_cache[ch][1] = sample * ((volume[ch] >> 0) & 0x0F); \
}
#define MK_SAMPLE_CACHE_VOICE \
{ \
int sample, half; \
sample = volume[ch]; \
half = sample >> 1; \
int sample = volume[ch]; \
int half = sample >> 1; \
sample_cache[ch][0] = (voice_volume & 4) ? sample : (voice_volume & 8) ? half : 0; \
sample_cache[ch][1] = (voice_volume & 1) ? sample : (voice_volume & 2) ? half : 0; \
}
@ -235,9 +232,7 @@ void WSwan_SoundWrite(uint32 A, uint8 V)
period[ch] = (period[ch] & 0x0700) | ((V & 0xFF) << 0);
}
else if(A >= 0x88 && A <= 0x8B)
{
volume[A - 0x88] = V;
}
else if(A == 0x8C)
sweep_value = V;
else if(A == 0x8D)
@ -294,7 +289,6 @@ uint8 WSwan_SoundRead(uint32 A)
if(A & 1)
return(period[ch] >> 8);
else
return(period[ch]);
}
else if(A >= 0x88 && A <= 0x8B)
@ -316,7 +310,7 @@ uint8 WSwan_SoundRead(uint32 A)
break;
}
return(0);
return 0;
}
int32 WSwan_SoundFlush(int16 **SoundBuf, int32 *SoundBufSize)
@ -427,7 +421,7 @@ int WSwan_SoundStateAction(StateMem *sm, int load, int data_only)
};
if(!MDFNSS_StateAction(sm, load, data_only, StateRegs, "PSG", false))
return(0);
return 0;
if(load)
{
@ -446,7 +440,7 @@ int WSwan_SoundStateAction(StateMem *sm, int load, int data_only)
}
}
return(1);
return 1;
}
void WSwan_SoundReset(void)

81
mednafen/wswan/v30mz.c
View File

@ -454,7 +454,8 @@ static struct {
{ \
if (ModRM >= 0xc0) \
I.regs.w[Mod_RM.RM.w[ModRM]]=val; \
else { \
else \
{ \
(*GetEA[ModRM])(); \
WriteWord( EA ,val); \
} \
@ -716,40 +717,57 @@ I.regs.w[IX] += -2 * I.DF + 1; CLK(6);
static INLINE void i_real_cmpsw(void)
{
uint32 src = GetMemW(DS1, I.regs.w[IY]); uint32 dst = GetMemW(DS0, I.regs.w[IX]); SUBW; I.regs.w[IY] += -4 * I.DF + 2;
I.regs.w[IX] += -4 * I.DF + 2; CLK(6);
uint32 src = GetMemW(DS1, I.regs.w[IY]);
uint32 dst = GetMemW(DS0, I.regs.w[IX]);
SUBW;
I.regs.w[IY] += -4 * I.DF + 2;
I.regs.w[IX] += -4 * I.DF + 2;
CLK(6);
}
static INLINE void i_real_stosb(void)
{
PutMemB(DS1,I.regs.w[IY],I.regs.b[AL]); I.regs.w[IY] += -2 * I.DF + 1; CLK(3);
PutMemB(DS1,I.regs.w[IY],I.regs.b[AL]);
I.regs.w[IY] += -2 * I.DF + 1;
CLK(3);
}
static INLINE void i_real_stosw(void)
{
PutMemW(DS1,I.regs.w[IY],I.regs.w[AW]); I.regs.w[IY] += -4 * I.DF + 2; CLK(3);
PutMemW(DS1,I.regs.w[IY],I.regs.w[AW]);
I.regs.w[IY] += -4 * I.DF + 2;
CLK(3);
}
static INLINE void i_real_lodsb(void)
{
I.regs.b[AL] = GetMemB(DS0,I.regs.w[IX]); I.regs.w[IX] += -2 * I.DF + 1; CLK(3);
I.regs.b[AL] = GetMemB(DS0,I.regs.w[IX]);
I.regs.w[IX] += -2 * I.DF + 1;
CLK(3);
}
static INLINE void i_real_lodsw(void)
{
I.regs.w[AW] = GetMemW(DS0,I.regs.w[IX]); I.regs.w[IX] += -4 * I.DF + 2; CLK(3);
I.regs.w[AW] = GetMemW(DS0,I.regs.w[IX]);
I.regs.w[IX] += -4 * I.DF + 2;
CLK(3);
}
static INLINE void i_real_scasb(void)
{
uint32 src = GetMemB(DS1, I.regs.w[IY]); uint32 dst = I.regs.b[AL]; SUBB;
I.regs.w[IY] += -2 * I.DF + 1; CLK(4);
uint32 src = GetMemB(DS1, I.regs.w[IY]);
uint32 dst = I.regs.b[AL]; SUBB;
I.regs.w[IY] += -2 * I.DF + 1;
CLK(4);
}
static INLINE void i_real_scasw(void)
{
uint32 src = GetMemW(DS1, I.regs.w[IY]); uint32 dst = I.regs.w[AW]; SUBW;
I.regs.w[IY] += -4 * I.DF + 2; CLK(4);
uint32 src = GetMemW(DS1, I.regs.w[IY]);
uint32 dst = I.regs.w[AW];
SUBW;
I.regs.w[IY] += -4 * I.DF + 2;
CLK(4);
}
static void DoOP(uint8 opcode)
@ -897,19 +915,14 @@ static void DoOP(uint8 opcode)
OP( 0x62, i_chkind )
{
uint32 low,high,tmp;
GetModRM;
low = GetRMWord(ModRM);
high = GetnextRMWord;
tmp = RegWord(ModRM);
uint32 low = GetRMWord(ModRM);
uint32 high = GetnextRMWord;
uint32 tmp = RegWord(ModRM);
CLK(13);
if (tmp<low || tmp>high)
{
nec_interrupt(5);
}
} OP_EPILOGUE;
OP( 0x68, i_push_d16 ) { uint32 tmp; FETCHuint16(tmp); PUSH(tmp); CLK(1); } OP_EPILOGUE;
@ -938,7 +951,7 @@ static void DoOP(uint8 opcode)
OP( 0x7e, i_jle ) { JMP((ZF)||(SF!=FLAG_O)); CLK(1); } OP_EPILOGUE;
OP( 0x7f, i_jnle ) { JMP((SF==FLAG_O)&&(!ZF)); CLK(1); } OP_EPILOGUE;
OP( 0x80, i_80pre ) { uint32 dst, src; GetModRM; dst = GetRMByte(ModRM); src = FETCH;
OP( 0x80, i_80pre ) { GetModRM; uint32 dst = GetRMByte(ModRM); uint32 src = FETCH;
CLKM(3, 1);
switch (ModRM & 0x38) {
case 0x00: ADDB; PutbackRMByte(ModRM,dst); break;
@ -952,7 +965,7 @@ static void DoOP(uint8 opcode)
}
} OP_EPILOGUE;
OP( 0x81, i_81pre ) { uint32 dst, src; GetModRM; dst = GetRMWord(ModRM); src = FETCH; src+= (FETCH << 8);
OP( 0x81, i_81pre ) { GetModRM; uint32 dst = GetRMWord(ModRM); uint32 src = FETCH; src+= (FETCH << 8);
CLKM(3, 1);
switch (ModRM & 0x38) {
case 0x00: ADDW; PutbackRMWord(ModRM,dst); break;
@ -966,7 +979,7 @@ static void DoOP(uint8 opcode)
}
} OP_EPILOGUE;
OP( 0x82, i_82pre ) { uint32 dst, src; GetModRM; dst = GetRMByte(ModRM); src = (uint8)((int8)FETCH);
OP( 0x82, i_82pre ) { GetModRM; uint32 dst = GetRMByte(ModRM); uint32 src = (uint8)((int8)FETCH);
CLKM(3,1);
switch (ModRM & 0x38) {
case 0x00: ADDB; PutbackRMByte(ModRM,dst); break;
@ -980,7 +993,7 @@ static void DoOP(uint8 opcode)
}
} OP_EPILOGUE;
OP( 0x83, i_83pre ) { uint32 dst, src; GetModRM; dst = GetRMWord(ModRM); src = (uint16)((int16)((int8)FETCH));
OP( 0x83, i_83pre ) { GetModRM; uint32 dst = GetRMWord(ModRM); uint32 src = (uint16)((int16)((int8)FETCH));
CLKM(3,1);
switch (ModRM & 0x38) {
case 0x00: ADDW; PutbackRMWord(ModRM,dst); break;
@ -999,13 +1012,13 @@ static void DoOP(uint8 opcode)
OP( 0x86, i_xchg_br8 ) { DEF_br8; RegByte(ModRM)=dst; PutbackRMByte(ModRM,src); CLKM(5,3); } OP_EPILOGUE;
OP( 0x87, i_xchg_wr16 ) { DEF_wr16; RegWord(ModRM)=dst; PutbackRMWord(ModRM,src); CLKM(5,3); } OP_EPILOGUE;
OP( 0x88, i_mov_br8 ) { uint8 src; GetModRM; src = RegByte(ModRM); PutRMByte(ModRM,src); CLK(1); } OP_EPILOGUE;
OP( 0x89, i_mov_wr16 ) { uint16 src; GetModRM; src = RegWord(ModRM); PutRMWord(ModRM,src); CLK(1); } OP_EPILOGUE;
OP( 0x8a, i_mov_r8b ) { uint8 src; GetModRM; src = GetRMByte(ModRM); RegByte(ModRM)=src; CLK(1); } OP_EPILOGUE;
OP( 0x8b, i_mov_r16w ) { uint16 src; GetModRM; src = GetRMWord(ModRM); RegWord(ModRM)=src; CLK(1); } OP_EPILOGUE;
OP( 0x88, i_mov_br8 ) { GetModRM; uint8 src = RegByte(ModRM); PutRMByte(ModRM,src); CLK(1); } OP_EPILOGUE;
OP( 0x89, i_mov_wr16 ) { GetModRM; uint16 src = RegWord(ModRM); PutRMWord(ModRM,src); CLK(1); } OP_EPILOGUE;
OP( 0x8a, i_mov_r8b ) { GetModRM; uint8 src = GetRMByte(ModRM); RegByte(ModRM)=src; CLK(1); } OP_EPILOGUE;
OP( 0x8b, i_mov_r16w ) { GetModRM; uint16 src = GetRMWord(ModRM); RegWord(ModRM)=src; CLK(1); } OP_EPILOGUE;
OP( 0x8c, i_mov_wsreg ) { GetModRM; PutRMWord(ModRM,I.sregs[(ModRM & 0x38) >> 3]); CLK(1); } OP_EPILOGUE;
OP( 0x8d, i_lea ) { uint16 ModRM = FETCH; if(ModRM >= 192) { } else { (void)(*GetEA[ModRM])(); } RegWord(ModRM)=EO; CLK(1); } OP_EPILOGUE;
OP( 0x8e, i_mov_sregw ) { uint16 src; GetModRM; src = GetRMWord(ModRM); CLKM(3,2);
OP( 0x8d, i_lea ) { uint16 ModRM = FETCH; if(ModRM < 192) { (void)(*GetEA[ModRM])(); } RegWord(ModRM)=EO; CLK(1); } OP_EPILOGUE;
OP( 0x8e, i_mov_sregw ) { GetModRM; uint16 src = GetRMWord(ModRM); CLKM(3,2);
switch (ModRM & 0x38) {
case 0x00: I.sregs[DS1] = src; break; /* mov ds1,ew */
case 0x08: I.sregs[PS] = src; break; /* mov cs,ew */
@ -1095,9 +1108,10 @@ static void DoOP(uint8 opcode)
} OP_EPILOGUE;
OP( 0xc1, i_rotshft_wd8 ) {
uint32 src, dst; uint8 c;
GetModRM; src = (unsigned)GetRMWord(ModRM); dst=src;
c=FETCH;
GetModRM;
uint32 src = (unsigned)GetRMWord(ModRM);
uint32 dst = src;
uint8 c = FETCH;
c&=0x1f;
CLKM(5,3);
if (c) switch (ModRM & 0x38) {
@ -1388,7 +1402,6 @@ static void DoOP(uint8 opcode)
/*****************************************************************************/
unsigned v30mz_get_reg(int regnum)
{
switch( regnum )
@ -1425,8 +1438,6 @@ unsigned v30mz_get_reg(int regnum)
return 0;
}
void nec_set_irq_line(int irqline, int state);
void v30mz_set_reg(int regnum, unsigned val)
{
switch( regnum )