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Remove unused dis files

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twinaphex 2020-09-19 17:30:00 +02:00
parent fe51ef2090
commit b489a78a05
8 changed files with 0 additions and 2556 deletions
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256
mednafen/wswan/dis/dis_decode.cpp
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@ -1,256 +0,0 @@
/////////////////////////////////////////////////////////////////////////
// $Id: dis_decode.cc,v 1.32 2006/05/12 17:04:19 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
#include "disasm.h"
#include "dis_tables.h"
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
x86_insn::x86_insn()
{
extend8b = 0;
seg_override = NO_SEG_OVERRIDE;
prefixes = 0;
ilen = 0;
b1 = 0;
modrm = mod = nnn = rm = 0;
sib = scale = index = base = 0;
displacement.displ32 = 0;
}
#define OPCODE(entry) ((BxDisasmOpcodeInfo_t*) entry->OpcodeInfo)
#define OPCODE_TABLE(entry) ((BxDisasmOpcodeTable_t*) entry->OpcodeInfo)
static const unsigned char instruction_has_modrm[512] = {
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
/* ------------------------------- */
/* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
/* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
/* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
/* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
/* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
/* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
/* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0,
/* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
/* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
/* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
/* A0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
/* B0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
/* C0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0,
/* D0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1,
/* E0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
/* F0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1,
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
/* ------------------------------- */
1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0F 00 */
1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 0F 10 */
1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 0F 20 */
0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 0F 30 */
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 40 */
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 50 */
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 60 */
1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 0F 70 */
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0F 80 */
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 90 */
0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* 0F A0 */
1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* 0F B0 */
1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 0F C0 */
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F D0 */
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F E0 */
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* 0F F0 */
/* ------------------------------- */
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
};
unsigned disassembler::disasm(bx_address base, bx_address ip, const uint8 *instr, char *disbuf)
{
x86_insn insn = decode(base, ip, instr, disbuf);
return insn.ilen;
}
x86_insn disassembler::decode(bx_address base, bx_address ip, const uint8 *instr, char *disbuf)
{
x86_insn insn;
const uint8 *instruction_begin = instruction = instr;
resolve_modrm = NULL;
unsigned b3 = 0;
db_eip = ip;
db_base = base; // cs linear base (base for PM & cs<<4 for RM & VM)
disbufptr = disbuf; // start sprintf()'ing into beginning of buffer
for(;;)
{
if(insn.prefixes == 7) // V30MZ only supports 7 prefixes reliably
break;
insn.b1 = fetch_byte();
insn.prefixes++;
switch(insn.b1) {
case 0x26: // ES:
insn.seg_override = ES_REG;
continue;
case 0x2e: // CS:
insn.seg_override = CS_REG;
continue;
case 0x36: // SS:
insn.seg_override = SS_REG;
continue;
case 0x3e: // DS:
insn.seg_override = DS_REG;
continue;
case 0x64: // FS:
insn.seg_override = FS_REG;
continue;
case 0x65: // GS:
insn.seg_override = GS_REG;
continue;
case 0xf0: // lock
continue;
case 0xf2: // repne
continue;
case 0xf3: // rep
continue;
// no more prefixes
default:
break;
}
insn.prefixes--;
break;
}
if (insn.b1 == 0x0f)
{
insn.b1 = 0x100 | fetch_byte();
}
const BxDisasmOpcodeTable_t *opcode_table, *entry;
opcode_table = BxDisasmOpcodes16;
entry = opcode_table + insn.b1;
// will require 3rd byte for 3-byte opcode
if (entry->Attr & _GRP3BTAB) b3 = fetch_byte();
if (instruction_has_modrm[insn.b1])
{
decode_modrm(&insn);
}
int attr = entry->Attr;
while(attr)
{
switch(attr) {
case _GROUPN:
entry = &(OPCODE_TABLE(entry)[insn.nnn]);
break;
case _SPLIT11B:
entry = &(OPCODE_TABLE(entry)[insn.mod != 3]); /* REG/MEM */
break;
case _GRPRM:
entry = &(OPCODE_TABLE(entry)[insn.rm]);
break;
case _GRP3BTAB:
entry = &(OPCODE_TABLE(entry)[b3 >> 4]);
break;
case _GRP3BOP:
entry = &(OPCODE_TABLE(entry)[b3 & 15]);
break;
default:
printf("Internal disassembler error - unknown attribute !\n");
return x86_insn();
}
/* get additional attributes from group table */
attr = entry->Attr;
}
#define BRANCH_NOT_TAKEN 0x2E
#define BRANCH_TAKEN 0x3E
unsigned branch_hint = 0;
// print prefixes
for(unsigned i=0;i<insn.prefixes;i++)
{
uint8 prefix_byte = *(instr+i);
if (prefix_byte == 0xF3 || prefix_byte == 0xF2 || prefix_byte == 0xF0)
{
const BxDisasmOpcodeTable_t *prefix = &(opcode_table[prefix_byte]);
dis_sprintf("%s ", OPCODE(prefix)->IntelOpcode);
}
// branch hint for jcc instructions
if ((insn.b1 >= 0x070 && insn.b1 <= 0x07F) ||
(insn.b1 >= 0x180 && insn.b1 <= 0x18F))
{
if (prefix_byte == BRANCH_NOT_TAKEN || prefix_byte == BRANCH_TAKEN)
branch_hint = prefix_byte;
}
}
const BxDisasmOpcodeInfo_t *opcode = OPCODE(entry);
// fix nop opcode
if (insn.b1 == 0x90) {
opcode = &Ia_nop;
}
// print instruction disassembly
if (intel_mode)
print_disassembly_intel(&insn, opcode);
else
print_disassembly_att (&insn, opcode);
if (branch_hint == BRANCH_NOT_TAKEN)
{
dis_sprintf(", not taken");
}
else if (branch_hint == BRANCH_TAKEN)
{
dis_sprintf(", taken");
}
insn.ilen = (unsigned)(instruction - instruction_begin);
return insn;
}
void disassembler::dis_sprintf(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
vsprintf(disbufptr, fmt, ap);
va_end(ap);
disbufptr += strlen(disbufptr);
}
void disassembler::dis_putc(char symbol)
{
*disbufptr++ = symbol;
*disbufptr = 0;
}

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mednafen/wswan/dis/dis_groups.cpp
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/////////////////////////////////////////////////////////////////////////
// $Id: dis_groups.cc,v 1.33 2006/08/13 09:40:07 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
#include "disasm.h"
#include <stdio.h>
/*
#if BX_DEBUGGER
#include "../bx_debug/debug.h"
#endif
*/
void disassembler::Apw(const x86_insn *insn)
{
uint16 imm16 = fetch_word();
uint16 cs_selector = fetch_word();
dis_sprintf("%04x:%04x", (unsigned) cs_selector, (unsigned) imm16);
}
void disassembler::Apd(const x86_insn *insn)
{
uint32 imm32 = fetch_dword();
uint16 cs_selector = fetch_word();
dis_sprintf("%04x:%08x", (unsigned) cs_selector, (unsigned) imm32);
}
// 8-bit general purpose registers
void disassembler::AL(const x86_insn *insn) { dis_sprintf("%s", general_8bit_regname[rAX_REG]); }
void disassembler::CL(const x86_insn *insn) { dis_sprintf("%s", general_8bit_regname[rCX_REG]); }
// 16-bit general purpose registers
void disassembler::AX(const x86_insn *insn) {
dis_sprintf("%s", general_16bit_regname[rAX_REG]);
}
void disassembler::DX(const x86_insn *insn) {
dis_sprintf("%s", general_16bit_regname[rDX_REG]);
}
// segment registers
void disassembler::CS(const x86_insn *insn) { dis_sprintf("%s", segment_name[CS_REG]); }
void disassembler::DS(const x86_insn *insn) { dis_sprintf("%s", segment_name[DS_REG]); }
void disassembler::ES(const x86_insn *insn) { dis_sprintf("%s", segment_name[ES_REG]); }
void disassembler::SS(const x86_insn *insn) { dis_sprintf("%s", segment_name[SS_REG]); }
void disassembler::Sw(const x86_insn *insn) { dis_sprintf("%s", segment_name[insn->nnn]); }
// test registers
void disassembler::Td(const x86_insn *insn)
{
if (intel_mode)
dis_sprintf ("tr%d", insn->nnn);
else
dis_sprintf("%%tr%d", insn->nnn);
}
// control register
void disassembler::Cd(const x86_insn *insn)
{
if (intel_mode)
dis_sprintf ("cr%d", insn->nnn);
else
dis_sprintf("%%cr%d", insn->nnn);
}
void disassembler::Cq(const x86_insn *insn) { Cd(insn); }
// debug register
void disassembler::Dd(const x86_insn *insn)
{
if (intel_mode)
dis_sprintf ("db%d", insn->nnn);
else
dis_sprintf("%%db%d", insn->nnn);
}
void disassembler::Dq(const x86_insn *insn) { Dd(insn); }
// 8-bit general purpose register
void disassembler::R8(const x86_insn *insn)
{
unsigned reg = (insn->b1 & 7);
dis_sprintf("%s", general_8bit_regname[reg]);
}
// 16-bit general purpose register
void disassembler::RX(const x86_insn *insn)
{
dis_sprintf("%s", general_16bit_regname[(insn->b1 & 7)]);
}
// general purpose register or memory operand
void disassembler::Eb(const x86_insn *insn)
{
if (insn->mod == 3) {
dis_sprintf("%s", general_8bit_regname[insn->rm]);
}
else
(this->*resolve_modrm)(insn, B_SIZE);
}
void disassembler::Ew(const x86_insn *insn)
{
if (insn->mod == 3)
dis_sprintf("%s", general_16bit_regname[insn->rm]);
else
(this->*resolve_modrm)(insn, W_SIZE);
}
// general purpose register
void disassembler::Gb(const x86_insn *insn)
{
dis_sprintf("%s", general_8bit_regname[insn->nnn]);
}
void disassembler::Gw(const x86_insn *insn)
{
dis_sprintf("%s", general_16bit_regname[insn->nnn]);
}
// immediate
void disassembler::I1(const x86_insn *insn)
{
if (! intel_mode) dis_putc('$');
dis_putc ('1');
}
void disassembler::Ib(const x86_insn *insn)
{
if (! intel_mode) dis_putc('$');
dis_sprintf("0x%02x", (unsigned) fetch_byte());
}
void disassembler::Iw(const x86_insn *insn)
{
if (! intel_mode) dis_putc('$');
dis_sprintf("0x%04x", (unsigned) fetch_word());
}
void disassembler::IwIb(const x86_insn *insn)
{
uint16 iw = fetch_word();
uint8 ib = fetch_byte();
if (intel_mode) {
dis_sprintf("0x%04x, 0x%02x", iw, ib);
}
else {
dis_sprintf("$0x%02x, $0x%04x", ib, iw);
}
}
// sign extended immediate
void disassembler::sIbw(const x86_insn *insn)
{
if (! intel_mode) dis_putc('$');
uint16 imm16 = (int8) fetch_byte();
dis_sprintf("0x%04x", (unsigned) imm16);
}
// sign extended immediate
void disassembler::sIbd(const x86_insn *insn)
{
if (! intel_mode) dis_putc('$');
uint32 imm32 = (int8) fetch_byte();
dis_sprintf ("0x%08x", (unsigned) imm32);
}
// 16-bit general purpose register
void disassembler::Rw(const x86_insn *insn)
{
dis_sprintf("%s", general_16bit_regname[insn->rm]);
}
// direct memory access
void disassembler::OP_O(const x86_insn *insn, unsigned size)
{
const char *seg;
if (insn->is_seg_override())
seg = segment_name[insn->seg_override];
else
seg = segment_name[DS_REG];
print_datasize(size);
uint16 imm16 = fetch_word();
dis_sprintf("%s:0x%x", seg, (unsigned) imm16);
}
void disassembler::Ob(const x86_insn *insn) { OP_O(insn, B_SIZE); }
void disassembler::Ow(const x86_insn *insn) { OP_O(insn, W_SIZE); }
void disassembler::Od(const x86_insn *insn) { OP_O(insn, D_SIZE); }
void disassembler::Oq(const x86_insn *insn) { OP_O(insn, Q_SIZE); }
// memory operand
void disassembler::OP_M(const x86_insn *insn, unsigned size)
{
if(insn->mod == 3)
dis_sprintf("(bad)");
else
(this->*resolve_modrm)(insn, size);
}
void disassembler::Ma(const x86_insn *insn) { OP_M(insn, X_SIZE); }
void disassembler::Mp(const x86_insn *insn) { OP_M(insn, X_SIZE); }
void disassembler::Ms(const x86_insn *insn) { OP_M(insn, X_SIZE); }
void disassembler::Mx(const x86_insn *insn) { OP_M(insn, X_SIZE); }
void disassembler::Mb(const x86_insn *insn) { OP_M(insn, B_SIZE); }
void disassembler::Mw(const x86_insn *insn) { OP_M(insn, W_SIZE); }
void disassembler::Md(const x86_insn *insn) { OP_M(insn, D_SIZE); }
void disassembler::Mq(const x86_insn *insn) { OP_M(insn, Q_SIZE); }
void disassembler::Mt(const x86_insn *insn) { OP_M(insn, T_SIZE); }
void disassembler::Mdq(const x86_insn *insn) { OP_M(insn, O_SIZE); }
void disassembler::Mps(const x86_insn *insn) { OP_M(insn, O_SIZE); }
void disassembler::Mpd(const x86_insn *insn) { OP_M(insn, O_SIZE); }
// string instructions
void disassembler::OP_X(const x86_insn *insn, unsigned size)
{
const char *rsi, *seg;
rsi = general_16bit_regname[rSI_REG];
if (insn->is_seg_override())
seg = segment_name[insn->seg_override];
else
seg = segment_name[DS_REG];
print_datasize(size);
if (intel_mode)
dis_sprintf("%s:[%s]", seg, rsi);
else
dis_sprintf("%s:(%s)", seg, rsi);
}
void disassembler::Xb(const x86_insn *insn) { OP_X(insn, B_SIZE); }
void disassembler::Xw(const x86_insn *insn) { OP_X(insn, W_SIZE); }
void disassembler::Xd(const x86_insn *insn) { OP_X(insn, D_SIZE); }
void disassembler::Xq(const x86_insn *insn) { OP_X(insn, Q_SIZE); }
void disassembler::OP_Y(const x86_insn *insn, unsigned size)
{
const char *rdi;
rdi = general_16bit_regname[rDI_REG];
print_datasize(size);
if (intel_mode)
dis_sprintf("%s:[%s]", segment_name[ES_REG], rdi);
else
dis_sprintf("%s:(%s)", segment_name[ES_REG], rdi);
}
void disassembler::Yb(const x86_insn *insn) { OP_Y(insn, B_SIZE); }
void disassembler::Yw(const x86_insn *insn) { OP_Y(insn, W_SIZE); }
void disassembler::Yd(const x86_insn *insn) { OP_Y(insn, D_SIZE); }
void disassembler::Yq(const x86_insn *insn) { OP_Y(insn, Q_SIZE); }
#define BX_JUMP_TARGET_NOT_REQ ((bx_address)(-1))
// jump offset
void disassembler::Jb(const x86_insn *insn)
{
int8 imm8 = (int8) fetch_byte();
uint16 imm16 = (int16) imm8;
dis_sprintf(".+0x%04x", (unsigned) imm16);
if (db_base != BX_JUMP_TARGET_NOT_REQ) {
uint16 target = (db_eip + (int16) imm16) & 0xffff;
dis_sprintf(" (0x%08x)", target + db_base);
}
}
void disassembler::Jw(const x86_insn *insn)
{
uint16 imm16 = (int16) fetch_word();
dis_sprintf(".+0x%04x", (unsigned) imm16);
if (db_base != BX_JUMP_TARGET_NOT_REQ) {
uint16 target = (db_eip + (int16) imm16) & 0xffff;
dis_sprintf(" (0x%08x)", target + db_base);
}
}
void disassembler::Jd(const x86_insn *insn)
{
int32 imm32 = (int32) fetch_dword();
dis_sprintf(".+0x%08x", (unsigned) imm32);
if (db_base != BX_JUMP_TARGET_NOT_REQ) {
uint32 target = db_eip + (int32) imm32; target += db_base;
dis_sprintf(" (0x%08x)", target);
}
}

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mednafen/wswan/dis/dis_tables.h
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/////////////////////////////////////////////////////////////////////////
// $Id: dis_tables.h,v 1.29 2006/04/27 15:11:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
#ifndef _BX_DISASM_TABLES_
#define _BX_DISASM_TABLES_
// opcode table attributes
#define _GROUPN 1
#define _SPLIT11B 2
#define _GRPFP 3
#define _GRPSSE 5
#define _GRPRM 6
#define _GRP3BOP 7
#define _GRP3BTAB 8
/* ************************************************************************ */
#define GRPSSE(n) _GRPSSE, BxDisasmGroupSSE_##n
#define GRPN(n) _GROUPN, BxDisasmGroup##n
#define GRPRM(n) _GRPRM, BxDisasmGroupRm##n
#define GRPMOD(n) _SPLIT11B, BxDisasmGroupMod##n
#define GRPFP(n) _GRPFP, BxDisasmFPGroup##n
#define GR3BOP(n) _GRP3BOP, BxDisasm3ByteOp##n
#define GR3BTAB(n) _GRP3BTAB, BxDisasm3ByteTable##n
/* ************************************************************************ */
#define Apw &disassembler::Apw
#define Apd &disassembler::Apd
#define AL &disassembler::AL
#define CL &disassembler::CL
#define AX &disassembler::AX
#define DX &disassembler::DX
#define EAX &disassembler::EAX
#define RAX &disassembler::RAX
#define CS &disassembler::CS
#define DS &disassembler::DS
#define ES &disassembler::ES
#define SS &disassembler::SS
#define FS &disassembler::FS
#define GS &disassembler::GS
#define Sw &disassembler::Sw
#define Td &disassembler::Td
#define Cd &disassembler::Cd
#define Cq &disassembler::Cq
#define Dd &disassembler::Dd
#define Dq &disassembler::Dq
#define R8 &disassembler::R8
#define RX &disassembler::RX
#define Eb &disassembler::Eb
#define Ew &disassembler::Ew
#define Ed &disassembler::Ed
#define Eq &disassembler::Eq
#define Gb &disassembler::Gb
#define Gw &disassembler::Gw
#define Gd &disassembler::Gd
#define Gq &disassembler::Gq
#define I1 &disassembler::I1
#define Ib &disassembler::Ib
#define Iw &disassembler::Iw
#define Id &disassembler::Id
#define Iq &disassembler::Iq
#define IwIb &disassembler::IwIb
#define sIbw &disassembler::sIbw
#define sIbd &disassembler::sIbd
#define sIbq &disassembler::sIbq
#define sIdq &disassembler::sIdq
#define ST0 &disassembler::ST0
#define STi &disassembler::STi
#define Rw &disassembler::Rw
#define Rd &disassembler::Rd
#define Rq &disassembler::Rq
#define Pq &disassembler::Pq
#define Qd &disassembler::Qd
#define Qq &disassembler::Qq
#define Nq &disassembler::Nq
#define Vq &disassembler::Vq
#define Vdq &disassembler::Vdq
#define Vss &disassembler::Vss
#define Vsd &disassembler::Vsd
#define Vps &disassembler::Vps
#define Vpd &disassembler::Vpd
#define Udq &disassembler::Udq
#define Wq &disassembler::Wq
#define Wdq &disassembler::Wdq
#define Wss &disassembler::Wss
#define Wsd &disassembler::Wsd
#define Wps &disassembler::Wps
#define Wpd &disassembler::Wpd
#define Ob &disassembler::Ob
#define Ow &disassembler::Ow
#define Od &disassembler::Od
#define Oq &disassembler::Oq
#define Ma &disassembler::Ma
#define Mp &disassembler::Mp
#define Ms &disassembler::Ms
#define Mx &disassembler::Mx
#define Mb &disassembler::Mb
#define Mw &disassembler::Mw
#define Md &disassembler::Md
#define Mq &disassembler::Mq
#define Mt &disassembler::Mt
#define Mdq &disassembler::Mdq
#define Mps &disassembler::Mps
#define Mpd &disassembler::Mpd
#define Xb &disassembler::Xb
#define Xw &disassembler::Xw
#define Xd &disassembler::Xd
#define Xq &disassembler::Xq
#define Yb &disassembler::Yb
#define Yw &disassembler::Yw
#define Yd &disassembler::Yd
#define Yq &disassembler::Yq
#define Jb &disassembler::Jb
#define Jw &disassembler::Jw
#define Jd &disassembler::Jd
#define XX 0
const struct BxDisasmOpcodeInfo_t
#include "opcodes.inc"
#include "dis_tables.inc"
#undef XX
#endif

667
mednafen/wswan/dis/dis_tables.inc
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@ -1,667 +0,0 @@
/* ************************************************************************ */
/* Opcode GroupN */
static BxDisasmOpcodeTable_t BxDisasmGroupG1EbIb[8] = {
/* 0 */ { 0, &Ia_addb_Eb_Ib },
/* 1 */ { 0, &Ia_orb_Eb_Ib },
/* 2 */ { 0, &Ia_adcb_Eb_Ib },
/* 3 */ { 0, &Ia_sbbb_Eb_Ib },
/* 4 */ { 0, &Ia_andb_Eb_Ib },
/* 5 */ { 0, &Ia_subb_Eb_Ib },
/* 6 */ { 0, &Ia_xorb_Eb_Ib },
/* 7 */ { 0, &Ia_cmpb_Eb_Ib }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG1EwIw[8] = {
/* 0 */ { 0, &Ia_addw_Ew_Iw },
/* 1 */ { 0, &Ia_orw_Ew_Iw },
/* 2 */ { 0, &Ia_adcw_Ew_Iw },
/* 3 */ { 0, &Ia_sbbw_Ew_Iw },
/* 4 */ { 0, &Ia_andw_Ew_Iw },
/* 5 */ { 0, &Ia_subw_Ew_Iw },
/* 6 */ { 0, &Ia_xorw_Ew_Iw },
/* 7 */ { 0, &Ia_cmpw_Ew_Iw }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG1EwIb[8] = {
/* 0 */ { 0, &Ia_addw_Ew_sIb }, // sign-extend byte
/* 1 */ { 0, &Ia_orw_Ew_sIb },
/* 2 */ { 0, &Ia_adcw_Ew_sIb },
/* 3 */ { 0, &Ia_sbbw_Ew_sIb },
/* 4 */ { 0, &Ia_andw_Ew_sIb },
/* 5 */ { 0, &Ia_subw_Ew_sIb },
/* 6 */ { 0, &Ia_xorw_Ew_sIb },
/* 7 */ { 0, &Ia_cmpw_Ew_sIb }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG2Eb[8] = {
/* 0 */ { 0, &Ia_rolb_Eb_Ib },
/* 1 */ { 0, &Ia_rorb_Eb_Ib },
/* 2 */ { 0, &Ia_rclb_Eb_Ib },
/* 3 */ { 0, &Ia_rcrb_Eb_Ib },
/* 4 */ { 0, &Ia_shlb_Eb_Ib },
/* 5 */ { 0, &Ia_shrb_Eb_Ib },
/* 6 */ { 0, &Ia_shlb_Eb_Ib },
/* 7 */ { 0, &Ia_sarb_Eb_Ib }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG2EbI1[8] = {
/* 0 */ { 0, &Ia_rolb_Eb_I1 },
/* 1 */ { 0, &Ia_rorb_Eb_I1 },
/* 2 */ { 0, &Ia_rclb_Eb_I1 },
/* 3 */ { 0, &Ia_rcrb_Eb_I1 },
/* 4 */ { 0, &Ia_shlb_Eb_I1 },
/* 5 */ { 0, &Ia_shrb_Eb_I1 },
/* 6 */ { 0, &Ia_shlb_Eb_I1 },
/* 7 */ { 0, &Ia_sarb_Eb_I1 }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG2EbCL[8] = {
/* 0 */ { 0, &Ia_rolb_Eb_CL },
/* 1 */ { 0, &Ia_rorb_Eb_CL },
/* 2 */ { 0, &Ia_rclb_Eb_CL },
/* 3 */ { 0, &Ia_rcrb_Eb_CL },
/* 4 */ { 0, &Ia_shlb_Eb_CL },
/* 5 */ { 0, &Ia_shrb_Eb_CL },
/* 6 */ { 0, &Ia_shlb_Eb_CL },
/* 7 */ { 0, &Ia_sarb_Eb_CL }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG2Ew[8] = {
/* 0 */ { 0, &Ia_rolw_Ew_Ib },
/* 1 */ { 0, &Ia_rorw_Ew_Ib },
/* 2 */ { 0, &Ia_rclw_Ew_Ib },
/* 3 */ { 0, &Ia_rcrw_Ew_Ib },
/* 4 */ { 0, &Ia_shlw_Ew_Ib },
/* 5 */ { 0, &Ia_shrw_Ew_Ib },
/* 6 */ { 0, &Ia_shlw_Ew_Ib },
/* 7 */ { 0, &Ia_sarw_Ew_Ib }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG2EwI1[8] = {
/* 0 */ { 0, &Ia_rolw_Ew_I1 },
/* 1 */ { 0, &Ia_rorw_Ew_I1 },
/* 2 */ { 0, &Ia_rclw_Ew_I1 },
/* 3 */ { 0, &Ia_rcrw_Ew_I1 },
/* 4 */ { 0, &Ia_shlw_Ew_I1 },
/* 5 */ { 0, &Ia_shrw_Ew_I1 },
/* 6 */ { 0, &Ia_shlw_Ew_I1 },
/* 7 */ { 0, &Ia_sarw_Ew_I1 }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG2EwCL[8] = {
/* 0 */ { 0, &Ia_rolw_Ew_CL },
/* 1 */ { 0, &Ia_rorw_Ew_CL },
/* 2 */ { 0, &Ia_rclw_Ew_CL },
/* 3 */ { 0, &Ia_rcrw_Ew_CL },
/* 4 */ { 0, &Ia_shlw_Ew_CL },
/* 5 */ { 0, &Ia_shrw_Ew_CL },
/* 6 */ { 0, &Ia_shlw_Ew_CL },
/* 7 */ { 0, &Ia_sarw_Ew_CL }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG3Eb[8] = {
/* 0 */ { 0, &Ia_testb_Eb_Ib },
/* 1 */ { 0, &Ia_testb_Eb_Ib },
/* 2 */ { 0, &Ia_notb_Eb },
/* 3 */ { 0, &Ia_negb_Eb },
/* 4 */ { 0, &Ia_mulb_AL_Eb },
/* 5 */ { 0, &Ia_imulb_AL_Eb },
/* 6 */ { 0, &Ia_divb_AL_Eb },
/* 7 */ { 0, &Ia_idivb_AL_Eb }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG3Ew[8] = {
/* 0 */ { 0, &Ia_testw_Ew_Iw },
/* 1 */ { 0, &Ia_testw_Ew_Iw },
/* 2 */ { 0, &Ia_notw_Ew },
/* 3 */ { 0, &Ia_negw_Ew },
/* 4 */ { 0, &Ia_mulw_AX_Ew },
/* 5 */ { 0, &Ia_imulw_AX_Ew },
/* 6 */ { 0, &Ia_divw_AX_Ew },
/* 7 */ { 0, &Ia_idivw_AX_Ew }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG4[8] = {
/* 0 */ { 0, &Ia_incb_Eb },
/* 1 */ { 0, &Ia_decb_Eb },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { 0, &Ia_Invalid },
/* 7 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG5w[8] = {
/* 0 */ { 0, &Ia_incw_Ew },
/* 1 */ { 0, &Ia_decw_Ew },
/* 2 */ { 0, &Ia_call_Ew },
/* 3 */ { 0, &Ia_lcall_Mp },
/* 4 */ { 0, &Ia_jmp_Ew },
/* 5 */ { 0, &Ia_ljmp_Mp },
/* 6 */ { 0, &Ia_pushw_Ew },
/* 7 */ { 0, &Ia_Invalid }
};
/* ************************************************************************ */
/* 16-bit operand size */
static BxDisasmOpcodeTable_t BxDisasmOpcodes16[256*2] = {
// 256 entries for single byte opcodes
/* 00 */ { 0, &Ia_addb_Eb_Gb },
/* 01 */ { 0, &Ia_addw_Ew_Gw },
/* 02 */ { 0, &Ia_addb_Gb_Eb },
/* 03 */ { 0, &Ia_addw_Gw_Ew },
/* 04 */ { 0, &Ia_addb_AL_Ib },
/* 05 */ { 0, &Ia_addw_AX_Iw },
/* 06 */ { 0, &Ia_pushw_ES },
/* 07 */ { 0, &Ia_popw_ES },
/* 08 */ { 0, &Ia_orb_Eb_Gb },
/* 09 */ { 0, &Ia_orw_Ew_Gw },
/* 0A */ { 0, &Ia_orb_Gb_Eb },
/* 0B */ { 0, &Ia_orw_Gw_Ew },
/* 0C */ { 0, &Ia_orb_AL_Ib },
/* 0D */ { 0, &Ia_orw_AX_Iw },
/* 0E */ { 0, &Ia_pushw_CS },
/* 0F */ { 0, &Ia_error }, // 2 byte escape
/* 10 */ { 0, &Ia_adcb_Eb_Gb },
/* 11 */ { 0, &Ia_adcw_Ew_Gw },
/* 12 */ { 0, &Ia_adcb_Gb_Eb },
/* 13 */ { 0, &Ia_adcw_Gw_Ew },
/* 14 */ { 0, &Ia_adcb_AL_Ib },
/* 15 */ { 0, &Ia_adcw_AX_Iw },
/* 16 */ { 0, &Ia_pushw_SS },
/* 17 */ { 0, &Ia_popw_SS },
/* 18 */ { 0, &Ia_sbbb_Eb_Gb },
/* 19 */ { 0, &Ia_sbbw_Ew_Gw },
/* 1A */ { 0, &Ia_sbbb_Gb_Eb },
/* 1B */ { 0, &Ia_sbbw_Gw_Ew },
/* 1C */ { 0, &Ia_sbbb_AL_Ib },
/* 1D */ { 0, &Ia_sbbw_AX_Iw },
/* 1E */ { 0, &Ia_pushw_DS },
/* 1F */ { 0, &Ia_popw_DS },
/* 20 */ { 0, &Ia_andb_Eb_Gb },
/* 21 */ { 0, &Ia_andw_Ew_Gw },
/* 22 */ { 0, &Ia_andb_Gb_Eb },
/* 23 */ { 0, &Ia_andw_Gw_Ew },
/* 24 */ { 0, &Ia_andb_AL_Ib },
/* 25 */ { 0, &Ia_andw_AX_Iw },
/* 26 */ { 0, &Ia_prefix_es }, // ES:
/* 27 */ { 0, &Ia_daa },
/* 28 */ { 0, &Ia_subb_Eb_Gb },
/* 29 */ { 0, &Ia_subw_Ew_Gw },
/* 2A */ { 0, &Ia_subb_Gb_Eb },
/* 2B */ { 0, &Ia_subw_Gw_Ew },
/* 2C */ { 0, &Ia_subb_AL_Ib },
/* 2D */ { 0, &Ia_subw_AX_Iw },
/* 2E */ { 0, &Ia_prefix_cs }, // CS:
/* 2F */ { 0, &Ia_das },
/* 30 */ { 0, &Ia_xorb_Eb_Gb },
/* 31 */ { 0, &Ia_xorw_Ew_Gw },
/* 32 */ { 0, &Ia_xorb_Gb_Eb },
/* 33 */ { 0, &Ia_xorw_Gw_Ew },
/* 34 */ { 0, &Ia_xorb_AL_Ib },
/* 35 */ { 0, &Ia_xorw_AX_Iw },
/* 36 */ { 0, &Ia_prefix_ss }, // SS:
/* 37 */ { 0, &Ia_aaa },
/* 38 */ { 0, &Ia_cmpb_Eb_Gb },
/* 39 */ { 0, &Ia_cmpw_Ew_Gw },
/* 3A */ { 0, &Ia_cmpb_Gb_Eb },
/* 3B */ { 0, &Ia_cmpw_Gw_Ew },
/* 3C */ { 0, &Ia_cmpb_AL_Ib },
/* 3D */ { 0, &Ia_cmpw_AX_Iw },
/* 3E */ { 0, &Ia_prefix_ds }, // DS:
/* 3F */ { 0, &Ia_aas },
/* 40 */ { 0, &Ia_incw_RX },
/* 41 */ { 0, &Ia_incw_RX },
/* 42 */ { 0, &Ia_incw_RX },
/* 43 */ { 0, &Ia_incw_RX },
/* 44 */ { 0, &Ia_incw_RX },
/* 45 */ { 0, &Ia_incw_RX },
/* 46 */ { 0, &Ia_incw_RX },
/* 47 */ { 0, &Ia_incw_RX },
/* 48 */ { 0, &Ia_decw_RX },
/* 49 */ { 0, &Ia_decw_RX },
/* 4A */ { 0, &Ia_decw_RX },
/* 4B */ { 0, &Ia_decw_RX },
/* 4C */ { 0, &Ia_decw_RX },
/* 4D */ { 0, &Ia_decw_RX },
/* 4E */ { 0, &Ia_decw_RX },
/* 4F */ { 0, &Ia_decw_RX },
/* 50 */ { 0, &Ia_pushw_RX },
/* 51 */ { 0, &Ia_pushw_RX },
/* 52 */ { 0, &Ia_pushw_RX },
/* 53 */ { 0, &Ia_pushw_RX },
/* 54 */ { 0, &Ia_pushw_RX },
/* 55 */ { 0, &Ia_pushw_RX },
/* 56 */ { 0, &Ia_pushw_RX },
/* 57 */ { 0, &Ia_pushw_RX },
/* 58 */ { 0, &Ia_popw_RX },
/* 59 */ { 0, &Ia_popw_RX },
/* 5A */ { 0, &Ia_popw_RX },
/* 5B */ { 0, &Ia_popw_RX },
/* 5C */ { 0, &Ia_popw_RX },
/* 5D */ { 0, &Ia_popw_RX },
/* 5E */ { 0, &Ia_popw_RX },
/* 5F */ { 0, &Ia_popw_RX },
/* 60 */ { 0, &Ia_pushaw },
/* 61 */ { 0, &Ia_popaw },
/* 62 */ { 0, &Ia_boundw_Gw_Ma },
/* 63 */ { 0, &Ia_Invalid },
/* 64 */ { 0, &Ia_Invalid }, // FS:
/* 65 */ { 0, &Ia_Invalid },
/* 66 */ { 0, &Ia_Invalid },
/* 67 */ { 0, &Ia_Invalid },
/* 68 */ { 0, &Ia_pushw_Iw },
/* 69 */ { 0, &Ia_imulw_Gw_Ew_Iw },
/* 6A */ { 0, &Ia_pushw_sIb },
/* 6B */ { 0, &Ia_imulw_Gw_Ew_sIb },
/* 6C */ { 0, &Ia_insb_Yb_DX },
/* 6D */ { 0, &Ia_insw_Yw_DX },
/* 6E */ { 0, &Ia_outsb_DX_Xb },
/* 6F */ { 0, &Ia_outsw_DX_Xw },
/* 70 */ { 0, &Ia_jo_Jb },
/* 71 */ { 0, &Ia_jno_Jb },
/* 72 */ { 0, &Ia_jb_Jb },
/* 73 */ { 0, &Ia_jnb_Jb },
/* 74 */ { 0, &Ia_jz_Jb },
/* 75 */ { 0, &Ia_jnz_Jb },
/* 76 */ { 0, &Ia_jbe_Jb },
/* 77 */ { 0, &Ia_jnbe_Jb },
/* 78 */ { 0, &Ia_js_Jb },
/* 79 */ { 0, &Ia_jns_Jb },
/* 7A */ { 0, &Ia_jp_Jb },
/* 7B */ { 0, &Ia_jnp_Jb },
/* 7C */ { 0, &Ia_jl_Jb },
/* 7D */ { 0, &Ia_jnl_Jb },
/* 7E */ { 0, &Ia_jle_Jb },
/* 7F */ { 0, &Ia_jnle_Jb },
/* 80 */ { GRPN(G1EbIb) },
/* 81 */ { GRPN(G1EwIw) },
/* 82 */ { GRPN(G1EbIb) },
/* 83 */ { GRPN(G1EwIb) },
/* 84 */ { 0, &Ia_testb_Eb_Gb },
/* 85 */ { 0, &Ia_testw_Ew_Gw },
/* 86 */ { 0, &Ia_xchgb_Eb_Gb },
/* 87 */ { 0, &Ia_xchgw_Ew_Gw },
/* 88 */ { 0, &Ia_movb_Eb_Gb },
/* 89 */ { 0, &Ia_movw_Ew_Gw },
/* 8A */ { 0, &Ia_movb_Gb_Eb },
/* 8B */ { 0, &Ia_movw_Gw_Ew },
/* 8C */ { 0, &Ia_movw_Ew_Sw },
/* 8D */ { 0, &Ia_leaw_Gw_Mw },
/* 8E */ { 0, &Ia_movw_Sw_Ew },
/* 8F */ { 0, &Ia_popw_Ew },
/* 90 */ { 0, &Ia_nop },
/* 91 */ { 0, &Ia_xchgw_RX_AX },
/* 92 */ { 0, &Ia_xchgw_RX_AX },
/* 93 */ { 0, &Ia_xchgw_RX_AX },
/* 94 */ { 0, &Ia_xchgw_RX_AX },
/* 95 */ { 0, &Ia_xchgw_RX_AX },
/* 96 */ { 0, &Ia_xchgw_RX_AX },
/* 97 */ { 0, &Ia_xchgw_RX_AX },
/* 98 */ { 0, &Ia_cbw },
/* 99 */ { 0, &Ia_cwd },
/* 9A */ { 0, &Ia_lcall_Apw },
/* 9B */ { 0, &Ia_poll },
/* 9C */ { 0, &Ia_pushfw },
/* 9D */ { 0, &Ia_popfw },
/* 9E */ { 0, &Ia_sahf },
/* 9F */ { 0, &Ia_lahf },
/* A0 */ { 0, &Ia_movb_AL_Ob },
/* A1 */ { 0, &Ia_movw_AX_Ow },
/* A2 */ { 0, &Ia_movb_Ob_AL },
/* A3 */ { 0, &Ia_movw_Ow_AX },
/* A4 */ { 0, &Ia_movsb_Yb_Xb },
/* A5 */ { 0, &Ia_movsw_Yw_Xw },
/* A6 */ { 0, &Ia_cmpsb_Yb_Xb },
/* A7 */ { 0, &Ia_cmpsw_Yw_Xw },
/* A8 */ { 0, &Ia_testb_AL_Ib },
/* A9 */ { 0, &Ia_testw_AX_Iw },
/* AA */ { 0, &Ia_stosb_Yb_AL },
/* AB */ { 0, &Ia_stosw_Yw_AX },
/* AC */ { 0, &Ia_lodsb_AL_Xb },
/* AD */ { 0, &Ia_lodsw_AX_Xw },
/* AE */ { 0, &Ia_scasb_Yb_AL },
/* AF */ { 0, &Ia_scasw_Yw_AX },
/* B0 */ { 0, &Ia_movb_R8_Ib },
/* B1 */ { 0, &Ia_movb_R8_Ib },
/* B2 */ { 0, &Ia_movb_R8_Ib },
/* B3 */ { 0, &Ia_movb_R8_Ib },
/* B4 */ { 0, &Ia_movb_R8_Ib },
/* B5 */ { 0, &Ia_movb_R8_Ib },
/* B6 */ { 0, &Ia_movb_R8_Ib },
/* B7 */ { 0, &Ia_movb_R8_Ib },
/* B8 */ { 0, &Ia_movw_RX_Iw },
/* B9 */ { 0, &Ia_movw_RX_Iw },
/* BA */ { 0, &Ia_movw_RX_Iw },
/* BB */ { 0, &Ia_movw_RX_Iw },
/* BC */ { 0, &Ia_movw_RX_Iw },
/* BD */ { 0, &Ia_movw_RX_Iw },
/* BE */ { 0, &Ia_movw_RX_Iw },
/* BF */ { 0, &Ia_movw_RX_Iw },
/* C0 */ { GRPN(G2Eb) },
/* C1 */ { GRPN(G2Ew) },
/* C2 */ { 0, &Ia_ret_Iw },
/* C3 */ { 0, &Ia_ret },
/* C4 */ { 0, &Ia_lesw_Gw_Mp },
/* C5 */ { 0, &Ia_ldsw_Gw_Mp },
/* C6 */ { 0, &Ia_movb_Eb_Ib },
/* C7 */ { 0, &Ia_movw_Ew_Iw },
/* C8 */ { 0, &Ia_enter },
/* C9 */ { 0, &Ia_leave },
/* CA */ { 0, &Ia_lret_Iw },
/* CB */ { 0, &Ia_lret },
/* CC */ { 0, &Ia_int3 },
/* CD */ { 0, &Ia_int_Ib },
/* CE */ { 0, &Ia_into },
/* CF */ { 0, &Ia_iretw },
/* D0 */ { GRPN(G2EbI1) },
/* D1 */ { GRPN(G2EwI1) },
/* D2 */ { GRPN(G2EbCL) },
/* D3 */ { GRPN(G2EwCL) },
/* D4 */ { 0, &Ia_aam },
/* D5 */ { 0, &Ia_aad },
/* D6 */ { 0, &Ia_salc },
/* D7 */ { 0, &Ia_xlat },
/* D8 */ { 0, &Ia_fpo1 },
/* D9 */ { 0, &Ia_fpo1 },
/* DA */ { 0, &Ia_fpo1 },
/* DB */ { 0, &Ia_fpo1 },
/* DC */ { 0, &Ia_fpo1 },
/* DD */ { 0, &Ia_fpo1 },
/* DE */ { 0, &Ia_fpo1 },
/* DF */ { 0, &Ia_fpo1 },
/* E0 */ { 0, &Ia_loopne_Jb },
/* E1 */ { 0, &Ia_loope_Jb },
/* E2 */ { 0, &Ia_loop_Jb },
/* E3 */ { 0, &Ia_jcxz_Jb },
/* E4 */ { 0, &Ia_inb_AL_Ib },
/* E5 */ { 0, &Ia_inw_AX_Ib },
/* E6 */ { 0, &Ia_outb_Ib_AL },
/* E7 */ { 0, &Ia_outw_Ib_AX },
/* E8 */ { 0, &Ia_call_Jw },
/* E9 */ { 0, &Ia_jmp_Jw },
/* EA */ { 0, &Ia_ljmp_Apw },
/* EB */ { 0, &Ia_jmp_Jb },
/* EC */ { 0, &Ia_inb_AL_DX },
/* ED */ { 0, &Ia_inw_AX_DX },
/* EE */ { 0, &Ia_outb_DX_AL },
/* EF */ { 0, &Ia_outw_DX_AX },
/* F0 */ { 0, &Ia_prefix_lock }, // LOCK:
/* F1 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_prefix_repne }, // REPNE:
/* F3 */ { 0, &Ia_prefix_rep }, // REP:
/* F4 */ { 0, &Ia_hlt },
/* F5 */ { 0, &Ia_cmc },
/* F6 */ { GRPN(G3Eb) },
/* F7 */ { GRPN(G3Ew) },
/* F8 */ { 0, &Ia_clc },
/* F9 */ { 0, &Ia_stc },
/* FA */ { 0, &Ia_cli },
/* FB */ { 0, &Ia_sti },
/* FC */ { 0, &Ia_cld },
/* FD */ { 0, &Ia_std },
/* FE */ { GRPN(G4) },
/* FF */ { GRPN(G5w) },
// 256 entries for two byte opcodes
/* 0F 00 */ { 0, &Ia_Invalid },
/* 0F 01 */ { 0, &Ia_Invalid },
/* 0F 02 */ { 0, &Ia_Invalid },
/* 0F 03 */ { 0, &Ia_Invalid },
/* 0F 04 */ { 0, &Ia_Invalid },
/* 0F 05 */ { 0, &Ia_Invalid },
/* 0F 06 */ { 0, &Ia_Invalid },
/* 0F 07 */ { 0, &Ia_Invalid },
/* 0F 08 */ { 0, &Ia_Invalid },
/* 0F 09 */ { 0, &Ia_Invalid },
/* 0F 0A */ { 0, &Ia_Invalid },
/* 0F 0B */ { 0, &Ia_Invalid },
/* 0F 0C */ { 0, &Ia_Invalid },
/* 0F 0D */ { 0, &Ia_Invalid },
/* 0F 0E */ { 0, &Ia_Invalid },
/* 0F 0F */ { 0, &Ia_Invalid },
/* 0F 10 */ { 0, &Ia_Invalid },
/* 0F 11 */ { 0, &Ia_Invalid },
/* 0F 12 */ { 0, &Ia_Invalid },
/* 0F 13 */ { 0, &Ia_Invalid },
/* 0F 14 */ { 0, &Ia_Invalid },
/* 0F 15 */ { 0, &Ia_Invalid },
/* 0F 16 */ { 0, &Ia_Invalid },
/* 0F 17 */ { 0, &Ia_Invalid },
/* 0F 18 */ { 0, &Ia_Invalid },
/* 0F 19 */ { 0, &Ia_Invalid },
/* 0F 1A */ { 0, &Ia_Invalid },
/* 0F 1B */ { 0, &Ia_Invalid },
/* 0F 1C */ { 0, &Ia_Invalid },
/* 0F 1D */ { 0, &Ia_Invalid },
/* 0F 1E */ { 0, &Ia_Invalid },
/* 0F 1F */ { 0, &Ia_Invalid },
/* 0F 20 */ { 0, &Ia_Invalid },
/* 0F 21 */ { 0, &Ia_Invalid },
/* 0F 22 */ { 0, &Ia_Invalid },
/* 0F 23 */ { 0, &Ia_Invalid },
/* 0F 24 */ { 0, &Ia_Invalid },
/* 0F 25 */ { 0, &Ia_Invalid },
/* 0F 26 */ { 0, &Ia_Invalid },
/* 0F 27 */ { 0, &Ia_Invalid },
/* 0F 28 */ { 0, &Ia_Invalid },
/* 0F 29 */ { 0, &Ia_Invalid },
/* 0F 2A */ { 0, &Ia_Invalid },
/* 0F 2B */ { 0, &Ia_Invalid },
/* 0F 2C */ { 0, &Ia_Invalid },
/* 0F 2D */ { 0, &Ia_Invalid },
/* 0F 2E */ { 0, &Ia_Invalid },
/* 0F 2F */ { 0, &Ia_Invalid },
/* 0F 30 */ { 0, &Ia_Invalid },
/* 0F 31 */ { 0, &Ia_Invalid },
/* 0F 32 */ { 0, &Ia_Invalid },
/* 0F 33 */ { 0, &Ia_Invalid },
/* 0F 34 */ { 0, &Ia_Invalid },
/* 0F 35 */ { 0, &Ia_Invalid },
/* 0F 36 */ { 0, &Ia_Invalid },
/* 0F 37 */ { 0, &Ia_Invalid },
/* 0F 38 */ { 0, &Ia_Invalid },
/* 0F 39 */ { 0, &Ia_Invalid },
/* 0F 3A */ { 0, &Ia_Invalid },
/* 0F 3B */ { 0, &Ia_Invalid },
/* 0F 3C */ { 0, &Ia_Invalid },
/* 0F 3D */ { 0, &Ia_Invalid },
/* 0F 3E */ { 0, &Ia_Invalid },
/* 0F 3F */ { 0, &Ia_Invalid },
/* 0F 40 */ { 0, &Ia_Invalid },
/* 0F 41 */ { 0, &Ia_Invalid },
/* 0F 42 */ { 0, &Ia_Invalid },
/* 0F 43 */ { 0, &Ia_Invalid },
/* 0F 44 */ { 0, &Ia_Invalid },
/* 0F 45 */ { 0, &Ia_Invalid },
/* 0F 46 */ { 0, &Ia_Invalid },
/* 0F 47 */ { 0, &Ia_Invalid },
/* 0F 48 */ { 0, &Ia_Invalid },
/* 0F 49 */ { 0, &Ia_Invalid },
/* 0F 4A */ { 0, &Ia_Invalid },
/* 0F 4B */ { 0, &Ia_Invalid },
/* 0F 4C */ { 0, &Ia_Invalid },
/* 0F 4D */ { 0, &Ia_Invalid },
/* 0F 4E */ { 0, &Ia_Invalid },
/* 0F 4F */ { 0, &Ia_Invalid },
/* 0F 50 */ { 0, &Ia_Invalid },
/* 0F 51 */ { 0, &Ia_Invalid },
/* 0F 52 */ { 0, &Ia_Invalid },
/* 0F 53 */ { 0, &Ia_Invalid },
/* 0F 54 */ { 0, &Ia_Invalid },
/* 0F 55 */ { 0, &Ia_Invalid },
/* 0F 56 */ { 0, &Ia_Invalid },
/* 0F 57 */ { 0, &Ia_Invalid },
/* 0F 58 */ { 0, &Ia_Invalid },
/* 0F 59 */ { 0, &Ia_Invalid },
/* 0F 5A */ { 0, &Ia_Invalid },
/* 0F 5B */ { 0, &Ia_Invalid },
/* 0F 5C */ { 0, &Ia_Invalid },
/* 0F 5D */ { 0, &Ia_Invalid },
/* 0F 5E */ { 0, &Ia_Invalid },
/* 0F 5F */ { 0, &Ia_Invalid },
/* 0F 60 */ { 0, &Ia_Invalid },
/* 0F 61 */ { 0, &Ia_Invalid },
/* 0F 62 */ { 0, &Ia_Invalid },
/* 0F 63 */ { 0, &Ia_Invalid },
/* 0F 64 */ { 0, &Ia_Invalid },
/* 0F 65 */ { 0, &Ia_Invalid },
/* 0F 66 */ { 0, &Ia_Invalid },
/* 0F 67 */ { 0, &Ia_Invalid },
/* 0F 68 */ { 0, &Ia_Invalid },
/* 0F 69 */ { 0, &Ia_Invalid },
/* 0F 6A */ { 0, &Ia_Invalid },
/* 0F 6B */ { 0, &Ia_Invalid },
/* 0F 6C */ { 0, &Ia_Invalid },
/* 0F 6D */ { 0, &Ia_Invalid },
/* 0F 6E */ { 0, &Ia_Invalid },
/* 0F 6F */ { 0, &Ia_Invalid },
/* 0F 70 */ { 0, &Ia_Invalid },
/* 0F 71 */ { 0, &Ia_Invalid },
/* 0F 72 */ { 0, &Ia_Invalid },
/* 0F 73 */ { 0, &Ia_Invalid },
/* 0F 74 */ { 0, &Ia_Invalid },
/* 0F 75 */ { 0, &Ia_Invalid },
/* 0F 76 */ { 0, &Ia_Invalid },
/* 0F 77 */ { 0, &Ia_Invalid },
/* 0F 78 */ { 0, &Ia_Invalid },
/* 0F 79 */ { 0, &Ia_Invalid },
/* 0F 7A */ { 0, &Ia_Invalid },
/* 0F 7B */ { 0, &Ia_Invalid },
/* 0F 7C */ { 0, &Ia_Invalid },
/* 0F 7D */ { 0, &Ia_Invalid },
/* 0F 7E */ { 0, &Ia_Invalid },
/* 0F 7F */ { 0, &Ia_Invalid },
/* 0F 80 */ { 0, &Ia_Invalid },
/* 0F 81 */ { 0, &Ia_Invalid },
/* 0F 82 */ { 0, &Ia_Invalid },
/* 0F 83 */ { 0, &Ia_Invalid },
/* 0F 84 */ { 0, &Ia_Invalid },
/* 0F 85 */ { 0, &Ia_Invalid },
/* 0F 86 */ { 0, &Ia_Invalid },
/* 0F 87 */ { 0, &Ia_Invalid },
/* 0F 88 */ { 0, &Ia_Invalid },
/* 0F 89 */ { 0, &Ia_Invalid },
/* 0F 8A */ { 0, &Ia_Invalid },
/* 0F 8B */ { 0, &Ia_Invalid },
/* 0F 8C */ { 0, &Ia_Invalid },
/* 0F 8D */ { 0, &Ia_Invalid },
/* 0F 8E */ { 0, &Ia_Invalid },
/* 0F 8F */ { 0, &Ia_Invalid },
/* 0F 90 */ { 0, &Ia_Invalid },
/* 0F 91 */ { 0, &Ia_Invalid },
/* 0F 92 */ { 0, &Ia_Invalid },
/* 0F 93 */ { 0, &Ia_Invalid },
/* 0F 94 */ { 0, &Ia_Invalid },
/* 0F 95 */ { 0, &Ia_Invalid },
/* 0F 96 */ { 0, &Ia_Invalid },
/* 0F 97 */ { 0, &Ia_Invalid },
/* 0F 98 */ { 0, &Ia_Invalid },
/* 0F 99 */ { 0, &Ia_Invalid },
/* 0F 9A */ { 0, &Ia_Invalid },
/* 0F 9B */ { 0, &Ia_Invalid },
/* 0F 9C */ { 0, &Ia_Invalid },
/* 0F 9D */ { 0, &Ia_Invalid },
/* 0F 9E */ { 0, &Ia_Invalid },
/* 0F 9F */ { 0, &Ia_Invalid },
/* 0F A0 */ { 0, &Ia_Invalid },
/* 0F A1 */ { 0, &Ia_Invalid },
/* 0F A2 */ { 0, &Ia_Invalid },
/* 0F A3 */ { 0, &Ia_Invalid },
/* 0F A4 */ { 0, &Ia_Invalid },
/* 0F A5 */ { 0, &Ia_Invalid },
/* 0F A6 */ { 0, &Ia_Invalid },
/* 0F A7 */ { 0, &Ia_Invalid },
/* 0F A8 */ { 0, &Ia_Invalid },
/* 0F A9 */ { 0, &Ia_Invalid },
/* 0F AA */ { 0, &Ia_Invalid },
/* 0F AB */ { 0, &Ia_Invalid },
/* 0F AC */ { 0, &Ia_Invalid },
/* 0F AD */ { 0, &Ia_Invalid },
/* 0F AE */ { 0, &Ia_Invalid },
/* 0F AF */ { 0, &Ia_Invalid },
/* 0F B0 */ { 0, &Ia_Invalid },
/* 0F B1 */ { 0, &Ia_Invalid },
/* 0F B2 */ { 0, &Ia_Invalid },
/* 0F B3 */ { 0, &Ia_Invalid },
/* 0F B4 */ { 0, &Ia_Invalid },
/* 0F B5 */ { 0, &Ia_Invalid },
/* 0F B6 */ { 0, &Ia_Invalid },
/* 0F B7 */ { 0, &Ia_Invalid },
/* 0F B8 */ { 0, &Ia_Invalid },
/* 0F B9 */ { 0, &Ia_Invalid },
/* 0F BA */ { 0, &Ia_Invalid },
/* 0F BB */ { 0, &Ia_Invalid },
/* 0F BC */ { 0, &Ia_Invalid },
/* 0F BD */ { 0, &Ia_Invalid },
/* 0F BE */ { 0, &Ia_Invalid },
/* 0F BF */ { 0, &Ia_Invalid },
/* 0F C0 */ { 0, &Ia_Invalid },
/* 0F C0 */ { 0, &Ia_Invalid },
/* 0F C2 */ { 0, &Ia_Invalid },
/* 0F C3 */ { 0, &Ia_Invalid },
/* 0F C4 */ { 0, &Ia_Invalid },
/* 0F C5 */ { 0, &Ia_Invalid },
/* 0F C6 */ { 0, &Ia_Invalid },
/* 0F C7 */ { 0, &Ia_Invalid },
/* 0F C8 */ { 0, &Ia_Invalid },
/* 0F C9 */ { 0, &Ia_Invalid },
/* 0F CA */ { 0, &Ia_Invalid },
/* 0F CB */ { 0, &Ia_Invalid },
/* 0F CC */ { 0, &Ia_Invalid },
/* 0F CD */ { 0, &Ia_Invalid },
/* 0F CE */ { 0, &Ia_Invalid },
/* 0F CF */ { 0, &Ia_Invalid },
/* 0F D0 */ { 0, &Ia_Invalid },
/* 0F D1 */ { 0, &Ia_Invalid },
/* 0F D2 */ { 0, &Ia_Invalid },
/* 0F D3 */ { 0, &Ia_Invalid },
/* 0F D4 */ { 0, &Ia_Invalid },
/* 0F D5 */ { 0, &Ia_Invalid },
/* 0F D6 */ { 0, &Ia_Invalid },
/* 0F D7 */ { 0, &Ia_Invalid },
/* 0F D8 */ { 0, &Ia_Invalid },
/* 0F D9 */ { 0, &Ia_Invalid },
/* 0F DA */ { 0, &Ia_Invalid },
/* 0F DB */ { 0, &Ia_Invalid },
/* 0F DC */ { 0, &Ia_Invalid },
/* 0F DD */ { 0, &Ia_Invalid },
/* 0F DE */ { 0, &Ia_Invalid },
/* 0F DF */ { 0, &Ia_Invalid },
/* 0F E0 */ { 0, &Ia_Invalid },
/* 0F E1 */ { 0, &Ia_Invalid },
/* 0F E2 */ { 0, &Ia_Invalid },
/* 0F E3 */ { 0, &Ia_Invalid },
/* 0F E4 */ { 0, &Ia_Invalid },
/* 0F E5 */ { 0, &Ia_Invalid },
/* 0F E6 */ { 0, &Ia_Invalid },
/* 0F E7 */ { 0, &Ia_Invalid },
/* 0F E8 */ { 0, &Ia_Invalid },
/* 0F E9 */ { 0, &Ia_Invalid },
/* 0F EA */ { 0, &Ia_Invalid },
/* 0F EB */ { 0, &Ia_Invalid },
/* 0F EC */ { 0, &Ia_Invalid },
/* 0F ED */ { 0, &Ia_Invalid },
/* 0F EE */ { 0, &Ia_Invalid },
/* 0F EF */ { 0, &Ia_Invalid },
/* 0F F0 */ { 0, &Ia_Invalid },
/* 0F F1 */ { 0, &Ia_Invalid },
/* 0F F2 */ { 0, &Ia_Invalid },
/* 0F F3 */ { 0, &Ia_Invalid },
/* 0F F4 */ { 0, &Ia_Invalid },
/* 0F F5 */ { 0, &Ia_Invalid },
/* 0F F6 */ { 0, &Ia_Invalid },
/* 0F F7 */ { 0, &Ia_Invalid },
/* 0F F8 */ { 0, &Ia_Invalid },
/* 0F F9 */ { 0, &Ia_Invalid },
/* 0F FA */ { 0, &Ia_Invalid },
/* 0F FB */ { 0, &Ia_Invalid },
/* 0F FC */ { 0, &Ia_Invalid },
/* 0F FD */ { 0, &Ia_Invalid },
/* 0F FE */ { 0, &Ia_Invalid },
/* 0F FF */ { 0, &Ia_Invalid }
};

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@ -1,380 +0,0 @@
#ifndef _BX_DISASM_H_
#define _BX_DISASM_H_
#include "../../types.h"
typedef uint16 bx_address;
#define BX_DECODE_MODRM(modrm_byte, mod, opcode, rm) { \
mod = (modrm_byte >> 6) & 0x03; \
opcode = (modrm_byte >> 3) & 0x07; \
rm = modrm_byte & 0x07; \
}
#define BX_DECODE_SIB(sib_byte, scale, index, base) { \
scale = sib_byte >> 6; \
index = (sib_byte >> 3) & 0x07; \
base = sib_byte & 0x07; \
}
/* general purpose bit register */
enum {
rAX_REG,
rCX_REG,
rDX_REG,
rBX_REG,
rSP_REG,
rBP_REG,
rSI_REG,
rDI_REG
};
/* segment register */
enum {
ES_REG,
CS_REG,
SS_REG,
DS_REG,
FS_REG,
GS_REG,
INVALID_SEG1,
INVALID_SEG2
};
class disassembler;
struct x86_insn;
typedef void (disassembler::*BxDisasmPtr_t)(const x86_insn *insn);
typedef void (disassembler::*BxDisasmResolveModrmPtr_t)(const x86_insn *insn, unsigned attr);
struct BxDisasmOpcodeInfo_t
{
const char *IntelOpcode;
const char *AttOpcode;
BxDisasmPtr_t Operand1;
BxDisasmPtr_t Operand2;
BxDisasmPtr_t Operand3;
};
struct BxDisasmOpcodeTable_t
{
uint32 Attr;
const void *OpcodeInfo;
};
// segment override not used
#define NO_SEG_OVERRIDE 0xFF
// datasize attributes
#define X_SIZE 0x0000
#define B_SIZE 0x0100
#define W_SIZE 0x0200
#define D_SIZE 0x0300
#define Q_SIZE 0x0400
#define Z_SIZE 0x0500
#define V_SIZE 0x0600
#define O_SIZE 0x0700
#define T_SIZE 0x0800
#define P_SIZE 0x0900
// branch hint attribute
#define BRANCH_HINT 0x1000
struct x86_insn
{
public:
x86_insn();
bool is_seg_override() const {
return (seg_override != NO_SEG_OVERRIDE);
}
public:
uint8 extend8b;
uint8 seg_override;
unsigned b1, prefixes;
unsigned ilen;
uint8 modrm, mod, nnn, rm;
uint8 sib, scale, index, base;
union {
uint16 displ16;
uint32 displ32;
} displacement;
};
class disassembler {
public:
disassembler() { set_syntax_intel(); }
unsigned disasm(bx_address base, bx_address ip, const uint8 *instr, char *disbuf);
unsigned disasm16(bx_address base, bx_address ip, const uint8 *instr, char *disbuf)
{ return disasm(base, ip, instr, disbuf); }
x86_insn decode(bx_address base, bx_address ip, const uint8 *instr, char *disbuf);
x86_insn decode16(bx_address base, bx_address ip, const uint8 *instr, char *disbuf)
{ return decode(base, ip, instr, disbuf); }
void set_syntax_intel();
void set_syntax_att ();
void toggle_syntax_mode();
private:
bool intel_mode;
const char **general_16bit_regname;
const char **general_8bit_regname;
const char **segment_name;
const char **index16;
const char *sreg_mod01or10_rm32[8];
const char *sreg_mod00_base32[8];
const char *sreg_mod01or10_base32[8];
const char *sreg_mod00_rm16[8];
const char *sreg_mod01or10_rm16[8];
private:
bx_address db_eip, db_base;
const uint8 *instruction; // for fetching of next byte of instruction
char *disbufptr;
BxDisasmResolveModrmPtr_t resolve_modrm;
uint8 fetch_byte() {
db_eip++;
return(*instruction++);
};
uint8 peek_byte() {
return(*instruction);
};
uint16 fetch_word() {
uint8 b0 = * (uint8 *) instruction++;
uint8 b1 = * (uint8 *) instruction++;
uint16 ret16 = (b1<<8) | b0;
db_eip += 2;
return(ret16);
};
uint32 fetch_dword() {
uint8 b0 = * (uint8 *) instruction++;
uint8 b1 = * (uint8 *) instruction++;
uint8 b2 = * (uint8 *) instruction++;
uint8 b3 = * (uint8 *) instruction++;
uint32 ret32 = (b3<<24) | (b2<<16) | (b1<<8) | b0;
db_eip += 4;
return(ret32);
};
void dis_putc(char symbol);
void dis_sprintf(const char *fmt, ...);
void decode_modrm(x86_insn *insn);
void resolve16_mod0 (const x86_insn *insn, unsigned mode);
void resolve16_mod1or2(const x86_insn *insn, unsigned mode);
void initialize_modrm_segregs();
void print_datasize (unsigned mode);
void print_memory_access16(int datasize,
const char *seg, const char *index, uint16 disp);
void print_memory_access (int datasize,
const char *seg, const char *base, const char *index, int scale, uint32 disp);
void print_disassembly_intel(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry);
void print_disassembly_att (const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry);
public:
/*
* Codes for Addressing Method:
* ---------------------------
* A - Direct address. The instruction has no ModR/M byte; the address
* of the operand is encoded in the instruction; and no base register,
* index register, or scaling factor can be applied.
* C - The reg field of the ModR/M byte selects a control register.
* D - The reg field of the ModR/M byte selects a debug register.
* E - A ModR/M byte follows the opcode and specifies the operand. The
* operand is either a general-purpose register or a memory address.
* If it is a memory address, the address is computed from a segment
* register and any of the following values: a base register, an
* index register, a scaling factor, a displacement.
* F - Flags Register.
* G - The reg field of the ModR/M byte selects a general register.
* I - Immediate data. The operand value is encoded in subsequent bytes of
* the instruction.
* J - The instruction contains a relative offset to be added to the
* instruction pointer register.
* M - The ModR/M byte may refer only to memory.
* N - The R/M field of the ModR/M byte selects a packed-quadword MMX
technology register.
* O - The instruction has no ModR/M byte; the offset of the operand is
* coded as a word or double word (depending on address size attribute)
* in the instruction. No base register, index register, or scaling
* factor can be applied.
* P - The reg field of the ModR/M byte selects a packed quadword MMX
* technology register.
* Q - A ModR/M byte follows the opcode and specifies the operand. The
* operand is either an MMX technology register or a memory address.
* If it is a memory address, the address is computed from a segment
* register and any of the following values: a base register, an
* index register, a scaling factor, and a displacement.
* R - The mod field of the ModR/M byte may refer only to a general register.
* S - The reg field of the ModR/M byte selects a segment register.
* U - The R/M field of the ModR/M byte selects a 128-bit XMM register.
* T - The reg field of the ModR/M byte selects a test register.
* V - The reg field of the ModR/M byte selects a 128-bit XMM register.
* W - A ModR/M byte follows the opcode and specifies the operand. The
* operand is either a 128-bit XMM register or a memory address. If
* it is a memory address, the address is computed from a segment
* register and any of the following values: a base register, an
* index register, a scaling factor, and a displacement.
* X - Memory addressed by the DS:rSI register pair.
* Y - Memory addressed by the ES:rDI register pair.
*/
/*
* Codes for Operand Type:
* ----------------------
* a - Two one-word operands in memory or two double-word operands in
* memory, depending on operand-size attribute (used only by the BOUND
* instruction).
* b - Byte, regardless of operand-size attribute.
* d - Doubleword, regardless of operand-size attribute.
* dq - Double-quadword, regardless of operand-size attribute.
* p - 32-bit or 48-bit pointer, depending on operand-size attribute.
* pd - 128-bit packed double-precision floating-point data.
* pi - Quadword MMX technology register (packed integer)
* ps - 128-bit packed single-precision floating-point data.
* q - Quadword, regardless of operand-size attribute.
* s - 6-byte or 10-byte pseudo-descriptor.
* si - Doubleword integer register (scalar integer)
* ss - Scalar element of a 128-bit packed single-precision floating data.
* sd - Scalar element of a 128-bit packed double-precision floating data.
* v - Word, doubleword or quadword, depending on operand-size attribute.
* w - Word, regardless of operand-size attr.
*/
// far call/jmp
void Apw(const x86_insn *insn);
void Apd(const x86_insn *insn);
// 8-bit general purpose registers
void AL(const x86_insn *insn);
void CL(const x86_insn *insn);
// 16-bit general purpose registers
void AX(const x86_insn *insn);
void DX(const x86_insn *insn);
// segment registers
void CS(const x86_insn *insn);
void DS(const x86_insn *insn);
void ES(const x86_insn *insn);
void SS(const x86_insn *insn);
// segment registers
void Sw(const x86_insn *insn);
// test registers
void Td(const x86_insn *insn);
// control register
void Cd(const x86_insn *insn);
void Cq(const x86_insn *insn);
// debug register
void Dd(const x86_insn *insn);
void Dq(const x86_insn *insn);
// 8-bit general purpose register
void R8(const x86_insn *insn);
// 16-bit general purpose register
void RX(const x86_insn *insn);
// general purpose register or memory operand
void Eb(const x86_insn *insn);
void Ew(const x86_insn *insn);
void Ed(const x86_insn *insn);
void Eq(const x86_insn *insn);
// general purpose register
void Gb(const x86_insn *insn);
void Gw(const x86_insn *insn);
void Gd(const x86_insn *insn);
void Gq(const x86_insn *insn);
// immediate
void I1(const x86_insn *insn);
void Ib(const x86_insn *insn);
void Iw(const x86_insn *insn);
void Id(const x86_insn *insn);
void Iq(const x86_insn *insn);
// two immediates Iw/Ib
void IwIb(const x86_insn *insn);
// sign extended immediate
void sIbw(const x86_insn *insn);
void sIbd(const x86_insn *insn);
void sIbq(const x86_insn *insn);
void sIdq(const x86_insn *insn);
// general purpose register
void Rw(const x86_insn *insn);
void Rd(const x86_insn *insn);
void Rq(const x86_insn *insn);
// direct memory access
void OP_O(const x86_insn *insn, unsigned size);
void Ob(const x86_insn *insn);
void Ow(const x86_insn *insn);
void Od(const x86_insn *insn);
void Oq(const x86_insn *insn);
// memory operand
void OP_M(const x86_insn *insn, unsigned size);
void Ma(const x86_insn *insn);
void Mp(const x86_insn *insn);
void Ms(const x86_insn *insn);
void Mx(const x86_insn *insn);
void Mb(const x86_insn *insn);
void Mw(const x86_insn *insn);
void Md(const x86_insn *insn);
void Mq(const x86_insn *insn);
void Mt(const x86_insn *insn);
void Mdq(const x86_insn *insn);
void Mps(const x86_insn *insn);
void Mpd(const x86_insn *insn);
// string instructions
void OP_X(const x86_insn *insn, unsigned size);
void Xb(const x86_insn *insn);
void Xw(const x86_insn *insn);
void Xd(const x86_insn *insn);
void Xq(const x86_insn *insn);
// string instructions
void OP_Y(const x86_insn *insn, unsigned size);
void Yb(const x86_insn *insn);
void Yw(const x86_insn *insn);
void Yd(const x86_insn *insn);
void Yq(const x86_insn *insn);
// jump offset
void Jb(const x86_insn *insn);
void Jw(const x86_insn *insn);
void Jd(const x86_insn *insn);
};
#endif

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Ia_hlt = { "hlt", "hlt", XX, XX, XX },
Ia_poll = { "poll", "poll", XX, XX, XX },
Ia_fpo1 = { "fop1", "fop1", Eb, XX, XX },
Ia_aaa = { "aaa", "aaa", XX, XX, XX },
Ia_aad = { "aad", "aad", Ib, XX, XX },
Ia_aam = { "aam", "aam", Ib, XX, XX },
Ia_aas = { "aas", "aas", XX, XX, XX },
Ia_adcb_AL_Ib = { "adc", "adcb", AL, Ib, XX },
Ia_adcb_Eb_Gb = { "adc", "adcb", Eb, Gb, XX },
Ia_adcb_Eb_Ib = { "adc", "adcb", Eb, Ib, XX },
Ia_adcb_Gb_Eb = { "adc", "adcb", Gb, Eb, XX },
Ia_adcw_AX_Iw = { "adc", "adcw", AX, Iw, XX },
Ia_adcw_Ew_Gw = { "adc", "adcw", Ew, Gw, XX },
Ia_adcw_Ew_Iw = { "adc", "adcw", Ew, Iw, XX },
Ia_adcw_Ew_sIb = { "adc", "adcw", Ew, sIbw, XX },
Ia_adcw_Gw_Ew = { "adc", "adcw", Gw, Ew, XX },
Ia_addb_AL_Ib = { "add", "addb", AL, Ib, XX },
Ia_addb_Eb_Gb = { "add", "addb", Eb, Gb, XX },
Ia_addb_Eb_Ib = { "add", "addb", Eb, Ib, XX },
Ia_addb_Gb_Eb = { "add", "addb", Gb, Eb, XX },
Ia_addw_AX_Iw = { "add", "addw", AX, Iw, XX },
Ia_addw_Ew_Gw = { "add", "addw", Ew, Gw, XX },
Ia_addw_Ew_Iw = { "add", "addw", Ew, Iw, XX },
Ia_addw_Ew_sIb = { "add", "addw", Ew, sIbw, XX },
Ia_addw_Gw_Ew = { "add", "addw", Gw, Ew, XX },
Ia_andb_AL_Ib = { "and", "andb", AL, Ib, XX },
Ia_andb_Eb_Gb = { "and", "andb", Eb, Gb, XX },
Ia_andb_Eb_Ib = { "and", "andb", Eb, Ib, XX },
Ia_andb_Gb_Eb = { "and", "andb", Gb, Eb, XX },
Ia_andw_AX_Iw = { "and", "andw", AX, Iw, XX },
Ia_andw_Ew_Gw = { "and", "andw", Ew, Gw, XX },
Ia_andw_Ew_Iw = { "and", "andw", Ew, Iw, XX },
Ia_andw_Ew_sIb = { "and", "andw", Ew, sIbw, XX },
Ia_andw_Gw_Ew = { "and", "andw", Gw, Ew, XX },
Ia_boundw_Gw_Ma = { "bound", "boundw", Gw, Ma, XX },
Ia_call_Ew = { "call", "call", Ew, XX, XX },
Ia_call_Jd = { "call", "call", Jd, XX, XX },
Ia_call_Jw = { "call", "call", Jw, XX, XX },
Ia_cbw = { "cbw", "cbtw", XX, XX, XX },
Ia_clc = { "clc", "clc", XX, XX, XX },
Ia_cld = { "cld", "cld", XX, XX, XX },
Ia_cli = { "cli", "cli", XX, XX, XX },
Ia_cmc = { "cmc", "cmc", XX, XX, XX },
Ia_cmpb_AL_Ib = { "cmp", "cmpb", AL, Ib, XX },
Ia_cmpb_Eb_Gb = { "cmp", "cmpb", Eb, Gb, XX },
Ia_cmpb_Eb_Ib = { "cmp", "cmpb", Eb, Ib, XX },
Ia_cmpb_Gb_Eb = { "cmp", "cmpb", Gb, Eb, XX },
Ia_cmpsb_Yb_Xb = { "cmpsb", "cmpsb", Yb, Xb, XX },
Ia_cmpsl_Yd_Xd = { "cmpsd", "cmpsl", Yd, Xd, XX },
Ia_cmpsw_Yw_Xw = { "cmpsw", "cmpsw", Yw, Xw, XX },
Ia_cmpw_AX_Iw = { "cmp", "cmpw", AX, Iw, XX },
Ia_cmpw_Ew_Gw = { "cmp", "cmpw", Ew, Gw, XX },
Ia_cmpw_Ew_Iw = { "cmp", "cmpw", Ew, Iw, XX },
Ia_cmpw_Ew_sIb = { "cmp", "cmpw", Ew, sIbw, XX },
Ia_cmpw_Gw_Ew = { "cmp", "cmpw", Gw, Ew, XX },
Ia_cwd = { "cwd", "cwtd", XX, XX, XX },
Ia_daa = { "daa", "daa", XX, XX, XX },
Ia_das = { "das", "das", XX, XX, XX },
Ia_decb_Eb = { "dec", "decb", Eb, XX, XX },
Ia_decw_Ew = { "dec", "decw", Ew, XX, XX },
Ia_decw_RX = { "dec", "decw", RX, XX, XX },
Ia_divb_AL_Eb = { "div", "divb", AL, Eb, XX },
Ia_divw_AX_Ew = { "div", "divw", AX, Ew, XX },
Ia_enter = { "enter", "enter", IwIb, XX, XX },
Ia_error = { "(error)", "(error)", XX, XX, XX },
Ia_idivb_AL_Eb = { "idiv", "idivb", AL, Eb, XX },
Ia_idivw_AX_Ew = { "idiv", "idivw", AX, Ew, XX },
Ia_imulb_AL_Eb = { "imul", "imulb", AL, Eb, XX },
Ia_imulw_AX_Ew = { "imul", "imulw", AX, Ew, XX },
Ia_imulw_Gw_Ew = { "imul", "imulw", Gw, Ew, XX },
Ia_imulw_Gw_Ew_Iw = { "imul", "imulw", Gw, Ew, Iw },
Ia_imulw_Gw_Ew_sIb = { "imul", "imulw", Gw, Ew, sIbw },
Ia_inb_AL_DX = { "in", "inb", AL, DX, XX },
Ia_inb_AL_Ib = { "in", "inb", AL, Ib, XX },
Ia_incb_Eb = { "inc", "incb", Eb, XX, XX },
Ia_incw_Ew = { "inc", "incw", Ew, XX, XX },
Ia_incw_RX = { "inc", "incw", RX, XX, XX },
Ia_insb_Yb_DX = { "insb", "insb", Yb, DX, XX },
Ia_insw_Yw_DX = { "insw", "insw", Yw, DX, XX },
Ia_int_Ib = { "int", "int", Ib, XX, XX },
Ia_int1 = { "int1", "int1", XX, XX, XX },
Ia_int3 = { "int3", "int3", XX, XX, XX },
Ia_into = { "into", "into", XX, XX, XX },
Ia_Invalid = { "(invalid)", "(invalid)", XX, XX, XX },
Ia_invd = { "invd", "invd", XX, XX, XX },
Ia_invlpg = { "invlpg", "invlpg", Mx, XX, XX },
Ia_inw_AX_DX = { "in", "inw", AX, DX, XX },
Ia_inw_AX_Ib = { "in", "inw", AX, Ib, XX },
Ia_iretl = { "iretd", "iretd", XX, XX, XX },
Ia_iretq = { "iretq", "iretq", XX, XX, XX },
Ia_iretw = { "iret", "iretw", XX, XX, XX },
Ia_jb_Jb = { "jb", "jb", Jb, XX, XX },
Ia_jb_Jd = { "jb", "jb", Jd, XX, XX },
Ia_jb_Jw = { "jb", "jb", Jw, XX, XX },
Ia_jbe_Jb = { "jbe", "jbe", Jb, XX, XX },
Ia_jbe_Jd = { "jbe", "jbe", Jd, XX, XX },
Ia_jbe_Jw = { "jbe", "jbe", Jw, XX, XX },
Ia_jcxz_Jb = { "jcxz", "jcxz", Jb, XX, XX },
Ia_jecxz_Jb = { "jecxz", "jecxz", Jb, XX, XX },
Ia_jl_Jb = { "jl", "jl", Jb, XX, XX },
Ia_jl_Jd = { "jl", "jl", Jd, XX, XX },
Ia_jl_Jw = { "jl", "jl", Jw, XX, XX },
Ia_jle_Jb = { "jle", "jle", Jb, XX, XX },
Ia_jle_Jd = { "jle", "jle", Jd, XX, XX },
Ia_jle_Jw = { "jle", "jle", Jw, XX, XX },
Ia_jmp_Ew = { "jmp", "jmp", Ew, XX, XX },
Ia_jmp_Jb = { "jmp", "jmp", Jb, XX, XX },
Ia_jmp_Jd = { "jmp", "jmp", Jd, XX, XX },
Ia_jmp_Jw = { "jmp", "jmp", Jw, XX, XX },
Ia_jnb_Jb = { "jnb", "jnb", Jb, XX, XX },
Ia_jnb_Jd = { "jnb", "jnb", Jd, XX, XX },
Ia_jnb_Jw = { "jnb", "jnb", Jw, XX, XX },
Ia_jnbe_Jb = { "jnbe", "jnbe", Jb, XX, XX },
Ia_jnbe_Jd = { "jnbe", "jnbe", Jd, XX, XX },
Ia_jnbe_Jw = { "jnbe", "jnbe", Jw, XX, XX },
Ia_jnl_Jb = { "jnl", "jnl", Jb, XX, XX },
Ia_jnl_Jd = { "jnl", "jnl", Jd, XX, XX },
Ia_jnl_Jw = { "jnl", "jnl", Jw, XX, XX },
Ia_jnle_Jb = { "jnle", "jnle", Jb, XX, XX },
Ia_jnle_Jd = { "jnle", "jnle", Jd, XX, XX },
Ia_jnle_Jw = { "jnle", "jnle", Jw, XX, XX },
Ia_jno_Jb = { "jno", "jno", Jb, XX, XX },
Ia_jno_Jd = { "jno", "jno", Jd, XX, XX },
Ia_jno_Jw = { "jno", "jno", Jw, XX, XX },
Ia_jnp_Jb = { "jnp", "jnp", Jb, XX, XX },
Ia_jnp_Jd = { "jnp", "jnp", Jd, XX, XX },
Ia_jnp_Jw = { "jnp", "jnp", Jw, XX, XX },
Ia_jns_Jb = { "jns", "jns", Jb, XX, XX },
Ia_jns_Jd = { "jns", "jns", Jd, XX, XX },
Ia_jns_Jw = { "jns", "jns", Jw, XX, XX },
Ia_jnz_Jb = { "jnz", "jnz", Jb, XX, XX },
Ia_jnz_Jd = { "jnz", "jnz", Jd, XX, XX },
Ia_jnz_Jw = { "jnz", "jnz", Jw, XX, XX },
Ia_jo_Jb = { "jo", "jo", Jb, XX, XX },
Ia_jo_Jd = { "jo", "jo", Jd, XX, XX },
Ia_jo_Jw = { "jo", "jo", Jw, XX, XX },
Ia_jp_Jb = { "jp", "jp", Jb, XX, XX },
Ia_jp_Jd = { "jp", "jp", Jd, XX, XX },
Ia_jp_Jw = { "jp", "jp", Jw, XX, XX },
Ia_jrcxz_Jb = { "jrcxz", "jrcxz", Jb, XX, XX },
Ia_js_Jb = { "js", "js", Jb, XX, XX },
Ia_js_Jd = { "js", "js", Jd, XX, XX },
Ia_js_Jw = { "js", "js", Jw, XX, XX },
Ia_jz_Jb = { "jz", "jz", Jb, XX, XX },
Ia_jz_Jd = { "jz", "jz", Jd, XX, XX },
Ia_jz_Jw = { "jz", "jz", Jw, XX, XX },
Ia_lahf = { "lahf", "lahf", XX, XX, XX },
Ia_larw_Gw_Ew = { "lar", "larw", Gw, Ew, XX },
Ia_lcall_Apd = { "call far", "lcall", Apd, XX, XX },
Ia_lcall_Apw = { "call far", "lcall", Apw, XX, XX },
Ia_lcall_Mp = { "call far", "lcall", Mp, XX, XX },
Ia_ldsw_Gw_Mp = { "lds", "ldsw", Gw, Mp, XX },
Ia_leave = { "leave", "leave", XX, XX, XX },
Ia_leaw_Gw_Mw = { "lea", "leaw", Gw, Mw, XX },
Ia_lesw_Gw_Mp = { "les", "lesw", Gw, Mp, XX },
Ia_lfence = { "lfence", "lfence", XX, XX, XX },
Ia_lfsw_Gw_Mp = { "lfs", "lfsw", Gw, Mp, XX },
Ia_lgdt = { "lgdt", "lgdt", Ms, XX, XX },
Ia_lgsw_Gw_Mp = { "lgs", "lgsw", Gw, Mp, XX },
Ia_lidt = { "lidt", "lidt", Ms, XX, XX },
Ia_ljmp_Apd = { "jmp far", "ljmp", Apd, XX, XX },
Ia_ljmp_Apw = { "jmp far", "ljmp", Apw, XX, XX },
Ia_ljmp_Mp = { "jmp far", "ljmp", Mp, XX, XX },
Ia_lldt = { "lldt", "lldt", Ew, XX, XX },
Ia_lmsw_Ew = { "lmsw", "lmsw", Ew, XX, XX },
Ia_lodsb_AL_Xb = { "lodsb", "lodsb", AL, Xb, XX },
Ia_lodsw_AX_Xw = { "lodsw", "lodsw", AX, Xw, XX },
Ia_loop_Jb = { "loop", "loop", Jb, XX, XX },
Ia_loope_Jb = { "loope", "loope", Jb, XX, XX },
Ia_loopne_Jb = { "loopne", "loopne", Jb, XX, XX },
Ia_lret = { "retf", "lret", XX, XX, XX },
Ia_lret_Iw = { "retf", "lret", Iw, XX, XX },
Ia_lslw_Gw_Ew = { "lsl", "lslw", Gw, Ew, XX },
Ia_lssw_Gw_Mp = { "lss", "lssw", Gw, Mp, XX },
Ia_ltr = { "ltr", "ltr", Ew, XX, XX },
Ia_movb_AL_Ob = { "mov", "movb", AL, Ob, XX },
Ia_movb_Eb_Gb = { "mov", "movb", Eb, Gb, XX },
Ia_movb_Eb_Ib = { "mov", "movb", Eb, Ib, XX },
Ia_movb_Gb_Eb = { "mov", "movb", Gb, Eb, XX },
Ia_movb_Ob_AL = { "mov", "movb", Ob, AL, XX },
Ia_movb_R8_Ib = { "mov", "movb", R8, Ib, XX },
Ia_movsb_Yb_Xb = { "movsb", "movsb", Yb, Xb, XX },
Ia_movsbw_Gw_Eb = { "movsx", "movsbw", Gw, Eb, XX },
Ia_movsl_Yd_Xd = { "movsd", "movsl", Yd, Xd, XX },
Ia_movsq_Yq_Xq = { "movsq", "movsq", Yq, Xq, XX },
Ia_movsw_Yw_Xw = { "movsw", "movsw", Yw, Xw, XX },
Ia_movw_AX_Ow = { "mov", "movw", AX, Ow, XX },
Ia_movw_Ew_Gw = { "mov", "movw", Ew, Gw, XX },
Ia_movw_Ew_Iw = { "mov", "movw", Ew, Iw, XX },
Ia_movw_Ew_Sw = { "mov", "movw", Ew, Sw, XX },
Ia_movw_Gw_Ew = { "mov", "movw", Gw, Ew, XX },
Ia_movw_Ow_AX = { "mov", "movw", Ow, AX, XX },
Ia_movw_RX_Iw = { "mov", "movw", RX, Iw, XX },
Ia_movw_Sw_Ew = { "mov", "movw", Sw, Ew, XX },
Ia_movzbw_Gw_Eb = { "movzx", "movzbw", Gw, Eb, XX },
Ia_mulb_AL_Eb = { "mul", "mulb", AL, Eb, XX },
Ia_multibyte_nop = { "multibyte nop", "multibyte nop", XX, XX, XX },
Ia_mulw_AX_Ew = { "mul", "mulw", AX, Ew, XX },
Ia_mwait = { "mwait", "mwait", XX, XX, XX },
Ia_negb_Eb = { "neg", "negb", Eb, XX, XX },
Ia_negw_Ew = { "neg", "negw", Ew, XX, XX },
Ia_nop = { "nop", "nop", XX, XX, XX },
Ia_notb_Eb = { "not", "notb", Eb, XX, XX },
Ia_notw_Ew = { "not", "notw", Ew, XX, XX },
Ia_orb_AL_Ib = { "or", "orb", AL, Ib, XX },
Ia_orb_Eb_Gb = { "or", "orb", Eb, Gb, XX },
Ia_orb_Eb_Ib = { "or", "orb", Eb, Ib, XX },
Ia_orb_Gb_Eb = { "or", "orb", Gb, Eb, XX },
Ia_orw_AX_Iw = { "or", "orw", AX, Iw, XX },
Ia_orw_Ew_Gw = { "or", "orw", Ew, Gw, XX },
Ia_orw_Ew_Iw = { "or", "orw", Ew, Iw, XX },
Ia_orw_Ew_sIb = { "or", "orw", Ew, sIbw, XX },
Ia_orw_Gw_Ew = { "or", "orw", Gw, Ew, XX },
Ia_outb_DX_AL = { "out", "outb", DX, AL, XX },
Ia_outb_Ib_AL = { "out", "outb", Ib, AL, XX },
Ia_outsb_DX_Xb = { "outsb", "outsb", DX, Xb, XX },
Ia_outsl_DX_Xd = { "outsd", "outsl", DX, Xd, XX },
Ia_outsw_DX_Xw = { "outsw", "outsw", DX, Xw, XX },
Ia_outw_DX_AX = { "out", "outw", DX, AX, XX },
Ia_outw_Ib_AX = { "out", "outw", Ib, AX, XX },
Ia_popaw = { "popa", "popa", XX, XX, XX },
Ia_popfw = { "popf", "popf", XX, XX, XX },
Ia_popw_DS = { "pop", "popw", DS, XX, XX },
Ia_popw_ES = { "pop", "popw", ES, XX, XX },
Ia_popw_Ew = { "pop", "popw", Ew, XX, XX },
Ia_popw_RX = { "pop", "popw", RX, XX, XX },
Ia_popw_SS = { "pop", "popw", SS, XX, XX },
Ia_prefix_cs = { "cs", "cs", XX, XX, XX },
Ia_prefix_ds = { "ds", "ds", XX, XX, XX },
Ia_prefix_es = { "es", "es", XX, XX, XX },
Ia_prefix_lock = { "lock", "lock", XX, XX, XX },
Ia_prefix_rep = { "rep", "rep", XX, XX, XX },
Ia_prefix_repne = { "repne", "repne", XX, XX, XX },
Ia_prefix_ss = { "ss", "ss", XX, XX, XX },
Ia_pushal = { "pushad", "pushal", XX, XX, XX },
Ia_pushaw = { "pusha", "pusha", XX, XX, XX },
Ia_pushfl = { "pushfd", "pushfl", XX, XX, XX },
Ia_pushfq = { "pushfq", "pushfq", XX, XX, XX },
Ia_pushfw = { "pushf", "pushf", XX, XX, XX },
Ia_pushl_CS = { "push", "pushl", CS, XX, XX },
Ia_pushl_DS = { "push", "pushl", DS, XX, XX },
Ia_pushl_ES = { "push", "pushl", ES, XX, XX },
Ia_pushl_sIb = { "push", "pushl", sIbd, XX, XX },
Ia_pushl_SS = { "push", "pushl", SS, XX, XX },
Ia_pushw_CS = { "push", "pushw", CS, XX, XX },
Ia_pushw_DS = { "push", "pushw", DS, XX, XX },
Ia_pushw_ES = { "push", "pushw", ES, XX, XX },
Ia_pushw_Ew = { "push", "pushw", Ew, XX, XX },
Ia_pushw_Iw = { "push", "pushw", Iw, XX, XX },
Ia_pushw_RX = { "push", "pushw", RX, XX, XX },
Ia_pushw_sIb = { "push", "pushw", sIbw, XX, XX },
Ia_pushw_SS = { "push", "pushw", SS, XX, XX },
Ia_rclb_Eb_CL = { "rcl", "rclb", Eb, CL, XX },
Ia_rclb_Eb_I1 = { "rcl", "rclb", Eb, I1, XX },
Ia_rclb_Eb_Ib = { "rcl", "rclb", Eb, Ib, XX },
Ia_rclw_Ew_CL = { "rcl", "rclw", Ew, CL, XX },
Ia_rclw_Ew_I1 = { "rcl", "rclw", Ew, I1, XX },
Ia_rclw_Ew_Ib = { "rcl", "rclw", Ew, Ib, XX },
Ia_rcrb_Eb_CL = { "rcr", "rcrb", Eb, CL, XX },
Ia_rcrb_Eb_I1 = { "rcr", "rcrb", Eb, I1, XX },
Ia_rcrb_Eb_Ib = { "rcr", "rcrb", Eb, Ib, XX },
Ia_rcrw_Ew_CL = { "rcr", "rcrw", Ew, CL, XX },
Ia_rcrw_Ew_I1 = { "rcr", "rcrw", Ew, I1, XX },
Ia_rcrw_Ew_Ib = { "rcr", "rcrw", Ew, Ib, XX },
Ia_rdmsr = { "rdmsr", "rdmsr", XX, XX, XX },
Ia_rdpmc = { "rdpmc", "rdpmc", XX, XX, XX },
Ia_rdtsc = { "rdtsc", "rdtsc", XX, XX, XX },
Ia_rdtscp = { "rdtscp", "rdtscp", XX, XX, XX },
Ia_ret = { "ret", "ret", XX, XX, XX },
Ia_ret_Iw = { "ret", "ret", Iw, XX, XX },
Ia_rolb_Eb_CL = { "rol", "rolb", Eb, CL, XX },
Ia_rolb_Eb_I1 = { "rol", "rolb", Eb, I1, XX },
Ia_rolb_Eb_Ib = { "rol", "rolb", Eb, Ib, XX },
Ia_rolw_Ew_CL = { "rol", "rolw", Ew, CL, XX },
Ia_rolw_Ew_I1 = { "rol", "rolw", Ew, I1, XX },
Ia_rolw_Ew_Ib = { "rol", "rolw", Ew, Ib, XX },
Ia_rorb_Eb_CL = { "ror", "rorb", Eb, CL, XX },
Ia_rorb_Eb_I1 = { "ror", "rorb", Eb, I1, XX },
Ia_rorb_Eb_Ib = { "ror", "rorb", Eb, Ib, XX },
Ia_rorw_Ew_CL = { "ror", "rorw", Ew, CL, XX },
Ia_rorw_Ew_I1 = { "ror", "rorw", Ew, I1, XX },
Ia_rorw_Ew_Ib = { "ror", "rorw", Ew, Ib, XX },
Ia_rsm = { "rsm", "rsm", XX, XX, XX },
Ia_sahf = { "sahf", "sahf", XX, XX, XX },
Ia_salc = { "salc", "salc", XX, XX, XX },
Ia_sarb_Eb_CL = { "sar", "sarb", Eb, CL, XX },
Ia_sarb_Eb_I1 = { "sar", "sarb", Eb, I1, XX },
Ia_sarb_Eb_Ib = { "sar", "sarb", Eb, Ib, XX },
Ia_sarw_Ew_CL = { "sar", "sarw", Ew, CL, XX },
Ia_sarw_Ew_I1 = { "sar", "sarw", Ew, I1, XX },
Ia_sarw_Ew_Ib = { "sar", "sarw", Ew, Ib, XX },
Ia_sbbb_AL_Ib = { "sbb", "sbbb", AL, Ib, XX },
Ia_sbbb_Eb_Gb = { "sbb", "sbbb", Eb, Gb, XX },
Ia_sbbb_Eb_Ib = { "sbb", "sbbb", Eb, Ib, XX },
Ia_sbbb_Gb_Eb = { "sbb", "sbbb", Gb, Eb, XX },
Ia_sbbw_AX_Iw = { "sbb", "sbbw", AX, Iw, XX },
Ia_sbbw_Ew_Gw = { "sbb", "sbbw", Ew, Gw, XX },
Ia_sbbw_Ew_Iw = { "sbb", "sbbw", Ew, Iw, XX },
Ia_sbbw_Ew_sIb = { "sbb", "sbbw", Ew, sIbw, XX },
Ia_sbbw_Gw_Ew = { "sbb", "sbbw", Gw, Ew, XX },
Ia_scasb_Yb_AL = { "scasb", "scasb", Yb, AL, XX },
Ia_scasw_Yw_AX = { "scasw", "scasw", Yw, AX, XX },
Ia_setb_Eb = { "setb", "setb", Eb, XX, XX },
Ia_setbe_Eb = { "setbe", "setbe", Eb, XX, XX },
Ia_setl_Eb = { "setl", "setl", Eb, XX, XX },
Ia_setle_Eb = { "setle", "setle", Eb, XX, XX },
Ia_setnb_Eb = { "setnb", "setnb", Eb, XX, XX },
Ia_setnbe_Eb = { "setnbe", "setnbe", Eb, XX, XX },
Ia_setnl_Eb = { "setnl", "setnl", Eb, XX, XX },
Ia_setnle_Eb = { "setnle", "setnle", Eb, XX, XX },
Ia_setno_Eb = { "setno", "setno", Eb, XX, XX },
Ia_setnp_Eb = { "setnp", "setnp", Eb, XX, XX },
Ia_setns_Eb = { "setns", "setns", Eb, XX, XX },
Ia_setnz_Eb = { "setnz", "setnz", Eb, XX, XX },
Ia_seto_Eb = { "seto", "seto", Eb, XX, XX },
Ia_setp_Eb = { "setp", "setp", Eb, XX, XX },
Ia_sets_Eb = { "sets", "sets", Eb, XX, XX },
Ia_setz_Eb = { "setz", "setz", Eb, XX, XX },
Ia_shlb_Eb_CL = { "shl", "shlb", Eb, CL, XX },
Ia_shlb_Eb_I1 = { "shl", "shlb", Eb, I1, XX },
Ia_shlb_Eb_Ib = { "shl", "shlb", Eb, Ib, XX },
Ia_shlw_Ew_CL = { "shl", "shlw", Ew, CL, XX },
Ia_shlw_Ew_I1 = { "shl", "shlw", Ew, I1, XX },
Ia_shlw_Ew_Ib = { "shl", "shlw", Ew, Ib, XX },
Ia_shrb_Eb_CL = { "shr", "shrb", Eb, CL, XX },
Ia_shrb_Eb_I1 = { "shr", "shrb", Eb, I1, XX },
Ia_shrb_Eb_Ib = { "shr", "shrb", Eb, Ib, XX },
Ia_shrw_Ew_CL = { "shr", "shrw", Ew, CL, XX },
Ia_shrw_Ew_I1 = { "shr", "shrw", Ew, I1, XX },
Ia_shrw_Ew_Ib = { "shr", "shrw", Ew, Ib, XX },
Ia_sidt = { "sidt", "sidt", Ms, XX, XX },
Ia_sldt = { "sldt", "sldt", Ew, XX, XX },
Ia_stc = { "stc", "stc", XX, XX, XX },
Ia_std = { "std", "std", XX, XX, XX },
Ia_sti = { "sti", "sti", XX, XX, XX },
Ia_stosb_Yb_AL = { "stosb", "stosb", Yb, AL, XX },
Ia_stosw_Yw_AX = { "stosw", "stosw", Yw, AX, XX },
Ia_str = { "str", "str", Ew, XX, XX },
Ia_subb_AL_Ib = { "sub", "subb", AL, Ib, XX },
Ia_subb_Eb_Gb = { "sub", "subb", Eb, Gb, XX },
Ia_subb_Eb_Ib = { "sub", "subb", Eb, Ib, XX },
Ia_subb_Gb_Eb = { "sub", "subb", Gb, Eb, XX },
Ia_subw_AX_Iw = { "sub", "subw", AX, Iw, XX },
Ia_subw_Ew_Gw = { "sub", "subw", Ew, Gw, XX },
Ia_subw_Ew_Iw = { "sub", "subw", Ew, Iw, XX },
Ia_subw_Ew_sIb = { "sub", "subw", Ew, sIbw, XX },
Ia_subw_Gw_Ew = { "sub", "subw", Gw, Ew, XX },
Ia_swapgs = { "swapgs", "swapgs", XX, XX, XX },
Ia_syscall = { "syscall", "syscall", XX, XX, XX },
Ia_sysenter = { "sysenter", "sysenter", XX, XX, XX },
Ia_sysexit = { "sysexit", "sysexit", XX, XX, XX },
Ia_sysret = { "sysret", "sysret", XX, XX, XX },
Ia_testb_AL_Ib = { "test", "testb", AL, Ib, XX },
Ia_testb_Eb_Gb = { "test", "testb", Eb, Gb, XX },
Ia_testb_Eb_Ib = { "test", "testb", Eb, Ib, XX },
Ia_testw_AX_Iw = { "test", "testw", AX, Iw, XX },
Ia_testw_Ew_Gw = { "test", "testw", Ew, Gw, XX },
Ia_testw_Ew_Iw = { "test", "testw", Ew, Iw, XX },
Ia_xaddb_Eb_Gb = { "xadd", "xaddb", Eb, Gb, XX },
Ia_xaddw_Ew_Gw = { "xadd", "xaddw", Ew, Gw, XX },
Ia_xchgb_Eb_Gb = { "xchg", "xchgb", Eb, Gb, XX },
Ia_xchgw_Ew_Gw = { "xchg", "xchgw", Ew, Gw, XX },
Ia_xchgw_RX_AX = { "xchg", "xchgw", RX, AX, XX },
Ia_xlat = { "xlat", "xlat", XX, XX, XX },
Ia_xorb_AL_Ib = { "xor", "xorb", AL, Ib, XX },
Ia_xorb_Eb_Gb = { "xor", "xorb", Eb, Gb, XX },
Ia_xorb_Eb_Ib = { "xor", "xorb", Eb, Ib, XX },
Ia_xorb_Gb_Eb = { "xor", "xorb", Gb, Eb, XX },
Ia_xorw_AX_Iw = { "xor", "xorw", AX, Iw, XX },
Ia_xorw_Ew_Gw = { "xor", "xorw", Ew, Gw, XX },
Ia_xorw_Ew_Iw = { "xor", "xorw", Ew, Iw, XX },
Ia_xorw_Ew_sIb = { "xor", "xorw", Ew, sIbw, XX },
Ia_xorw_Gw_Ew = { "xor", "xorw", Gw, Ew, XX };

226
mednafen/wswan/dis/resolve.cpp
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@ -1,226 +0,0 @@
/////////////////////////////////////////////////////////////////////////
// $Id: resolve.cc,v 1.13 2006/08/11 17:22:43 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
#include "disasm.h"
#include <stdio.h>
void disassembler::decode_modrm(x86_insn *insn)
{
insn->modrm = fetch_byte();
BX_DECODE_MODRM(insn->modrm, insn->mod, insn->nnn, insn->rm);
// MOVs with CRx and DRx always use register ops and ignore the mod field.
if ((insn->b1 & ~3) == 0x120) insn->mod = 3;
if (insn->mod == 3) {
/* mod, reg, reg */
return;
}
/* 16 bit addressing modes. */
switch (insn->mod) {
case 0:
resolve_modrm = &disassembler::resolve16_mod0;
if(insn->rm == 6)
insn->displacement.displ16 = fetch_word();
break;
case 1:
/* reg, 8-bit displacement, sign extend */
resolve_modrm = &disassembler::resolve16_mod1or2;
insn->displacement.displ16 = (int8) fetch_byte();
break;
case 2:
resolve_modrm = &disassembler::resolve16_mod1or2;
insn->displacement.displ16 = fetch_word();
break;
} /* switch (mod) ... */
}
void disassembler::resolve16_mod0(const x86_insn *insn, unsigned mode)
{
const char *seg;
if (insn->is_seg_override())
seg = segment_name[insn->seg_override];
else
seg = sreg_mod00_rm16[insn->rm];
if(insn->rm == 6)
print_memory_access16(mode, seg, NULL, insn->displacement.displ16);
else
print_memory_access16(mode, seg, index16[insn->rm], 0);
}
void disassembler::resolve16_mod1or2(const x86_insn *insn, unsigned mode)
{
const char *seg;
if (insn->is_seg_override())
seg = segment_name[insn->seg_override];
else
seg = sreg_mod01or10_rm16[insn->rm];
print_memory_access16(mode, seg, index16[insn->rm], insn->displacement.displ16);
}
void disassembler::print_datasize(unsigned size)
{
if (!intel_mode) return;
switch(size)
{
case B_SIZE:
dis_sprintf("byte ptr ");
break;
case W_SIZE:
dis_sprintf("word ptr ");
break;
case D_SIZE:
dis_sprintf("dword ptr ");
break;
case Q_SIZE:
dis_sprintf("qword ptr ");
break;
case O_SIZE:
dis_sprintf("dqword ptr ");
break;
case T_SIZE:
dis_sprintf("tbyte ptr ");
break;
case P_SIZE:
break;
case X_SIZE:
break;
};
}
void disassembler::print_memory_access16(int datasize,
const char *seg, const char *index, uint16 disp)
{
print_datasize(datasize);
if (intel_mode)
{
if (index == NULL)
{
dis_sprintf("%s:0x%x", seg, (unsigned) disp);
}
else
{
if (disp != 0)
dis_sprintf("%s:[%s+0x%x]", seg, index, (unsigned) disp);
else
dis_sprintf("%s:[%s]", seg, index);
}
}
else
{
if (index == NULL)
{
dis_sprintf("%s:0x%x", seg, (unsigned) disp);
}
else
{
if (disp != 0)
dis_sprintf("%s:0x%x(%s,1)", seg, (unsigned) disp, index);
else
dis_sprintf("%s:(%s,1)", seg, index);
}
}
}
void disassembler::print_memory_access(int datasize,
const char *seg, const char *base, const char *index, int scale, uint32 disp)
{
print_datasize(datasize);
if (intel_mode)
{
if (base == NULL)
{
if (index == NULL)
{
dis_sprintf("%s:0x%x", seg, (unsigned) disp);
}
else
{
if (scale != 0)
{
if (disp != 0)
dis_sprintf("%s:[%s*%d+0x%x]", seg, index, 1<<scale, (unsigned) disp);
else
dis_sprintf("%s:[%s*%d]", seg, index, 1<<scale);
}
else
{
if (disp != 0)
dis_sprintf("%s:[%s+0x%x]", seg, index, (unsigned) disp);
else
dis_sprintf("%s:[%s]", seg, index);
}
}
}
else
{
if (index == NULL)
{
if (disp != 0)
dis_sprintf("%s:[%s+0x%x]", seg, base, (unsigned) disp);
else
dis_sprintf("%s:[%s]", seg, base);
}
else
{
if (scale != 0)
{
if (disp != 0)
dis_sprintf("%s:[%s+%s*%d+0x%x]", seg, base, index, 1<<scale, (unsigned) disp);
else
dis_sprintf("%s:[%s+%s*%d]", seg, base, index, 1<<scale);
}
else
{
if (disp != 0)
dis_sprintf("%s:[%s+%s+0x%x]", seg, base, index, (unsigned) disp);
else
dis_sprintf("%s:[%s+%s]", seg, base, index);
}
}
}
}
else
{
if (base == NULL)
{
if (index == NULL)
{
dis_sprintf("%s:0x%x", seg, (unsigned) disp);
}
else
{
if (disp != 0)
dis_sprintf("%s:0x%x(,%s,%d)", seg, (unsigned) disp, index, 1<<scale);
else
dis_sprintf("%s:(,%s,%d)", seg, index, 1<<scale);
}
}
else
{
if (index == NULL)
{
if (disp != 0)
dis_sprintf("%s:0x%x(%s)", seg, (unsigned) disp, base);
else
dis_sprintf("%s:(%s)", seg, base);
}
else
{
if (disp != 0)
dis_sprintf("%s:0x%x(%s,%s,%d)", seg, (unsigned) disp, base, index, 1<<scale);
else
dis_sprintf("%s:(%s,%s,%d)", seg, base, index, 1<<scale);
}
}
}
}

187
mednafen/wswan/dis/syntax.cpp
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@ -1,187 +0,0 @@
/////////////////////////////////////////////////////////////////////////
// $Id: syntax.cc,v 1.10 2006/04/27 15:11:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
#include "disasm.h"
#include <stdio.h>
//////////////////
// Intel STYLE
//////////////////
static const char *intel_general_16bit_regname[8] = {
"ax", "cx", "dx", "bx", "sp", "bp", "si", "di"
};
static const char *intel_general_8bit_regname[8] = {
"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
};
static const char *intel_segment_name[8] = {
"es", "cs", "ss", "ds", "fs", "gs", "??", "??"
};
static const char *intel_index16[8] = {
"bx+si",
"bx+di",
"bp+si",
"bp+di",
"si",
"di",
"bp",
"bx"
};
//////////////////
// AT&T STYLE
//////////////////
static const char *att_general_16bit_regname[8] = {
"%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di"
};
static const char *att_general_8bit_regname[8] = {
"%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh"
};
static const char *att_segment_name[8] = {
"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%??", "%??"
};
static const char *att_index16[8] = {
"%bx, %si",
"%bx, %di",
"%bp, %si",
"%bp, %di",
"%si",
"%di",
"%bp",
"%bx"
};
#define NULL_SEGMENT_REGISTER 7
void disassembler::initialize_modrm_segregs()
{
sreg_mod00_rm16[0] = segment_name[DS_REG];
sreg_mod00_rm16[1] = segment_name[DS_REG];
sreg_mod00_rm16[2] = segment_name[SS_REG];
sreg_mod00_rm16[3] = segment_name[SS_REG];
sreg_mod00_rm16[4] = segment_name[DS_REG];
sreg_mod00_rm16[5] = segment_name[DS_REG];
sreg_mod00_rm16[6] = segment_name[DS_REG];
sreg_mod00_rm16[7] = segment_name[DS_REG];
sreg_mod01or10_rm16[0] = segment_name[DS_REG];
sreg_mod01or10_rm16[1] = segment_name[DS_REG];
sreg_mod01or10_rm16[2] = segment_name[SS_REG];
sreg_mod01or10_rm16[3] = segment_name[SS_REG];
sreg_mod01or10_rm16[4] = segment_name[DS_REG];
sreg_mod01or10_rm16[5] = segment_name[DS_REG];
sreg_mod01or10_rm16[6] = segment_name[SS_REG];
sreg_mod01or10_rm16[7] = segment_name[DS_REG];
sreg_mod01or10_rm32[0] = segment_name[DS_REG];
sreg_mod01or10_rm32[1] = segment_name[DS_REG];
sreg_mod01or10_rm32[2] = segment_name[DS_REG];
sreg_mod01or10_rm32[3] = segment_name[DS_REG];
sreg_mod01or10_rm32[4] = segment_name[NULL_SEGMENT_REGISTER];
sreg_mod01or10_rm32[5] = segment_name[SS_REG];
sreg_mod01or10_rm32[6] = segment_name[DS_REG];
sreg_mod01or10_rm32[7] = segment_name[DS_REG];
sreg_mod00_base32[0] = segment_name[DS_REG];
sreg_mod00_base32[1] = segment_name[DS_REG];
sreg_mod00_base32[2] = segment_name[DS_REG];
sreg_mod00_base32[3] = segment_name[DS_REG];
sreg_mod00_base32[4] = segment_name[SS_REG];
sreg_mod00_base32[5] = segment_name[DS_REG];
sreg_mod00_base32[6] = segment_name[DS_REG];
sreg_mod00_base32[7] = segment_name[DS_REG];
sreg_mod01or10_base32[0] = segment_name[DS_REG];
sreg_mod01or10_base32[1] = segment_name[DS_REG];
sreg_mod01or10_base32[2] = segment_name[DS_REG];
sreg_mod01or10_base32[3] = segment_name[DS_REG];
sreg_mod01or10_base32[4] = segment_name[SS_REG];
sreg_mod01or10_base32[5] = segment_name[SS_REG];
sreg_mod01or10_base32[6] = segment_name[DS_REG];
sreg_mod01or10_base32[7] = segment_name[DS_REG];
}
//////////////////
// Intel STYLE
//////////////////
void disassembler::set_syntax_intel()
{
intel_mode = 1;
general_16bit_regname = intel_general_16bit_regname;
general_8bit_regname = intel_general_8bit_regname;
segment_name = intel_segment_name;
index16 = intel_index16;
initialize_modrm_segregs();
}
void disassembler::print_disassembly_intel(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry)
{
// print opcode
dis_sprintf("%s ", entry->IntelOpcode);
if (entry->Operand1) {
(this->*entry->Operand1)(insn);
}
if (entry->Operand2) {
dis_sprintf(", ");
(this->*entry->Operand2)(insn);
}
if (entry->Operand3) {
dis_sprintf(", ");
(this->*entry->Operand3)(insn);
}
}
//////////////////
// AT&T STYLE
//////////////////
void disassembler::set_syntax_att()
{
intel_mode = 0;
general_16bit_regname = att_general_16bit_regname;
general_8bit_regname = att_general_8bit_regname;
segment_name = att_segment_name;
index16 = att_index16;
initialize_modrm_segregs();
}
void disassembler::toggle_syntax_mode()
{
if (intel_mode) set_syntax_att();
else set_syntax_intel();
}
void disassembler::print_disassembly_att(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry)
{
// print opcode
dis_sprintf("%s ", entry->AttOpcode);
if (entry->Operand3) {
(this->*entry->Operand3)(insn);
dis_sprintf(", ");
}
if (entry->Operand2) {
(this->*entry->Operand2)(insn);
dis_sprintf(", ");
}
if (entry->Operand1) {
(this->*entry->Operand1)(insn);
}
}