mirror of
https://github.com/libretro/blastem.git
synced 2026-11-07 10:15:58 -10:00
WizzardSK
e1a4cb6c5b
This repo has been sitting on the July 2022 state of upstream BlastEm. The sync brings in four years of upstream work, most importantly for this repo the DSL generated CPU cores: upstream's Makefile now switches to NEW_CORE automatically on any architecture that has no native code generator, and genesis.h picks up the generated m68k context in that configuration, which is what makes non-x86 builds possible at all. Only .gitlab-ci.yml and Makefile.libretro are kept from this repo, every other file is upstream's.
154 lines
3.2 KiB
C
154 lines
3.2 KiB
C
#ifndef SH7095_H_
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#define SH7095_H_
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#include "sh2.h"
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enum {
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SH_SMR,
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SH_BRR,
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SH_SCR,
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SH_TDR,
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SH_SSR,
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SH_RDR,
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SH_TIER = 0x10,
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SH_FTCSR,
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SH_FRCH,
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SH_FRCL,
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SH_OCRH,
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SH_OCRL,
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SH_TCR,
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SH_TOCR,
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SH_ICRH,
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SH_ICRL,
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SH_IPRB = 0x60,
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SH_VCRA = 0x62,
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SH_VCRB = 0x64,
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SH_VCRC = 0x66,
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SH_VCRD = 0x68,
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SH_DRCR0 = 0x71,
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SH_DRCR1,
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SH_WTCSR = 0x80,
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SH_WTCNT,
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SH_RSTCSR = 0x83,
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SH_SBYCR = 0x91,
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SH_CCR,
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SH_ICR = 0xE0,
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SH_IPRA = 0xE2,
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SH_VCRWDT = 0xE4,
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SH_DVSR = 0x100,
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SH_DVDNT = 0x104,
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SH_DVCR = 0x108,
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SH_VCRDIV = 0x10C,
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SH_DVDNTH = 0x110,//does this have a mirror at 0x118?
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SH_DVDNTL = 0x114,
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SH_DVDNTH_ALT = 0x118,
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SH_DVDNTL_ALT = 0x11C,
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//TODO: user break controller
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SH_SAR0 = 0x180,
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SH_DAR0 = 0x184,
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SH_TCR0 = 0x188,
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SH_CHCR0 = 0x18C,
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SH_SAR1 = 0x190,
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SH_DAR1 = 0x194,
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SH_TCR1 = 0x198,
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SH_CHCR1 = 0x19C,
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SH_VCRDMA0 = 0x1A0,
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SH_VCRDMA1 = 0x1A8,
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SH_DMAOR = 0x1B0,
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SH_BCR1 = 0x1E0,
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SH_BCR2 = 0x1E4,
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SH_WCR = 0x1E8,
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SH_MCR = 0x1EC,
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SH_RTCSR = 0x1F0,
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SH_RTCNT = 0x1F4,
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SH_RTCOR = 0x1F8
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};
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#define BIT_SMR_CA 0x80
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#define BIT_SMR_CHR 0x40
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#define BIT_SMR_PE 0x20
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#define BIT_SMR_STOP 0x08
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#define MASK_SMR_CKS 0x03
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#define BIT_SCR_TIE 0x80
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#define BIT_SCR_RIE 0x40
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#define BIT_SCR_TE 0x20
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#define BIT_SCR_RE 0x10
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#define BIT_SCR_TEIE 0x04
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#define MASK_SCR_CKE 0x03
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#define BIT_SSR_TDRE 0x80
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#define BIT_SSR_RDRF 0x40
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#define BIT_SSR_ORER 0x20
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#define BIT_SSR_TEND 0x04
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#define BIT_TOCR_OCRS 0x10
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#define BIT_FTCSR_OCFA 0x08
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#define BIT_FTCSR_OCFB 0x04
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#define BIT_FTCSR_OVF 0x02
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#define BIT_FTCSR_CCLRA 0x01
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#define BIT_WTCSR_OVF 0x80
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#define BIT_WTCSR_WTIT 0x40
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#define BIT_WTCSR_TME 0x20
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#define BIT_RSTCSR_WOVF 0x80
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#define BIT_RSTCSR_RSTE 0x40
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#define BIT_RSTCSR_RSTS 0x20
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#define BIT_CCR_CP 0x10
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#define BIT_CCR_TW 0x08
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#define BIT_CCR_OD 0x04
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#define BIT_CCR_ID 0x02
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#define BIT_CCR_CE 0x01
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#define BIT_CHCR_IE 0x04
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#define BIT_CHCR_TE 0x02
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#define BIT_CHCR_DE 0x01
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#define BIT_DMAOR_PR 0x08
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#define BIT_DMAOR_DMIE 0x01
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typedef void (*sci_handler)(void *data, uint32_t cycle, uint8_t byte);
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typedef struct {
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void *sci_handler_data;
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sci_handler transmit_handler;
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uint32_t cycle;
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uint32_t divide_counter;
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uint32_t transmit_counter;
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uint32_t frc_counter;
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uint32_t wdt_counter;
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int32_t quotient;
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int32_t remainder;
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uint16_t ocra;
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uint16_t ocrb;
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uint8_t div_overflow;
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uint8_t frc_temp;
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uint8_t tsr;
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uint8_t ti_pending;
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uint8_t ri_pending;
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uint8_t tei_pending;
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uint8_t eri_pending;
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uint8_t dmac_which;
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uint8_t dmac0_run;
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uint8_t dmac1_run;
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uint8_t dreq0;
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uint8_t dreq1;
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uint8_t dmac0_pending;
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uint8_t dmac1_pending;
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uint8_t iti_pending;
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uint8_t divu_loaded;
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} sh7095_periph;
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void sh7095_setup(sh2_context *sh2);
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void sh7095_free(sh2_context *sh2);
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void sh7095_adjust_cycles(sh2_context *sh2, uint32_t deduction);
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void sh7095_sci_to_sh7095_sci(void *data, uint32_t cycle, uint8_t byte);
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void sh7095_next_int(sh2_context *sh2, uint32_t priority_mask);
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void sh7095_assert_dreq0(sh2_context *sh2);
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void sh7095_assert_dreq1(sh2_context *sh2);
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void sh7095_clear_dreq0(sh2_context *sh2);
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void sh7095_clear_dreq1(sh2_context *sh2);
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#endif //SH7095_H_
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