diff --git a/higan/emulator/emulator.hpp b/higan/emulator/emulator.hpp
index a6d1ff24..da17fb40 100644
--- a/higan/emulator/emulator.hpp
+++ b/higan/emulator/emulator.hpp
@@ -30,7 +30,7 @@ using namespace nall;
 
 namespace Emulator {
   static const string Name    = "higan";
-  static const string Version = "106.72";
+  static const string Version = "106.73";
   static const string Author  = "byuu";
   static const string License = "GPLv3";
   static const string Website = "https://byuu.org/";
diff --git a/higan/processor/tlcs900h/instruction.cpp b/higan/processor/tlcs900h/instruction.cpp
index ad6f7896..8bca259b 100644
--- a/higan/processor/tlcs900h/instruction.cpp
+++ b/higan/processor/tlcs900h/instruction.cpp
@@ -27,20 +27,42 @@ auto TLCS900H::instruction() -> void {
   case 0x15: return instructionPop<Byte>(A);
   case 0x18: return instructionPush<Byte>(r.sr.f);
   case 0x19: return instructionPop<Byte>(r.sr.f);
+  case 0x1a: return instructionJump<Word>(Immediate{fetch<uint16>()});
+  case 0x1b: return instructionJump<Long>(Immediate{fetch<uint24>()});
   case 0x1f: return (void)Undefined;
 
+  case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+    return instructionLoad<Byte>(registerLookup<Byte>(data), Immediate{fetch<Byte>()});
+
   case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
     return instructionPush<Word>(registerLookup<Word>(data));
 
+  case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+    return instructionLoad<Word>(registerLookup<Word>(data), Immediate{fetch<Word>()});
+
   case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
     return instructionPush<Long>(registerLookup<Long>(data));
 
+  case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+    return instructionLoad<Long>(registerLookup<Long>(data), Immediate{fetch<Long>()});
+
   case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
     return instructionPop<Word>(registerLookup<Word>(data));
 
+  case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+    return (void)Undefined;
+
   case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
     return instructionPop<Long>(registerLookup<Long>(data));
 
+  case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+  case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+    return instructionJumpRelative(data & 15, fetch< int8>());
+
+  case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
+  case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+    return instructionJumpRelative(data & 15, fetch<int16>());
+
   case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
     memory = {read<Long>(register)};
     return instructionSourceMemory<Byte>(memory);
@@ -244,7 +266,7 @@ auto TLCS900H::instruction() -> void {
     return (void)Undefined;
 
   case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
-    return instructionSoftwareInterrupt(Immediate{data.bits(0,2)});
+    return instructionSoftwareInterrupt(data.bits(0,2));
   }
 }
 
@@ -258,10 +280,16 @@ auto TLCS900H::instructionRegister(Register register) -> void {
 
   case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
     return instructionAdd<Size>(registerLookup<Size>(data), register);
+  case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+    return instructionLoad<Size>(registerLookup<Size>(data), register);
   case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
     return instructionAddCarry<Size>(registerLookup<Size>(data), register);
+  case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+    return instructionLoad<Size>(register, registerLookup<Size>(data));
   case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
     return instructionSubtract<Size>(registerLookup<Size>(data), register);
+  case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+    return instructionLoad<Size>(register, Immediate{data.bits(0,2)});
   case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
     return instructionSubtractCarry<Size>(registerLookup<Size>(data), register);
   case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
@@ -277,7 +305,7 @@ auto TLCS900H::instructionRegister(Register register) -> void {
   case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
     return instructionXor<Size>(registerLookup<Size>(data), register);
   case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
-    return instructionCompare<Size>(register, Immediate{data & 7});
+    return instructionCompare<Size>(register, Immediate{data.bits(0,2)});
   case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
     return instructionOr<Size>(registerLookup<Size>(data), register);
   case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
@@ -290,20 +318,25 @@ auto TLCS900H::instructionSourceMemory(Memory memory) -> void {
   auto data = fetch();
 
   switch(data) {
-  case 0x04:
-    if constexpr(isLong<Size>()) return (void)Undefined;
+  case 0x00: case 0x01: case 0x02: case 0x03: return (void)Undefined;
+  case 0x04: if constexpr(isLong<Size>()) return (void)Undefined;
     return instructionPush<Size>(memory);
-  case 0x38:
-    if constexpr(isLong<Size>()) return (void)Undefined;
+  case 0x05: return (void)Undefined;
+  case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: return (void)Undefined;
+  case 0x18: return (void)Undefined;
+  case 0x19: if constexpr(isLong<Size>()) return (void)Undefined;
+    return instructionLoad<Size>(Memory{fetch<Size>()}, memory);
+  case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: return (void)Undefined;
+  case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+    return instructionLoad<Size>(registerLookup<Size>(data), memory);
+  case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: return (void)Undefined;
+  case 0x38: if constexpr(isLong<Size>()) return (void)Undefined;
     return instructionAdd<Size>(memory, Immediate{fetch<Size>()});
-  case 0x39:
-    if constexpr(isLong<Size>()) return (void)Undefined;
+  case 0x39: if constexpr(isLong<Size>()) return (void)Undefined;
     return instructionAddCarry<Size>(memory, Immediate{fetch<Size>()});
-  case 0x3a:
-    if constexpr(isLong<Size>()) return (void)Undefined;
+  case 0x3a: if constexpr(isLong<Size>()) return (void)Undefined;
     return instructionSubtract<Size>(memory, Immediate{fetch<Size>()});
-  case 0x3b:
-    if constexpr(isLong<Size>()) return (void)Undefined;
+  case 0x3b: if constexpr(isLong<Size>()) return (void)Undefined;
     return instructionSubtractCarry<Size>(memory, Immediate{fetch<Size>()});
   case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
     return instructionAdd<Size>(registerLookup<Size>(data), memory);
@@ -344,7 +377,36 @@ auto TLCS900H::instructionTargetMemory(Memory memory) -> void {
   auto data = fetch();
 
   switch(data) {
+  case 0x01: return (void)Undefined;
+  case 0x03: return (void)Undefined;
   case 0x04: return instructionPop<Byte>(memory);
+  case 0x05: return (void)Undefined;
   case 0x06: return instructionPop<Word>(memory);
+  case 0x07: return (void)Undefined;
+  case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: return (void)Undefined;
+  case 0x10: case 0x11: case 0x12: case 0x13: return (void)Undefined;
+  case 0x15: return (void)Undefined;
+  case 0x17: return (void)Undefined;
+  case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: return (void)Undefined;
+  case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+    return instructionLoad<Word>(registerLookup<Word>(data), memory);
+  case 0x2d: case 0x2e: case 0x2f: return (void)Undefined;
+  case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+    return instructionLoad<Long>(registerLookup<Long>(data), memory);
+  case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f: return (void)Undefined;
+  case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+    return instructionLoad<Byte>(memory, registerLookup<Byte>(data));
+  case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f: return (void)Undefined;
+  case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+    return instructionLoad<Word>(memory, registerLookup<Word>(data));
+  case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: return (void)Undefined;
+  case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+    return instructionLoad<Long>(memory, registerLookup<Long>(data));
+  case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: return (void)Undefined;
+  case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: return (void)Undefined;
+  case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: return (void)Undefined;
+  case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
+  case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
+    return instructionJump<Long>(data.bits(0,3), memory);
   }
 }
diff --git a/higan/processor/tlcs900h/instructions.cpp b/higan/processor/tlcs900h/instructions.cpp
index 7c2a2a7e..a5b01cff 100644
--- a/higan/processor/tlcs900h/instructions.cpp
+++ b/higan/processor/tlcs900h/instructions.cpp
@@ -28,6 +28,24 @@ auto TLCS900H::instructionComplementCarry() -> void {
   CF = !CF;
 }
 
+template<typename Size, typename Source> auto TLCS900H::instructionJump(Source source) -> void {
+  PC = read(source);
+}
+
+template<typename Size, typename Source> auto TLCS900H::instructionJump(uint4 code, Source source) -> void {
+  auto address = read(source);
+  if(condition(code)) PC = address;
+}
+
+template<typename Size> auto TLCS900H::instructionJumpRelative(uint4 code, Size displacement) -> void {
+  if(condition(code)) PC += displacement;
+}
+
+template<typename Size, typename Target, typename Source>
+auto TLCS900H::instructionLoad(Target target, Source source) -> void {
+  write(target, read(source));
+}
+
 auto TLCS900H::instructionNoOperation() -> void {
 }
 
@@ -46,7 +64,8 @@ auto TLCS900H::instructionPush(Source source) -> void {
   push(read(source));
 }
 
-auto TLCS900H::instructionSoftwareInterrupt(Immediate interrupt) -> void {
+auto TLCS900H::instructionSoftwareInterrupt(uint3 interrupt) -> void {
+  //TODO
 }
 
 template<typename Size, typename Target, typename Source>
diff --git a/higan/processor/tlcs900h/memory.cpp b/higan/processor/tlcs900h/memory.cpp
index e0918128..97cadf95 100644
--- a/higan/processor/tlcs900h/memory.cpp
+++ b/higan/processor/tlcs900h/memory.cpp
@@ -1,25 +1,30 @@
-template<> auto TLCS900H::fetch<uint8>() -> uint8 {
+template<> auto TLCS900H::fetch<Byte>() -> Byte {
   return 0x00;
 }
 
-template<> auto TLCS900H::fetch<uint16>() -> uint16 {
-  uint16 data = fetch<uint8>();
-  return data | fetch<uint8>() << 8;
+template<> auto TLCS900H::fetch<Word>() -> Word {
+  uint16 data = fetch<Byte>();
+  return data | fetch<Byte>() << 8;
 }
 
 template<> auto TLCS900H::fetch<uint24>() -> uint24 {
-  uint24 data  = fetch<uint8>();
-         data |= fetch<uint8>() << 8;
-  return data |= fetch<uint8>() << 16;
+  uint24 data  = fetch<Byte>();
+         data |= fetch<Byte>() << 8;
+  return data |= fetch<Byte>() << 16;
 }
 
-template<> auto TLCS900H::fetch<uint32>() -> uint32 {
-  uint32 data  = fetch<uint8>();
-         data |= fetch<uint8>() << 8;
-         data |= fetch<uint8>() << 16;
-  return data |= fetch<uint8>() << 24;
+template<> auto TLCS900H::fetch<Long>() -> Long {
+  uint32 data  = fetch<Byte>();
+         data |= fetch<Byte>() << 8;
+         data |= fetch<Byte>() << 16;
+  return data |= fetch<Byte>() << 24;
 }
 
+template<> auto TLCS900H::fetch< int8>() ->  int8 { return ( int8)fetch< uint8>(); }
+template<> auto TLCS900H::fetch<int16>() -> int16 { return (int16)fetch<uint16>(); }
+template<> auto TLCS900H::fetch<int24>() -> int24 { return (int24)fetch<uint24>(); }
+template<> auto TLCS900H::fetch<int32>() -> int32 { return (int32)fetch<uint32>(); }
+
 //
 
 #define XSP r.xsp.l.l0
diff --git a/higan/processor/tlcs900h/tlcs900h.cpp b/higan/processor/tlcs900h/tlcs900h.cpp
index 898a518d..f4425c3a 100644
--- a/higan/processor/tlcs900h/tlcs900h.cpp
+++ b/higan/processor/tlcs900h/tlcs900h.cpp
@@ -3,10 +3,9 @@
 
 namespace Processor {
 
-//todo: these defines should not be necessary; yet ADL doesn't work without them ... why not?
-#define Byte uint8
-#define Word uint16
-#define Long uint32
+using Byte =  uint8;
+using Word = uint16;
+using Long = uint32;
 
 template<typename Size> static constexpr auto isByte() -> bool { return is_same<Size, Byte>::value; }
 template<typename Size> static constexpr auto isWord() -> bool { return is_same<Size, Word>::value; }
diff --git a/higan/processor/tlcs900h/tlcs900h.hpp b/higan/processor/tlcs900h/tlcs900h.hpp
index 8ccb57e8..96e2578f 100644
--- a/higan/processor/tlcs900h/tlcs900h.hpp
+++ b/higan/processor/tlcs900h/tlcs900h.hpp
@@ -12,7 +12,7 @@
 namespace Processor {
 
 struct TLCS900H {
-  using Byte = uint8;
+  using Byte =  uint8;
   using Word = uint16;
   using Long = uint32;
 
@@ -94,11 +94,15 @@ struct TLCS900H {
   template<typename Size, typename Target, typename Source> auto instructionAnd(Target target, Source source) -> void;
   template<typename Size, typename Target, typename Source> auto instructionCompare(Target target, Source source) -> void;
   auto instructionComplementCarry() -> void;
+  template<typename Size, typename Source> auto instructionJump(Source) -> void;
+  template<typename Size, typename Source> auto instructionJump(uint4 code, Source) -> void;
+  template<typename Size> auto instructionJumpRelative(uint4 code, Size displacement) -> void;
+  template<typename Size, typename Target, typename Source> auto instructionLoad(Target target, Source source) -> void;
   auto instructionNoOperation() -> void;
   template<typename Size, typename Target, typename Source> auto instructionOr(Target target, Source source) -> void;
   template<typename Size, typename Target> auto instructionPop(Target target) -> void;
   template<typename Size, typename Source> auto instructionPush(Source source) -> void;
-  auto instructionSoftwareInterrupt(Immediate interrupt) -> void;
+  auto instructionSoftwareInterrupt(uint3 interrupt) -> void;
   template<typename Size, typename Target, typename Source> auto instructionSubtract(Target target, Source source) -> void;
   template<typename Size, typename Target, typename Source> auto instructionSubtractCarry(Target target, Source source) -> void;
   template<typename Size, typename Target, typename Source> auto instructionXor(Target target, Source source) -> void;
diff --git a/nall/platform.hpp b/nall/platform.hpp
index a6566220..9140f68f 100644
--- a/nall/platform.hpp
+++ b/nall/platform.hpp
@@ -1,7 +1,5 @@
 #pragma once
 
-#define register $register
-
 #include <nall/intrinsics.hpp>
 
 namespace Math {
@@ -120,3 +118,5 @@ namespace Math {
 #else
   #define unreachable throw
 #endif
+
+#define register $register
diff --git a/nall/windows/guard.hpp b/nall/windows/guard.hpp
index bb067d2f..353874cb 100644
--- a/nall/windows/guard.hpp
+++ b/nall/windows/guard.hpp
@@ -26,8 +26,9 @@
 #undef NALL_WINDOWS_GUARD_HPP
 
 #undef boolean
-#undef far
 #undef interface
+
+#undef far
 #undef near
 
 #endif