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Fix adc/sbc and add_hl_rr hfc calc, sp_plus_n cf/hcf calc and daa thanks to blargg.
git-svn-id: https://gambatte.svn.sourceforge.net/svnroot/gambatte@68 9dfb2916-2d38-0410-aef4-c5fe6c9ffc24
This commit is contained in:
sinamas
parent
357c8d6683
commit
4968e85afc
@ -86,6 +86,23 @@ bool CPU::load(const char* romfile) {
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return cycleCounter;
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}*/
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// (HF2 & 0x200) == true means HF is set.
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static inline void calcHF(const unsigned HF1, unsigned& HF2) {
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unsigned arg1 = HF1 & 0xF;
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unsigned arg2 = (HF2 & 0xF) + (HF2 >> 8 & 1);
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if (HF2 & 0x800) {
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arg1 = arg2;
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arg2 = 1;
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}
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if (HF2 & 0x400)
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arg1 -= arg2;
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else
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arg1 = arg1 + arg2 << 5;
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HF2 |= arg1 & 0x200;
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}
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#define BC() ( (B << 8) | C )
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#define DE() ( (D << 8) | E )
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@ -272,8 +289,8 @@ bool CPU::load(const char* romfile) {
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//Add 8-bit value+CF to A, check flags:
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#define adc_a_u8(u8) do { \
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HF1 = A; \
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HF2 = ((CF >> 8) & 1) + (u8); \
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A = ZF = CF = HF2 + A; \
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HF2 = (CF & 0x100) | (u8); \
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A = ZF = CF = ((CF >> 8) & 1) + (u8) + A; \
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} while (0)
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//sub a,r (4 cycles):
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@ -291,9 +308,8 @@ bool CPU::load(const char* romfile) {
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//Subtract CF and 8-bit value from A, check flags:
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#define sbc_a_u8(u8) do { \
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HF1 = A; \
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HF2 = ((CF >> 8) & 1) + (u8); \
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A = ZF = CF = A - HF2; \
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HF2 |= 0x400; \
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HF2 = 0x400 | (CF & 0x100) | (u8); \
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A = ZF = CF = A - ((CF >> 8) & 1) - (u8); \
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} while (0)
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//and a,r (4 cycles):
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@ -351,13 +367,21 @@ bool CPU::load(const char* romfile) {
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//16-BIT ARITHMETIC
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//add hl,rr (8 cycles):
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//add 16-bit register to HL, check flags except ZF:
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#define add_hl_rr(rh, rl) do { \
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/*#define add_hl_rr(rh, rl) do { \
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L = HF1 = L + (rl); \
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HF1 >>= 8; \
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HF1 += H; \
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HF2 = (rh); \
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H = CF = HF1 + (rh); \
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cycleCounter += 4; \
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} while (0)*/
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#define add_hl_rr(rh, rl) do { \
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L = CF = L + (rl); \
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HF1 = H; \
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HF2 = (CF & 0x100) | (rh); \
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H = CF = H + (CF >> 8) + (rh); \
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cycleCounter += 4; \
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} while (0)
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//inc rr (8 cycles):
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@ -378,6 +402,16 @@ bool CPU::load(const char* romfile) {
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cycleCounter += 4; \
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} while (0)
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#define sp_plus_n(sumout) do { \
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const unsigned sp_plus_n_var_n = int8_t(memory.pc_read(PC++, cycleCounter)); \
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const unsigned sp_plus_n_var_sum = SP + sp_plus_n_var_n; \
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CF = SP ^ sp_plus_n_var_n ^ sp_plus_n_var_sum; \
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HF2 = CF << 5 & 0x200; \
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ZF = 1; \
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cycleCounter += 8; \
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(sumout) = sp_plus_n_var_sum; \
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} while (0)
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//JUMPS:
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//jp nn (16 cycles):
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//Jump to address stored in the next two bytes in memory:
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@ -652,30 +686,43 @@ void CPU::process(const unsigned cycles) {
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//daa (4 cycles):
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//Adjust register A to correctly represent a BCD. Check ZF, HF and CF:
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case 0x27:
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{
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unsigned correction = ((A > 0x99) || (CF & 0x100)) ? 0x60 : 0x00;
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/*{
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unsigned correction = ((A > 0x99) || (CF & 0x100)) ? 0x60 : 0x00;
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calcHF(HF1, HF2);
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if ((A & 0x0F) > 0x09 || (HF2 & 0x200))
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correction |= 0x06;
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HF1 = A;
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HF2 = (HF2 & 0x400) | correction;
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CF = (correction & 0x40) << 2;
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A = (HF2 & 0x400) ? A - correction : (A + correction);
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ZF = A;
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}*/
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if (HF2 & 0x400) {
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if (HF2 & 0x800)
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HF2 |= ((HF2 & 0xF) - 1) & 0x200;
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else
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HF2 |= ((HF1 & 0xF) - (HF2 & 0xF)) & 0x200;
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} else {
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if (HF2 & 0x800)
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HF2 |= (((HF2 & 0xF) + 1) & 0x10) << 5;
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else
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HF2 |= (((HF1 & 0xF) + (HF2 & 0xF)) & 0x10) << 5;
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calcHF(HF1, HF2);
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{
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unsigned correction = (CF & 0x100) ? 0x60 : 0x00;
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if (HF2 & 0x200)
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correction |= 0x06;
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if (!(HF2 &= 0x400)) {
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if ((A & 0x0F) > 0x09)
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correction |= 0x06;
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if (A > 0x99)
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correction |= 0x60;
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A += correction;
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} else
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A -= correction;
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CF = correction << 2 & 0x100;
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ZF = A;
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}
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if ((A & 0x0F) > 0x09 || (HF2 & 0x200))
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correction |= 0x06;
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HF1 = A;
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HF2 = (HF2 & 0x400) | correction;
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CF = (correction & 0x40) << 2;
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A = (HF2 & 0x400) ? A - correction : (A + correction);
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ZF = A;
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}
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break;
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//jr z,disp (12;8 cycles):
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@ -2548,15 +2595,18 @@ void CPU::process(const unsigned cycles) {
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//add sp,n (16 cycles):
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//Add next (signed) byte in memory to SP, reset ZF and SF, check HCF and CF:
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case 0xE8: {
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int8_t tmp = int8_t(memory.pc_read(PC++, cycleCounter));
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HF2 = (((SP & 0xFFF) + tmp) >> 3) & 0x200;
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CF = SP + tmp;
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SP = CF;
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CF >>= 8;
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ZF = 1;
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cycleCounter += 12;
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}
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case 0xE8:
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/*{
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int8_t tmp = int8_t(memory.pc_read(PC++, cycleCounter));
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HF2 = (((SP & 0xFFF) + tmp) >> 3) & 0x200;
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CF = SP + tmp;
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SP = CF;
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CF >>= 8;
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ZF = 1;
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cycleCounter += 12;
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}*/
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sp_plus_n(SP);
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cycleCounter += 4;
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break;
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//jp hl (4 cycles):
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@ -2639,17 +2689,8 @@ void CPU::process(const unsigned cycles) {
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case 0xF4: /*doesn't exist*/
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break;
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case 0xF5: /*push_rr(A, F); Cycles(16); break;*/
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if (HF2&0x400) {
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if (HF2&0x800)
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HF2 |= ((HF2 & 0xF) - 1) & 0x200;
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else
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HF2 |= ((HF1 & 0xF) - (HF2 & 0xF)) & 0x200;
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} else {
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if (HF2&0x800)
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HF2 |= (((HF2 & 0xF) + 1) & 0x10) << 5;
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else
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HF2 |= (((HF1 & 0xF) + (HF2 & 0xF)) & 0x10) << 5;
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}
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calcHF(HF1, HF2);
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{
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unsigned F = HF2 & 0x600;
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F |= CF & 0x100;
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@ -2676,7 +2717,7 @@ void CPU::process(const unsigned cycles) {
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//ldhl sp,n (12 cycles):
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//Put (sp+next (signed) byte in memory) into hl (unsets ZF and SF, may enable HF and CF):
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case 0xF8:
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{
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/*{
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int8_t tmp = int8_t(memory.pc_read(PC++, cycleCounter));
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HF2 = (((SP & 0xFFF) + tmp) >> 3) & 0x200;
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CF = SP + tmp;
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@ -2685,6 +2726,12 @@ void CPU::process(const unsigned cycles) {
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H = CF;
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ZF = 1;
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cycleCounter += 8;
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}*/
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{
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unsigned sum;
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sp_plus_n(sum);
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L = sum;
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H = sum >> 8;
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}
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break;
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