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Makefile: use $(CC), not gcc

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This commit is contained in:
John Hawthorn 2013-02-03 17:53:03 -08:00
parent bbd831404d
commit 7832e2a2ee
1 changed files with 1 additions and 1 deletions
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2
Makefile
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@ -6,7 +6,7 @@ TARGET := vecx
CLEANFILES := $(TARGET) $(OBJECTS)
$(TARGET): $(OBJECTS)
gcc $(CFLAGS) -o $@ $^ $(LIBS)
$(CC) $(CFLAGS) -o $@ $^ $(LIBS)
clean:
$(RM) $(CLEANFILES)