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GB Serialize: Add MBC state serialization
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@ -173,6 +173,7 @@ Misc:
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- Qt: Minor test fixes
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- PSP2: Update toolchain to use vita.cmake
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- Qt: Move shader settings into main settings window
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- GB Serialize: Add MBC state serialization
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0.6 beta 1: (2017-06-29)
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- Initial beta for 0.6
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@ -18,6 +18,7 @@ struct GB;
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struct GBMemory;
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void GBMBCInit(struct GB* gb);
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void GBMBCSwitchBank(struct GB* gb, int bank);
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void GBMBCSwitchBank0(struct GB* gb, int bank);
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void GBMBCSwitchSramBank(struct GB* gb, int bank);
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struct GBMBCRTCSaveBuffer {
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@ -145,7 +145,7 @@ mLOG_DECLARE_CATEGORY(GB_STATE);
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* | 0x0017C - 0x0017D: HDMA remaining
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* | 0x0017E: DMA remaining
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* | 0x0017F - 0x00183: RTC registers
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* | 0x00184 - 0x00193: MBC state (TODO)
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* | 0x00184 - 0x00193: MBC state
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* | 0x00194 - 0x00195: Flags
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* | bit 0: SRAM accessable
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* | bit 1: RTC accessible
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@ -331,18 +331,21 @@ struct GBSerializedState {
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union {
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struct {
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uint32_t mode;
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uint8_t mode;
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uint8_t multicartStride;
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} mbc1;
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struct {
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uint64_t lastLatch;
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} rtc;
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struct {
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int8_t machineState;
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GBMBC7Field field;
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int8_t address;
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uint8_t state;
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GBMBC7Field eeprom;
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uint8_t address;
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uint8_t access;
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uint8_t latch;
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uint8_t srBits;
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uint32_t sr;
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GBSerializedMBC7Flags flags;
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uint16_t sr;
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uint32_t writable;
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} mbc7;
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struct {
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uint8_t reserved[16];
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@ -50,7 +50,7 @@ void GBMBCSwitchBank(struct GB* gb, int bank) {
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}
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}
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static void _switchBank0(struct GB* gb, int bank) {
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void GBMBCSwitchBank0(struct GB* gb, int bank) {
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size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
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if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
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mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
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@ -320,7 +320,7 @@ void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
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case 0x2:
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bank &= 3;
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if (memory->mbcState.mbc1.mode) {
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_switchBank0(gb, bank);
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GBMBCSwitchBank0(gb, bank);
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GBMBCSwitchSramBank(gb, bank);
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}
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GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
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@ -328,9 +328,9 @@ void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
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case 0x3:
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memory->mbcState.mbc1.mode = value & 1;
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if (memory->mbcState.mbc1.mode) {
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_switchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
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GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
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} else {
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_switchBank0(gb, 0);
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GBMBCSwitchBank0(gb, 0);
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GBMBCSwitchSramBank(gb, 0);
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}
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break;
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@ -629,6 +629,28 @@ void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state) {
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flags = GBSerializedMemoryFlagsSetIsHdma(flags, memory->isHdma);
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flags = GBSerializedMemoryFlagsSetActiveRtcReg(flags, memory->activeRtcReg);
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STORE_16LE(flags, 0, &state->memory.flags);
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switch (memory->mbcType) {
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case GB_MBC1:
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state->memory.mbc1.mode = memory->mbcState.mbc1.mode;
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state->memory.mbc1.multicartStride = memory->mbcState.mbc1.multicartStride;
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break;
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case GB_MBC3_RTC:
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STORE_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
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break;
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case GB_MBC7:
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state->memory.mbc7.state = memory->mbcState.mbc7.state;
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state->memory.mbc7.eeprom = memory->mbcState.mbc7.eeprom;
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state->memory.mbc7.address = memory->mbcState.mbc7.address;
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state->memory.mbc7.access = memory->mbcState.mbc7.access;
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state->memory.mbc7.latch = memory->mbcState.mbc7.latch;
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state->memory.mbc7.srBits = memory->mbcState.mbc7.srBits;
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STORE_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
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STORE_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
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break;
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default:
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break;
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}
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}
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void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state) {
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@ -671,6 +693,32 @@ void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state) {
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memory->ime = GBSerializedMemoryFlagsGetIme(flags);
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memory->isHdma = GBSerializedMemoryFlagsGetIsHdma(flags);
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memory->activeRtcReg = GBSerializedMemoryFlagsGetActiveRtcReg(flags);
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switch (memory->mbcType) {
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case GB_MBC1:
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memory->mbcState.mbc1.mode = state->memory.mbc1.mode;
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memory->mbcState.mbc1.multicartStride = state->memory.mbc1.multicartStride;
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if (memory->mbcState.mbc1.mode) {
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GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
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}
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break;
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case GB_MBC3_RTC:
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// TODO?
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//LOAD_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
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break;
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case GB_MBC7:
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memory->mbcState.mbc7.state = state->memory.mbc7.state;
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memory->mbcState.mbc7.eeprom = state->memory.mbc7.eeprom;
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memory->mbcState.mbc7.address = state->memory.mbc7.address & 0x7F;
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memory->mbcState.mbc7.access = state->memory.mbc7.access;
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memory->mbcState.mbc7.latch = state->memory.mbc7.latch;
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memory->mbcState.mbc7.srBits = state->memory.mbc7.srBits;
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LOAD_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
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LOAD_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
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break;
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default:
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break;
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}
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}
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void _pristineCow(struct GB* gb) {
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