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Implement LDR(1)
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@ -101,7 +101,7 @@ DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, ARM_STUB)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, ARM_STUB)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
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