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texdecode_test.sh builds texdecode_test.c, a C program, against the
texture cache itself (core/rend/TexCache.o, through the small C++ shim
texdecode_cpu.cpp) and runs it on a Vulkan device - Mesa's software one,
lavapipe, when it is installed - with the validation layer on when that
is.
Close to 8000 textures: every pixel format, the reserved one too;
twiddled, compressed, planar and planar compressed; with and without
mipmaps, every mipmapped size, and sizes from 8x8 to 1024x1024 square and
not; planar ones with no stride, narrower, wider and empty strides, and
running into the end of video memory; paletted ones with every palette
format and random selections, as colours and as the indices the GPU
looks up itself; 16-bit formats to 16 bits and to 32; Force Texture LOD0;
then 2000 random ones. Each is made by the texture cache, which converts
it on the CPU and says what it would hand a renderer that converts on
the GPU. From those bytes the C text of the kernel, and then the kernel
on the device, into images made as the renderer makes them, have to
make every level the CPU made, byte for byte. A planar 16-bit texture
the renderer copies to its image as it is has to read, texel by texel,
as the same colour the CPU's texels do.
The script also builds the header as C89 and C++, compiles the three
GLSL kernels and the HLSL one (texdecode_kernel.hlsl, the shape a
Direct3D renderer will have) with glslangValidator, and checks that
core/rend/texdecode_text.inc is still the header ('update' makes it
again).
116 lines
3.4 KiB
C++
116 lines
3.4 KiB
C++
/* The CPU's side of texdecode_test.c: the texture cache itself
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* (core/rend/TexCache.o) making a texture, with what it would hand a
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* renderer that converts on the GPU caught on the way.
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*
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* A texture is made with BaseTextureCacheData::Create() and Update(), as
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* the renderers make them. Update() first offers the texture to
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* GpuDecode(), which takes the plan and says no; then converts it on the
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* CPU and hands the texels to UploadToGPU(), which takes those. So one
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* Update() gives both, from the same state. */
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// the registers the frame is rendered with, as the texture cache reads them
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#define PVR_REGS_FOR_RENDERER
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#include <cstdio>
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#include <cstdlib>
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#include <cstring>
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#include "types.h"
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#include "rend/TexCache.h"
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#include "rend/texdecode.h"
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#include "hw/pvr/pvr_regs.h"
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#include "texdecode_case.h"
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// what the texture cache takes from the rest of the core
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settings_t settings;
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u32 FrameCount = 1;
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unsigned VRAM_SIZE = 8 * 1024 * 1024;
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unsigned VRAM_MASK = 8 * 1024 * 1024 - 1;
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static u8 pvr_regs_mem[0x10000];
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u8 *rend_pvr_regs = pvr_regs_mem;
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void _vmem_protect_vram(u32, u32) {}
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void _vmem_unprotect_vram(u32, u32) {}
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u32 _vmem_get_vram_offset(void *) { return (u32)-1; }
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bool _vmem_vram_page_protected(u32) { return false; }
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void os_DebugBreak() { abort(); }
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void GenericLog(LogTypes::LOG_LEVELS, LogTypes::LOG_TYPE, const char *, int, const char *, ...) {}
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extern VArray2 vram;
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namespace {
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struct TestTexture : public BaseTextureCacheData
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{
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bool force32 = false;
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bool planned = false;
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texd_plan plan;
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u8 *out = nullptr;
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size_t cap = 0, bytes = 0;
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std::string GetId() override { return "test"; }
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bool Force32BitTexture(TextureType type) const override { return force32; }
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bool GpuDecode(const texd_plan& p) override
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{
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plan = p;
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planned = true;
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return false;
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}
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void UploadToGPU(int width, int height, u8 *data, bool mipmapped, bool mipmapsIncluded) override
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{
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const size_t pixel = tex_type == TextureType::_8888 ? 4 : tex_type == TextureType::_8 ? 1 : 2;
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size_t n = (size_t)width * height * pixel;
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if (mipmapsIncluded)
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for (int w = width / 2; w != 0; w /= 2)
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n += (size_t)w * w * pixel;
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bytes = n <= cap ? n : 0;
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if (bytes != 0)
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memcpy(out, data, n);
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}
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};
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}
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extern "C" void texd_cpu_init(void *video_memory)
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{
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vram.data = (u8 *)video_memory;
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vram.size = VRAM_SIZE;
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settings.rend.TextureUpscale = 1;
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settings.rend.MaxFilteredTextureSize = 256;
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settings.rend.GpuTextureDecode = true;
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}
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extern "C" int texd_cpu_run(const struct texd_case *c, struct texd_plan *plan, void *out, size_t cap, size_t *bytes, int *type)
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{
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TestTexture t;
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t.tcw.full = 0;
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t.tcw.TexAddr = c->addr >> 3;
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t.tcw.PixelFmt = c->fmt;
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t.tcw.ScanOrder = c->scan_order;
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t.tcw.VQ_Comp = c->vq;
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t.tcw.MipMapped = c->mip;
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t.tcw.StrideSel = c->stride_sel;
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if (c->fmt == PixelPal4 || c->fmt == PixelPal8)
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t.tcw.PalSelect = c->pal_select; // (over the bits above it: as the hardware has it)
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t.tsp.full = 0;
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t.tsp.TexU = c->tex_u;
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t.tsp.TexV = c->tex_v;
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t.tsp.FilterMode = c->filter;
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t.area = 0;
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t.force32 = c->force32 != 0;
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settings.rend.ForceTextureLOD0 = c->lod0 != 0;
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TEXT_CONTROL = c->text_control;
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PAL_RAM_CTRL = c->pal_ctrl;
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palette_update();
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t.out = (u8 *)out;
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t.cap = cap;
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t.Create();
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t.Update();
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t.Delete();
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*bytes = t.bytes;
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*type = (int)t.tex_type;
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if (t.planned)
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*plan = t.plan;
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return t.planned;
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}
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/* For the palette: the registers' memory */
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extern "C" void *texd_cpu_palette_ram(void)
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{
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return PALETTE_RAM;
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}
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