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twinaphex
parent
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commit
ae955d5844
@ -1,41 +1,10 @@
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/******************************************************************************\
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* Authors: Iconoclast *
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* Release: 2013.12.04 *
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* License: CC0 Public Domain Dedication *
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* *
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* To the extent possible under law, the author(s) have dedicated all copyright *
|
||||
* and related and neighboring rights to this software to the public domain *
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||||
* worldwide. This software is distributed without any warranty. *
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||||
* *
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||||
* You should have received a copy of the CC0 Public Domain Dedication along *
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* with this software. *
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* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>. *
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\******************************************************************************/
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#ifndef _CXD4_CONFIG_H
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#define _CXD4_CONFIG_H
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#include <stdint.h>
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extern unsigned char conf[32];
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#define MINIMUM_MESSAGE_PRIORITY 1
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#define EXTERN_COMMAND_LIST_GBI
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#define EXTERN_COMMAND_LIST_ABI
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#define SEMAPHORE_LOCK_CORRECTIONS
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#define WAIT_FOR_CPU_HOST
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#define EMULATE_STATIC_PC
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#ifdef EMULATE_STATIC_PC
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#define CONTINUE {continue;}
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#define JUMP {goto BRANCH;}
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#else
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#define CONTINUE {break;}
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#define JUMP {break;}
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#endif
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#if (0)
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#define SP_EXECUTE_LOG
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#define VU_EMULATE_SCALAR_ACCUMULATOR_READ
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#endif
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/*
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* The config file used to be a 32-byte EEPROM with binary settings storage.
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* It was found necessary for user and contributor convenience to replace.
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@ -47,33 +16,5 @@ extern unsigned char conf[32];
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#define CFG_HLE_AUD (conf[0x01])
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#define CFG_HLE_VID (conf[0x02]) /* reserved/unused */
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#define CFG_HLE_JPG (conf[0x03]) /* unused */
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/*
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* Most of the point behind this config system is to let users use HLE video
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* or audio plug-ins. The other task types are used less than 1% of the time
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* and only in a few games. They require simulation from within the RSP
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* internally, which I have no intention to ever support. Some good research
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* on a few of these special task types was done by Hacktarux in the MUPEN64
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* HLE RSP plug-in, so consider using that instead for complete HLE.
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*/
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/*
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* Schedule binary dump exports to the DllConfig schedule delay queue.
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*/
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#define CFG_QUEUE_E_DRAM (*(int *)(conf + 0x04))
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#define CFG_QUEUE_E_DMEM (*(int *)(conf + 0x08))
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#define CFG_QUEUE_E_IMEM (*(int *)(conf + 0x0C))
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/*
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* Note: This never actually made it into the configuration system.
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* Instead, DMEM and IMEM are always exported on every call to DllConfig().
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*/
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/*
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* Special switches.
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* (generally for correcting RSP clock behavior on Project64 2.x)
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* Also includes RSP register states debugger.
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*/
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#define CFG_WAIT_FOR_CPU_HOST (*(int *)(conf + 0x10))
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#define CFG_MEND_SEMAPHORE_LOCK (*(int *)(conf + 0x14))
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#define CFG_TRACE_RSP_REGISTERS (*(int *)(conf + 0x18))
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#endif
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@ -1,452 +0,0 @@
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/******************************************************************************\
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* Authors: Iconoclast *
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* Release: 2013.12.11 *
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* License: CC0 Public Domain Dedication *
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* *
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* To the extent possible under law, the author(s) have dedicated all copyright *
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* and related and neighboring rights to this software to the public domain *
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* worldwide. This software is distributed without any warranty. *
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* *
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* You should have received a copy of the CC0 Public Domain Dedication along *
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* with this software. *
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* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>. *
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\******************************************************************************/
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#include "Rsp_#1.1.h"
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#include "rsp.h"
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#include "su.h"
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#include "vu/vu.h"
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#include "matrix.h"
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#define FIT_IMEM(PC) (PC & 0xFFF & 0xFFC)
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NOINLINE void run_task(void)
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{
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register uint32_t PC;
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register unsigned int i;
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#ifdef WAIT_FOR_CPU_HOST
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for (i = 0; i < 32; i++)
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MFC0_count[i] = 0;
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#endif
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PC = FIT_IMEM(*RSP.SP_PC_REG);
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while ((*RSP.SP_STATUS_REG & 0x00000001) == 0x00000000)
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{
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register uint32_t inst;
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register int rd, rs, rt;
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register int base;
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inst = *(uint32_t *)(RSP.IMEM + FIT_IMEM(PC));
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#ifdef EMULATE_STATIC_PC
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PC = (PC + 0x004);
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EX:
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#endif
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#ifdef SP_EXECUTE_LOG
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step_SP_commands(inst);
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#endif
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if (inst >> 25 == 0x25) /* is a VU instruction */
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{
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const int opcode = inst % 64; /* inst.R.func */
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const int vd = (inst & 0x000007FF) >> 6; /* inst.R.sa */
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const int vs = (unsigned short)(inst) >> 11; /* inst.R.rd */
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const int vt = (inst >> 16) & 31; /* inst.R.rt */
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const int e = (inst >> 21) & 0xF; /* rs & 0xF */
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COP2_C2[opcode](vd, vs, vt, e);
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}
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else
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{
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const int op = inst >> 26;
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const int element = (inst & 0x000007FF) >> 7;
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switch (op)
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{
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int16_t offset;
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register uint32_t addr;
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case 000: /* SPECIAL */
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#if (1u >> 1 == 0)
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rd = (inst & 0x0000FFFFu) >> 11;
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/* rs = inst >> 21; // Primary op is 0, so we don't need &= 31. */
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#else
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rd = (inst >> 11) % 32;
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/* rs = (inst >> 21) % 32; */
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#endif
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rt = (inst >> 16) % (1 << 5);
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switch (inst % 64)
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{
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case 000: /* SLL */
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SR[rd] = SR[rt] << MASK_SA(inst >> 6);
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SR[0] = 0x00000000;
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CONTINUE
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case 002: /* SRL */
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SR[rd] = (unsigned)(SR[rt]) >> MASK_SA(inst >> 6);
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SR[0] = 0x00000000;
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CONTINUE
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case 003: /* SRA */
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SR[rd] = (signed)(SR[rt]) >> MASK_SA(inst >> 6);
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SR[0] = 0x00000000;
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CONTINUE
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case 004: /* SLLV */
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SR[rd] = SR[rt] << MASK_SA(SR[rs = inst >> 21]);
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SR[0] = 0x00000000;
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CONTINUE
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case 006: /* SRLV */
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SR[rd] = (unsigned)(SR[rt]) >> MASK_SA(SR[rs = inst >> 21]);
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SR[0] = 0x00000000;
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CONTINUE
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case 007: /* SRAV */
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SR[rd] = (signed)(SR[rt]) >> MASK_SA(SR[rs = inst >> 21]);
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SR[0] = 0x00000000;
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CONTINUE
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case 011: /* JALR */
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SR[rd] = (PC + LINK_OFF) & 0x00000FFC;
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SR[0] = 0x00000000;
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case 010: /* JR */
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set_PC(SR[rs = inst >> 21]);
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JUMP
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case 015: /* BREAK */
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*RSP.SP_STATUS_REG |= 0x00000003; /* BROKE | HALT */
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if (*RSP.SP_STATUS_REG & 0x00000040)
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{ /* SP_STATUS_INTR_BREAK */
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*RSP.MI_INTR_REG |= 0x00000001;
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RSP.CheckInterrupts();
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}
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CONTINUE
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case 040: /* ADD */
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case 041: /* ADDU */
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rs = inst >> 21;
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SR[rd] = SR[rs] + SR[rt];
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SR[0] = 0x00000000; /* needed for Rareware ucodes */
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CONTINUE
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case 042: /* SUB */
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case 043: /* SUBU */
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rs = inst >> 21;
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SR[rd] = SR[rs] - SR[rt];
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SR[0] = 0x00000000;
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CONTINUE
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case 044: /* AND */
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rs = inst >> 21;
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SR[rd] = SR[rs] & SR[rt];
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SR[0] = 0x00000000; /* needed for Rareware ucodes */
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CONTINUE
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case 045: /* OR */
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rs = inst >> 21;
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SR[rd] = SR[rs] | SR[rt];
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SR[0] = 0x00000000;
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CONTINUE
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case 046: /* XOR */
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rs = inst >> 21;
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SR[rd] = SR[rs] ^ SR[rt];
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SR[0] = 0x00000000;
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CONTINUE
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case 047: /* NOR */
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rs = inst >> 21;
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SR[rd] = ~(SR[rs] | SR[rt]);
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SR[0] = 0x00000000;
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CONTINUE
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case 052: /* SLT */
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rs = inst >> 21;
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SR[rd] = ((signed)(SR[rs]) < (signed)(SR[rt]));
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SR[0] = 0x00000000;
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CONTINUE
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case 053: /* SLTU */
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rs = inst >> 21;
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SR[rd] = ((unsigned)(SR[rs]) < (unsigned)(SR[rt]));
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SR[0] = 0x00000000;
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CONTINUE
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default:
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res_S();
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CONTINUE
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}
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CONTINUE
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case 001: /* REGIMM */
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rs = (inst >> 21) & 31;
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rt = (inst >> 16) & 31;
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switch (rt)
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{
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case 020: /* BLTZAL */
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SR[31] = (PC + LINK_OFF) & 0x00000FFC;
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case 000: /* BLTZ */
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if (!(SR[rs] < 0))
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CONTINUE
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set_PC(PC + 4*inst + SLOT_OFF);
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JUMP
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case 021: /* BGEZAL */
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SR[31] = (PC + LINK_OFF) & 0x00000FFC;
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case 001: /* BGEZ */
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if (!(SR[rs] >= 0))
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CONTINUE
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set_PC(PC + 4*inst + SLOT_OFF);
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JUMP
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default:
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res_S();
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CONTINUE
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}
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CONTINUE
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case 003: /* JAL */
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SR[31] = (PC + LINK_OFF) & 0x00000FFC;
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case 002: /* J */
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set_PC(4*inst);
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JUMP
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case 004: /* BEQ */
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rs = (inst >> 21) & 31;
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rt = (inst >> 16) & 31;
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if (!(SR[rs] == SR[rt]))
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CONTINUE
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set_PC(PC + 4*inst + SLOT_OFF);
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JUMP
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case 005: /* BNE */
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rs = (inst >> 21) & 31;
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rt = (inst >> 16) & 31;
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if (!(SR[rs] != SR[rt]))
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CONTINUE
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set_PC(PC + 4*inst + SLOT_OFF);
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JUMP
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case 006: /* BLEZ */
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if (!((signed)SR[rs = (inst >> 21) & 31] <= 0x00000000))
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CONTINUE
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set_PC(PC + 4*inst + SLOT_OFF);
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JUMP
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case 007: /* BGTZ */
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if (!((signed)SR[rs = (inst >> 21) & 31] > 0x00000000))
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CONTINUE
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set_PC(PC + 4*inst + SLOT_OFF);
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JUMP
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case 010: /* ADDI */
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case 011: /* ADDIU */
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rs = (inst >> 21) & 31;
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rt = (inst >> 16) & 31;
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SR[rt] = SR[rs] + (signed short)(inst);
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SR[0] = 0x00000000;
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CONTINUE
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case 012: /* SLTI */
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rs = (inst >> 21) & 31;
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rt = (inst >> 16) & 31;
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SR[rt] = ((signed)(SR[rs]) < (signed short)(inst));
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SR[0] = 0x00000000;
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CONTINUE
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case 013: /* SLTIU */
|
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rs = (inst >> 21) & 31;
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rt = (inst >> 16) & 31;
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SR[rt] = ((unsigned)(SR[rs]) < (unsigned short)(inst));
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SR[0] = 0x00000000;
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CONTINUE
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case 014: /* ANDI */
|
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rs = (inst >> 21) & 31;
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rt = (inst >> 16) & 31;
|
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SR[rt] = SR[rs] & (unsigned short)(inst);
|
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SR[0] = 0x00000000;
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CONTINUE
|
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case 015: /* ORI */
|
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rs = (inst >> 21) & 31;
|
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rt = (inst >> 16) & 31;
|
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SR[rt] = SR[rs] | (unsigned short)(inst);
|
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SR[0] = 0x00000000;
|
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CONTINUE
|
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case 016: /* XORI */
|
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rs = (inst >> 21) & 31;
|
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rt = (inst >> 16) & 31;
|
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SR[rt] = SR[rs] ^ (unsigned short)(inst);
|
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SR[0] = 0x00000000;
|
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CONTINUE
|
||||
case 017: /* LUI */
|
||||
SR[rt = (inst >> 16) & 31] = inst << 16;
|
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SR[0] = 0x00000000;
|
||||
CONTINUE
|
||||
case 020: /* COP0 */
|
||||
rd = (inst & 0x0000F800u) >> 11;
|
||||
rs = (inst >> 21) & 31;
|
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rt = (inst >> 16) & 31;
|
||||
switch (rs)
|
||||
{
|
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case 000: /* MFC0 */
|
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MFC0(rt, rd & 0xF);
|
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CONTINUE
|
||||
case 004: /* MTC0 */
|
||||
MTC0[rd & 0xF](rt);
|
||||
CONTINUE
|
||||
default:
|
||||
res_S();
|
||||
CONTINUE
|
||||
}
|
||||
CONTINUE
|
||||
case 022: /* COP2 */
|
||||
rd = (inst & 0x0000F800u) >> 11;
|
||||
rs = (inst >> 21) & 31;
|
||||
rt = (inst >> 16) & 31;
|
||||
switch (rs)
|
||||
{
|
||||
case 000: /* MFC2 */
|
||||
MFC2(rt, rd, element);
|
||||
CONTINUE
|
||||
case 002: /* CFC2 */
|
||||
CFC2(rt, rd);
|
||||
CONTINUE
|
||||
case 004: /* MTC2 */
|
||||
MTC2(rt, rd, element);
|
||||
CONTINUE
|
||||
case 006: /* CTC2 */
|
||||
CTC2(rt, rd);
|
||||
CONTINUE
|
||||
default:
|
||||
res_S();
|
||||
CONTINUE
|
||||
}
|
||||
CONTINUE
|
||||
case 040: /* LB */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst);
|
||||
addr = (SR[base = (inst >> 21) & 31] + offset) & 0x00000FFF;
|
||||
SR[rt] = RSP.DMEM[BES(addr)];
|
||||
SR[rt] = (signed char)(SR[rt]);
|
||||
SR[0] = 0x00000000;
|
||||
CONTINUE
|
||||
case 041: /* LH */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst);
|
||||
addr = (SR[base = (inst >> 21) & 31] + offset) & 0x00000FFF;
|
||||
if (addr%0x004 == 0x003)
|
||||
{
|
||||
SR_B(rt, 2) = RSP.DMEM[addr - BES(0x000)];
|
||||
addr = (addr + 0x00000001) & 0x00000FFF;
|
||||
SR_B(rt, 3) = RSP.DMEM[addr + BES(0x000)];
|
||||
SR[rt] = (signed short)(SR[rt]);
|
||||
}
|
||||
else
|
||||
{
|
||||
addr -= HES(0x000)*(addr%0x004 - 1);
|
||||
SR[rt] = *(signed short *)(RSP.DMEM + addr);
|
||||
}
|
||||
SR[0] = 0x00000000;
|
||||
CONTINUE
|
||||
case 043: /* LW */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst);
|
||||
addr = (SR[base = (inst >> 21) & 31] + offset) & 0x00000FFF;
|
||||
if (addr%0x004 != 0x000)
|
||||
ULW(rt, addr);
|
||||
else
|
||||
SR[rt] = *(int32_t *)(RSP.DMEM + addr);
|
||||
SR[0] = 0x00000000;
|
||||
CONTINUE
|
||||
case 044: /* LBU */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst);
|
||||
addr = (SR[base = (inst >> 21) & 31] + offset) & 0x00000FFF;
|
||||
SR[rt] = RSP.DMEM[BES(addr)];
|
||||
SR[rt] = (unsigned char)(SR[rt]);
|
||||
SR[0] = 0x00000000;
|
||||
CONTINUE
|
||||
case 045: /* LHU */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst);
|
||||
addr = (SR[base = (inst >> 21) & 31] + offset) & 0x00000FFF;
|
||||
if (addr%0x004 == 0x003)
|
||||
{
|
||||
SR_B(rt, 2) = RSP.DMEM[addr - BES(0x000)];
|
||||
addr = (addr + 0x00000001) & 0x00000FFF;
|
||||
SR_B(rt, 3) = RSP.DMEM[addr + BES(0x000)];
|
||||
SR[rt] = (unsigned short)(SR[rt]);
|
||||
}
|
||||
else
|
||||
{
|
||||
addr -= HES(0x000)*(addr%0x004 - 1);
|
||||
SR[rt] = *(unsigned short *)(RSP.DMEM + addr);
|
||||
}
|
||||
SR[0] = 0x00000000;
|
||||
CONTINUE
|
||||
case 050: /* SB */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst);
|
||||
addr = (SR[base = (inst >> 21) & 31] + offset) & 0x00000FFF;
|
||||
RSP.DMEM[BES(addr)] = (unsigned char)(SR[rt]);
|
||||
CONTINUE
|
||||
case 051: /* SH */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst);
|
||||
addr = (SR[base = (inst >> 21) & 31] + offset) & 0x00000FFF;
|
||||
if (addr%0x004 == 0x003)
|
||||
{
|
||||
RSP.DMEM[addr - BES(0x000)] = SR_B(rt, 2);
|
||||
addr = (addr + 0x00000001) & 0x00000FFF;
|
||||
RSP.DMEM[addr + BES(0x000)] = SR_B(rt, 3);
|
||||
CONTINUE
|
||||
}
|
||||
addr -= HES(0x000)*(addr%0x004 - 1);
|
||||
*(short *)(RSP.DMEM + addr) = (short)(SR[rt]);
|
||||
CONTINUE
|
||||
case 053: /* SW */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst);
|
||||
addr = (SR[base = (inst >> 21) & 31] + offset) & 0x00000FFF;
|
||||
if (addr%0x004 != 0x000)
|
||||
USW(rt, addr);
|
||||
else
|
||||
*(int32_t *)(RSP.DMEM + addr) = SR[rt];
|
||||
CONTINUE
|
||||
case 062: /* LWC2 */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst & 0x0000FFFFu);
|
||||
#if defined(ARCH_MIN_SSE2)
|
||||
offset <<= 5 + 4; /* safe on x86, skips 5-bit rd, 4-bit element */
|
||||
offset >>= 5 + 4;
|
||||
#else
|
||||
offset = SE(offset, 6);
|
||||
#endif
|
||||
base = (inst >> 21) & 31;
|
||||
LWC2_op[rd = (inst & 0xF800u) >> 11](rt, element, offset, base);
|
||||
CONTINUE
|
||||
case 072: /* SWC2 */
|
||||
rt = (inst >> 16) % (1 << 5);
|
||||
offset = (signed short)(inst & 0x0000FFFFu);
|
||||
#if defined(ARCH_MIN_SSE2)
|
||||
offset <<= 5 + 4; /* safe on x86, skips 5-bit rd, 4-bit element */
|
||||
offset >>= 5 + 4;
|
||||
#else
|
||||
offset = SE(offset, 6);
|
||||
#endif
|
||||
base = (inst >> 21) & 31;
|
||||
SWC2_op[rd = (inst & 0xF800u) >> 11](rt, element, offset, base);
|
||||
CONTINUE
|
||||
default:
|
||||
res_S();
|
||||
CONTINUE
|
||||
}
|
||||
}
|
||||
#ifndef EMULATE_STATIC_PC
|
||||
if (stage == 2) /* branch phase of scheduler */
|
||||
{
|
||||
stage = 0*stage;
|
||||
PC = temp_PC & 0x00000FFC;
|
||||
*RSP.SP_PC_REG = temp_PC;
|
||||
}
|
||||
else
|
||||
{
|
||||
stage = 2*stage; /* next IW in branch delay slot? */
|
||||
PC = (PC + 0x004) & 0xFFC;
|
||||
*RSP.SP_PC_REG = 0x04001000 + PC;
|
||||
}
|
||||
continue;
|
||||
#else
|
||||
continue;
|
||||
BRANCH:
|
||||
inst = *(uint32_t *)(RSP.IMEM + FIT_IMEM(PC));
|
||||
PC = temp_PC & 0x00000FFC;
|
||||
goto EX;
|
||||
#endif
|
||||
}
|
||||
*RSP.SP_PC_REG = 0x04001000 | FIT_IMEM(PC);
|
||||
if (*RSP.SP_STATUS_REG & 0x00000002) /* normal exit, from executing BREAK */
|
||||
return;
|
||||
else if (*RSP.MI_INTR_REG & 0x00000001) /* interrupt set by MTC0 to break */
|
||||
RSP.CheckInterrupts();
|
||||
else if (*RSP.SP_SEMAPHORE_REG != 0x00000000) /* semaphore lock fixes */
|
||||
{}
|
||||
#ifndef WAIT_FOR_CPU_HOST
|
||||
else /* ??? unknown, possibly external intervention from CPU memory map */
|
||||
return; /* SP_SET_HALT */
|
||||
#endif
|
||||
*RSP.SP_STATUS_REG &= ~0x00000001; /* CPU restarts with the correct SIGs. */
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -14,8 +14,6 @@
|
||||
#ifndef _RSP_H_
|
||||
#define _RSP_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "Rsp_#1.1.h"
|
||||
RSP_INFO RSP;
|
||||
|
||||
#ifdef _MSC_VER
|
||||
@ -73,11 +71,4 @@ static short MFC0_count[32];
|
||||
/* Keep one C0 MF status read count for each scalar register. */
|
||||
#endif
|
||||
|
||||
#include "su.h"
|
||||
#include "vu/vu.h"
|
||||
|
||||
/* Allocate the RSP CPU loop to its own functional space. */
|
||||
NOINLINE extern void run_task(void);
|
||||
#include "execute.h"
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user