mirror of
https://github.com/libretro/parallel-n64.git
synced 2025-03-01 05:05:49 +00:00
Ifdef out intense debug stuff in cxd4.
This commit is contained in:
Tiny Tiger
twinaphex
parent
2d6a113a04
commit
ce1d6f3d29
@ -36,6 +36,24 @@ unsigned char rsp_conf[32];
|
||||
#define CONFIG_API_VERSION 0x020100
|
||||
#define CONFIG_PARAM_VERSION 1.00
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
// Need super-fast hash here.
|
||||
static uint64_t hash_imem(const uint8_t *data, size_t size)
|
||||
{
|
||||
uint64_t h = 0xcbf29ce484222325ull;
|
||||
size_t i;
|
||||
for (i = 0; i < size; i++)
|
||||
h = (h * 0x100000001b3ull) ^ data[i];
|
||||
return h;
|
||||
}
|
||||
|
||||
void log_rsp_mem(void)
|
||||
{
|
||||
fprintf(stderr, "IMEM HASH: 0x%016llx\n", hash_imem(RSP.IMEM, 0x1000));
|
||||
fprintf(stderr, "DMEM HASH: 0x%016llx\n", hash_imem(RSP.DMEM, 0x1000));
|
||||
}
|
||||
#endif
|
||||
|
||||
static void (*l_DebugCallback)(void *, int, const char *) = NULL;
|
||||
static void *l_DebugCallContext = NULL;
|
||||
static int l_PluginInit = 0;
|
||||
@ -88,23 +106,32 @@ static INLINE unsigned SPECIAL(uint32_t inst, uint32_t PC)
|
||||
SR[rd] = (PC + LINK_OFF) & 0x00000FFC;
|
||||
SR[0] = 0x00000000;
|
||||
SET_PC(SR[rs = inst >> 21]);
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
{
|
||||
uint64_t hash = hash_imem((const uint8_t*)VR, sizeof(VR));
|
||||
fprintf(stderr, "JR (PC: %u): 0, %llu\n", temp_PC & 0xfff, hash);
|
||||
}
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
case 010: /* JR */
|
||||
SET_PC(SR[rs = inst >> 21]);
|
||||
#ifdef INTENSE_DEBUG
|
||||
{
|
||||
uint64_t hash = hash_imem((const uint8_t*)VR, sizeof(VR));
|
||||
fprintf(stderr, "JR (PC: %u): 0, %llu\n", temp_PC & 0xfff, hash);
|
||||
}
|
||||
#endif
|
||||
return 1;
|
||||
case 015: /* BREAK */
|
||||
*RSP.SP_STATUS_REG |= SP_STATUS_BROKE | SP_STATUS_HALT;
|
||||
if (*RSP.SP_STATUS_REG & SP_STATUS_INTR_BREAK)
|
||||
{ /* SP_STATUS_INTR_BREAK */
|
||||
*RSP.MI_INTR_REG |= 0x00000001;
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "CHECK IRQ\n");
|
||||
#endif
|
||||
RSP.CheckInterrupts();
|
||||
}
|
||||
break;
|
||||
@ -202,10 +229,12 @@ static unsigned int run_task_opcode(uint32_t inst, const int opcode)
|
||||
case 003: /* JAL */
|
||||
SR[31] = (PC + LINK_OFF) & 0x00000FFC;
|
||||
SET_PC(4*inst);
|
||||
#ifdef INTENSE_DEBUG
|
||||
{
|
||||
uint64_t hash = hash_imem((const uint8_t*)VR, sizeof(VR));
|
||||
fprintf(stderr, "JAL (PC: %u): 0, %llu\n", temp_PC & 0xfff, hash);
|
||||
}
|
||||
#endif
|
||||
return 1;
|
||||
|
||||
case 002: /* J */
|
||||
@ -306,10 +335,12 @@ static unsigned int run_task_opcode(uint32_t inst, const int opcode)
|
||||
break;
|
||||
case 004: /* MTC2 */
|
||||
MTC2(rt, rd, element);
|
||||
#ifdef INTENSE_DEBUG
|
||||
{
|
||||
uint64_t hash = hash_imem((const uint8_t*)VR, sizeof(VR));
|
||||
fprintf(stderr, "MTC2 (PC: %u): 0, %llu\n", 0, hash);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
case 006: /* CTC2 */
|
||||
CTC2(rt, rd);
|
||||
@ -421,11 +452,13 @@ static unsigned int run_task_opcode(uint32_t inst, const int opcode)
|
||||
base = (inst >> 21) & 31;
|
||||
LWC2_op[rd = (inst & 0xF800u) >> 11](rt, element, offset, base);
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
{
|
||||
uint64_t hash = hash_imem((const uint8_t*)VR, sizeof(VR));
|
||||
fprintf(stderr, "LWC2 (PC: %u): %u, %llu\n", CPC + 4, inst, hash);
|
||||
fprintf(stderr, " DMEM HASH: 0x%016llx\n", hash_imem(RSP.DMEM, 0x1000));
|
||||
}
|
||||
#endif
|
||||
|
||||
break;
|
||||
case 072: /* SWC2 */
|
||||
@ -440,11 +473,13 @@ static unsigned int run_task_opcode(uint32_t inst, const int opcode)
|
||||
base = (inst >> 21) & 31;
|
||||
SWC2_op[rd = (inst & 0xF800u) >> 11](rt, element, offset, base);
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
{
|
||||
uint64_t hash = hash_imem((const uint8_t*)VR, sizeof(VR));
|
||||
fprintf(stderr, "SWC2 (PC: %u): %u, %llu\n", CPC + 4, inst, hash);
|
||||
fprintf(stderr, " DMEM HASH: 0x%016llx\n", hash_imem(RSP.DMEM, 0x1000));
|
||||
}
|
||||
#endif
|
||||
|
||||
break;
|
||||
default:
|
||||
@ -458,6 +493,11 @@ NOINLINE void run_task(void)
|
||||
{
|
||||
PC = FIT_IMEM(*RSP.SP_PC_REG);
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "RUN TASK: %u\n", PC);
|
||||
log_rsp_mem();
|
||||
#endif
|
||||
|
||||
stale_signals = 0;
|
||||
|
||||
#ifdef HAVE_RSP_DUMP
|
||||
@ -500,10 +540,12 @@ EX:
|
||||
const int e = (inst >> 21) & 0xF; /* rs & 0xF */
|
||||
|
||||
COP2_C2[opcode](vd, vs, vt, e);
|
||||
#ifdef INTENSE_DEBUG
|
||||
{
|
||||
uint64_t hash = hash_imem((const uint8_t*)VR, sizeof(VR));
|
||||
fprintf(stderr, "CP2 (PC: %u): 0, %llu\n", opcode, hash);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else if (run_task_opcode(inst, inst >> 26))
|
||||
{
|
||||
@ -697,6 +739,10 @@ EXPORT unsigned int CALL cxd4DoRspCycles(unsigned int cycles)
|
||||
if (*RSP.SP_STATUS_REG & SP_STATUS_BROKE) /* normal exit, from executing BREAK */
|
||||
return (cycles);
|
||||
else if (*RSP.MI_INTR_REG & 0x00000001) /* interrupt set by MTC0 to break */
|
||||
{
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "CHECK IRQ\n");
|
||||
#endif
|
||||
RSP.CheckInterrupts();
|
||||
else if (*RSP.SP_SEMAPHORE_REG != 0x00000000) /* semaphore lock fixes */
|
||||
{}
|
||||
|
||||
@ -136,6 +136,11 @@ static void MT_DMA_DRAM(int rt)
|
||||
*RSP.SP_DRAM_ADDR_REG = SR[rt] & 0xFFFFFFF8; /* & 0x00FFFFF8 */
|
||||
/* Let the reserved bits get sent, but the pointer is 24-bit. */
|
||||
}
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
void log_rsp_mem(void);
|
||||
#endif
|
||||
|
||||
static void MT_DMA_READ_LENGTH(int rt)
|
||||
{
|
||||
unsigned int offC, offD; /* SP cache and dynamic DMA pointers */
|
||||
@ -152,6 +157,14 @@ static void MT_DMA_READ_LENGTH(int rt)
|
||||
|
||||
++length;
|
||||
++count;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "DMA READ: (0x%x <- 0x%x) len %u, count %u, skip %u\n",
|
||||
*RSP.SP_MEM_ADDR_REG,
|
||||
*RSP.SP_DRAM_ADDR_REG,
|
||||
length, count, skip);
|
||||
#endif
|
||||
|
||||
skip += length;
|
||||
do
|
||||
{ /* `count` always starts > 0, so we begin with `do` instead of `while`. */
|
||||
@ -184,6 +197,10 @@ static void MT_DMA_READ_LENGTH(int rt)
|
||||
#ifdef HAVE_RSP_DUMP
|
||||
rsp_dump_end_read_dma();
|
||||
#endif
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
log_rsp_mem();
|
||||
#endif
|
||||
}
|
||||
static void MT_DMA_WRITE_LENGTH(int rt)
|
||||
{
|
||||
@ -197,6 +214,16 @@ static void MT_DMA_WRITE_LENGTH(int rt)
|
||||
/* length |= 07; // already corrected by mtc0 */
|
||||
++length;
|
||||
++count;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "DMA WRITE: (0x%x <- 0x%x) len %u, count %u, skip %u\n",
|
||||
*RSP.SP_DRAM_ADDR_REG,
|
||||
*RSP.SP_MEM_ADDR_REG,
|
||||
length, count, skip);
|
||||
#endif
|
||||
|
||||
unsigned src = *RSP.SP_MEM_ADDR_REG;
|
||||
|
||||
skip += length;
|
||||
do
|
||||
{ /* `count` always starts > 0, so we begin with `do` instead of `while`. */
|
||||
@ -217,6 +244,10 @@ static void MT_DMA_WRITE_LENGTH(int rt)
|
||||
*RSP.SP_DMA_BUSY_REG = 0x00000000;
|
||||
*RSP.SP_STATUS_REG &= ~SP_STATUS_DMA_BUSY;
|
||||
}
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
log_rsp_mem();
|
||||
#endif
|
||||
}
|
||||
static void MT_SP_STATUS(int rt)
|
||||
{
|
||||
@ -266,6 +297,9 @@ static void MT_CMD_START(int rt)
|
||||
message("MTC0\nCMD_START", 0);
|
||||
#endif
|
||||
*RSP.DPC_END_REG = *RSP.DPC_CURRENT_REG = *RSP.DPC_START_REG = source;
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "CMD_START 0x%x\n", source);
|
||||
#endif
|
||||
}
|
||||
static void MT_CMD_END(int rt)
|
||||
{
|
||||
@ -276,6 +310,9 @@ static void MT_CMD_END(int rt)
|
||||
*RSP.DPC_END_REG = SR[rt] & 0xFFFFFFF8;
|
||||
if (RSP.ProcessRdpList == NULL) /* zilmar GFX #1.2 */
|
||||
return;
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "CMD_END 0x%x\n", *RSP.DPC_END_REG);
|
||||
#endif
|
||||
RSP.ProcessRdpList();
|
||||
}
|
||||
static void MT_CMD_STATUS(int rt)
|
||||
@ -414,8 +451,10 @@ static void MFC2(int rt, int vs, int e)
|
||||
|
||||
static void MTC2(int rt, int vd, int e)
|
||||
{
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "MTC2, rt = %u, [rt] = 0x%x, rd = %u, e = %u\n",
|
||||
rt, SR[rt], vd, e);
|
||||
#endif
|
||||
|
||||
VR_B(vd, e+0x0) = SR_B(rt, 2);
|
||||
VR_B(vd, e+0x1) = SR_B(rt, 3);
|
||||
@ -572,6 +611,12 @@ static void SBV(int vt, int element, int offset, int base)
|
||||
{
|
||||
const unsigned int e = element;
|
||||
register uint32_t addr = (SR[base] + 1*offset) & 0x00000FFF;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "SBV: 0x%x (0x%x)\n", addr,
|
||||
VR_B(vt, (e + 0x0)));
|
||||
#endif
|
||||
|
||||
RSP.DMEM[BES(addr)] = VR_B(vt, e);
|
||||
}
|
||||
|
||||
@ -579,6 +624,12 @@ static void SSV(int vt, int element, int offset, int base)
|
||||
{
|
||||
const unsigned int e = element;
|
||||
register uint32_t addr = (SR[base] + 2*offset) & 0x00000FFF;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "SSV: 0x%x (0x%x, 0x%x)\n", addr,
|
||||
VR_B(vt, (e + 0x0)), VR_B(vt, (e + 0x1) & 0xf));
|
||||
#endif
|
||||
|
||||
RSP.DMEM[BES(addr)] = VR_B(vt, (e + 0x0));
|
||||
addr = (addr + 0x00000001) & 0x00000FFF;
|
||||
RSP.DMEM[BES(addr)] = VR_B(vt, (e + 0x1) & 0xF);
|
||||
@ -596,6 +647,10 @@ static void SLV(int vt, int element, int offset, int base)
|
||||
return;
|
||||
}
|
||||
addr = (SR[base] + 4*offset) & 0x00000FFF;
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "SLV 0x%x, e = %u\n", addr, e);
|
||||
#endif
|
||||
|
||||
if (addr & 0x00000001)
|
||||
{
|
||||
message("SLV\nOdd addr.", 3);
|
||||
@ -613,6 +668,10 @@ static void SDV(int vt, int element, int offset, int base)
|
||||
const int e = element;
|
||||
|
||||
addr = (SR[base] + 8*offset) & 0x00000FFF;
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "SDV 0x%x, e = %u\n", addr, e);
|
||||
#endif
|
||||
|
||||
if (e > 0x8 || (e & 0x1))
|
||||
{ /* Illegal elements with Boss Game Studios publications. */
|
||||
register int i;
|
||||
@ -1186,7 +1245,9 @@ static void LQV(int vt, int element, int offset, int base)
|
||||
}
|
||||
addr = (SR[base] + 16*offset) & 0x00000FFF;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
fprintf(stderr, "LQV: 0x%x, e = %u, vt = %u, base = %u\n", addr, element, vt, base);
|
||||
#endif
|
||||
|
||||
if (addr & 0x00000001)
|
||||
{
|
||||
|
||||
@ -20,10 +20,12 @@ INLINE static void do_cr(short* VD, short* VS, short* VT)
|
||||
short cmp[N];
|
||||
register int i;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "VS[%d] = %d\n", i, VS[i]);
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "VT[%d] = %d\n", i, VT[i]);
|
||||
#endif
|
||||
|
||||
for (i = 0; i < N; i++)
|
||||
VC[i] = VT[i];
|
||||
@ -62,8 +64,10 @@ INLINE static void do_cr(short* VD, short* VS, short* VT)
|
||||
for (i = 0; i < N; i++)
|
||||
vce[i] = 0;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "VD[%d] = %d\n", i, VD[i]);
|
||||
#endif
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
|
||||
INLINE static void do_madn(short* VD, short* VS, short* VT)
|
||||
{
|
||||
#ifdef INTENSE_DEBUG
|
||||
unsigned i;
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "ACC LO[%u] = %d\n", i, VACC_L[i]);
|
||||
@ -26,6 +27,7 @@ INLINE static void do_madn(short* VD, short* VS, short* VT)
|
||||
fprintf(stderr, "VS[%u] = %d\n", i, VS[i]);
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "VT[%u] = %d\n", i, VT[i]);
|
||||
#endif
|
||||
|
||||
#ifdef ARCH_MIN_SSE2
|
||||
__m128i acc_hi, acc_md, acc_lo;
|
||||
@ -88,8 +90,10 @@ INLINE static void do_madn(short* VD, short* VS, short* VT)
|
||||
vs = _mm_xor_si128(vs, acc_md); /* Stupid unsigned-clamp-ish adjustment. */
|
||||
|
||||
_mm_storeu_si128((__m128i *)VD, vs);
|
||||
#ifdef INTENSE_DEBUG
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "VD[%u] = %d\n", i, VD[i]);
|
||||
#endif
|
||||
#else
|
||||
uint32_t addend[N];
|
||||
register int i;
|
||||
|
||||
@ -17,10 +17,12 @@ INLINE static void do_ne(short* VD, short* VS, short* VT)
|
||||
{
|
||||
register int i;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "VS[%d] = %d\n", i, VS[i]);
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "VT[%d] = %d\n", i, VT[i]);
|
||||
#endif
|
||||
|
||||
for (i = 0; i < N; i++)
|
||||
clip[i] = 0;
|
||||
@ -40,8 +42,10 @@ INLINE static void do_ne(short* VD, short* VS, short* VT)
|
||||
for (i = 0; i < N; i++)
|
||||
co[i] = 0;
|
||||
|
||||
#ifdef INTENSE_DEBUG
|
||||
for (i = 0; i < 8; i++)
|
||||
fprintf(stderr, "VD[%d] = %d\n", i, VD[i]);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user