2 Commits
Author SHA1 Message Date
libretroadmin 8c6acaddab GIF: the DMA channel, its FIFO and the MFIFO in C89
Gif.c is the GIF DMA channel, its 16-quadword FIFO, the MFIFO drain and
the GIF registers in C89. The FIFO is a plain struct with
gif_fifo_init/write/read, the GIF unit is reached through the
gif_unit_* and gif_path_* glue in Gif_Unit.cpp (Gif_hw.h), the GIF FIFO
hack through emu_config_giffifo_hack, and the GS CSR accessors and FIFO
states move from GS.h into GSmmio.h so C reaches them.

Normal and non-ring MFIFO transfers now stop at the end of one
contiguous run of mapped memory, and an MFIFO tag at an unmapped
address raises the bus error and stops the channel instead of being
read through NULL. tests/eegif checks the channel against the previous
C++ and covers both fixes.
2026-11-09 08:22:50 +01:00
libretroadmin f15d2b83c9 EE hardware: the register handlers and the DMAC in C89
Hw.cpp and Dmac.cpp become C. The register handlers were templates on
the page; they are now page-taking workers that each per-page handler
calls with a constant, so each still reduces to its own page's arm, and
Hw.c hands the vtlb the sets it registered before. The units still in
C++ are reached through C-linkage entry points: FIFOs, counters, IPU,
VIF register wrappers, GS and VU resets, the gamefix accessors, and the
GIF's register writes, OPH read hack, reset and MFIFO hand-off, which
move to Gif.cpp. IPU/IPU_hw.h is the IPU's C face; Vif_Unpack.h and
Vif_Dma.h read as C. MemCopy_WrappedDest and the std templates in this
path are gone.

The MFIFO write now refuses a ring that does not lie in one run of host
memory, as one running past the end of main RAM does, instead of
copying past the mapping. tests/eehw drives every page's handlers
through the vtlb registration against the transcript the C++ made, and
checks the MFIFO bound and the reset order. tests/vu's VU EFU lane links
again (gifPathReadAmount).
2026-11-09 05:50:35 +01:00