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https://github.com/libretro/parallel-ps2.git
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libretroadmin
80c1251d80
SPR.cpp becomes C. Hw.cpp's MFIFO entry points and vucpu_execute_block get C linkage, THREAD_VU1 is asked through emu_config_thread_vu1(), and VU.h and VUmicro.h lose their // comments, which a C89 lane read into vu1RunCycles. Copies between the scratchpad and memory now stay inside what they address: a run past the end of main RAM reads on from the zero source, one through VU0's 4 KiB windows mirrors instead of running into VU1, the scratchpad's own window wraps, the scratchpad copied onto itself goes front to back, interleave transfers to or from a bus error no longer copy through NULL, and a source-chain tag at a bus error raises BEIS and stops the channel instead of being read through NULL. tests/eespr replays both channels against the transcript the C++ made and checks each of these.
641 lines
24 KiB
C++
641 lines
24 KiB
C++
/* EE integer ops against console captures, driving the real code.
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*
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* tests/ee/hwalu.c and hwload.c and hwstore.c transcribe the semantics
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* out of pcsx2/R5900OpcodeImpl.cpp and score the copy, which catches a
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* wrong answer but not drift. This links that file and calls the ops
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* through their real entry points, building the instruction word so the
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* _Rd_, _Rs_, _Rt_, _Sa_ and _Imm_ macros decode what the harness
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* intends.
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*
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* Its dependencies are stubbed rather than pulled in. Most are inert --
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* the BIOS hacks, the savestate helpers, the COP2 print table -- but the
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* vtlb accessors are backed by a real array, so the loads and stores
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* execute against memory rather than being skipped. That is what lets
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* the same harness cover alu.expected and lsu.expected.
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*
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* Three tables of ops, by shape:
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* RRR rd = f(rs, rt) -- the register arithmetic
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* RRI rt = f(rs, immediate) -- the immediate forms
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* RRS rd = f(rt, sa) -- shift by immediate
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*
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* The load and store blocks reuse the same memory pattern the standalone
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* scorers do, at the same two bases: the load harness bases at byte 16
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* of the pattern and the store harness at byte 4, which is not a typo
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* but a difference between the two test programs.
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*
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* Usage: tests/ee/hwrealee <dir-with-the-.expected-files>
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "Common.h"
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#include "R5900.h"
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#include "R5900OpcodeTables.h"
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#include "GS.h"
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#include "ps2/BiosTools.h"
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alignas(16) cpuRegisters cpuRegs;
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/* ---- stubs ------------------------------------------------------------
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* Everything R5900OpcodeImpl.cpp reaches for that this harness does not
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* exercise. The memory accessors are real; the rest are inert. */
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#define MEMSIZE 4096
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static u8 s_mem[MEMSIZE];
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static u32 clampaddr(u32 a) { return a & (MEMSIZE - 1); }
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u8 vtlb_memRead8 (u32 a) { return s_mem[clampaddr(a)]; }
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u16 vtlb_memRead16(u32 a) { u16 v; memcpy(&v, s_mem + clampaddr(a), 2); return v; }
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u32 vtlb_memRead32(u32 a) { u32 v; memcpy(&v, s_mem + clampaddr(a), 4); return v; }
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u64 vtlb_memRead64(u32 a) { u64 v; memcpy(&v, s_mem + clampaddr(a), 8); return v; }
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void vtlb_memWrite8 (u32 a, u8 v) { s_mem[clampaddr(a)] = v; }
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void vtlb_memWrite16(u32 a, u16 v) { memcpy(s_mem + clampaddr(a), &v, 2); }
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void vtlb_memWrite32(u32 a, u32 v) { memcpy(s_mem + clampaddr(a), &v, 4); }
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void vtlb_memWrite64(u32 a, u64 v) { memcpy(s_mem + clampaddr(a), &v, 8); }
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void* vtlb_GetPhyPtr(u32 a) { return s_mem + clampaddr(a); }
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RETURNS_R128 vtlb_memRead128(u32 a)
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{
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r128 v;
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memcpy(&v, s_mem + clampaddr(a), 16);
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return v;
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}
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void vtlb_memWrite128(u32 a, r128 v) { memcpy(s_mem + clampaddr(a), &v, 16); }
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/* Inert stubs: nothing here runs a BIOS, a savestate or the GS. */
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bool g_SkipBiosHack = false, AllowParams1 = false, AllowParams2 = false, NoOSD = false;
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void cpuException(u32, u32) { }
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/* Cpu is only reached by the misaligned-access paths, which call
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* CancelInstruction; the captures never take one. */
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static void nop_v() { }
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static void nop_u32(u32) { }
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static void nop_u32_u32(u32, u32) { }
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/* Set when an op takes its misaligned-address path. The captures use
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* aligned addresses, so this firing means the harness set up the address
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* wrongly -- it is recorded rather than ignored, and never null, because a
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* null CancelInstruction turns that mistake into a segfault. */
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static int s_cancelled;
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static void harness_cancel() { s_cancelled = 1; }
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static R5900cpu s_cpu = {};
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R5900cpu* Cpu = &s_cpu;
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static struct cpu_init_t { cpu_init_t() { s_cpu.CancelInstruction = harness_cancel; } } s_cpu_init;
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BiosDebugInformation CurrentBiosInformation = {};
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/* Referenced by inline helpers in GS.h and Dmac.h; only needed when the
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* compiler does not elide them, which -O0 does not. */
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alignas(16) u8 g_RealGSMem[0x2000];
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alignas(16) u8 eeHw[0x10000];
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void gsSetVideoMode(GS_VideoMode) { }
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extern "C" void cdvdReadLanguageParams(u8*) { }
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tDMA_TAG* dmaGetAddr(u32, bool) { return (tDMA_TAG*)s_mem; }
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void SaveState_FreezeMem(SaveStateBase*, void*, int) { }
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bool SaveState_FreezeTag(SaveStateBase*, const char*) { return true; }
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/* ---- the harness ------------------------------------------------------ */
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namespace R5900 { namespace Interpreter { namespace OpcodeImpl {
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void ADDU(); void SUBU(); void AND(); void OR(); void XOR(); void NOR();
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void SLT(); void SLTU(); void DADDU(); void DSUBU();
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void MOVN(); void MOVZ();
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void SLLV(); void SRLV(); void SRAV();
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void DSLLV(); void DSRLV(); void DSRAV();
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void ADDIU(); void ANDI(); void DADDIU(); void ORI(); void XORI();
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void SLTI(); void SLTIU(); void LUI();
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void SLL(); void SRL(); void SRA();
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void DSLL(); void DSRL(); void DSRA();
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void DSLL32(); void DSRL32(); void DSRA32();
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void LB(); void LBU(); void LH(); void LHU(); void LW(); void LWU();
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void LD(); void LQ(); void LWL(); void LWR(); void LDL(); void LDR();
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void SB(); void SH(); void SW(); void SD(); void SQ();
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void SWL(); void SWR(); void SDL(); void SDR();
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void DIV(); void DIVU(); void MULT(); void MULTU();
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void MFHI(); void MFLO(); void MTHI(); void MTLO();
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} } }
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using namespace R5900::Interpreter::OpcodeImpl;
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/* HILO_MOVE: one operand, and the result is a pipeline register or rd
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* depending on the direction. */
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enum Shape { RRR, RRI, RRS, RI, LOAD, STORE, MULDIV, HILO_MOVE };
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static const struct { const char* name; void (*fn)(); Shape shape; int swap; }
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kOps[] = {
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{ "addu",ADDU,RRR,0 },{ "subu",SUBU,RRR,0 },{ "and",AND,RRR,0 },
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{ "or",OR,RRR,0 },{ "xor",XOR,RRR,0 },{ "nor",NOR,RRR,0 },
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{ "slt",SLT,RRR,0 },{ "sltu",SLTU,RRR,0 },
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{ "daddu",DADDU,RRR,0 },{ "dsubu",DSUBU,RRR,0 },
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{ "movn",MOVN,RRR,0 },{ "movz",MOVZ,RRR,0 },
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/* The variable shifts assemble as rd, rt, rs -- value first, amount
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* second -- so the printed operands go in swapped. */
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{ "sllv",SLLV,RRR,1 },{ "srlv",SRLV,RRR,1 },{ "srav",SRAV,RRR,1 },
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{ "dsllv",DSLLV,RRR,1 },{ "dsrlv",DSRLV,RRR,1 },{ "dsrav",DSRAV,RRR,1 },
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{ "addiu",ADDIU,RRI,0 },{ "andi",ANDI,RRI,0 },{ "daddiu",DADDIU,RRI,0 },
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{ "ori",ORI,RRI,0 },{ "xori",XORI,RRI,0 },
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{ "slti",SLTI,RRI,0 },{ "sltiu",SLTIU,RRI,0 },
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{ "lui",LUI,RI,0 },
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{ "sll",SLL,RRS,0 },{ "srl",SRL,RRS,0 },{ "sra",SRA,RRS,0 },
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{ "dsll",DSLL,RRS,0 },{ "dsrl",DSRL,RRS,0 },{ "dsra",DSRA,RRS,0 },
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{ "dsll32",DSLL32,RRS,0 },{ "dsrl32",DSRL32,RRS,0 },{ "dsra32",DSRA32,RRS,0 },
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/* Loads and stores run against the backing array; the base register
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* holds the pattern's base and the offset comes from the line. */
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{ "lb",LB,LOAD,0 },{ "lbu",LBU,LOAD,0 },{ "lh",LH,LOAD,0 },
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{ "lhu",LHU,LOAD,0 },{ "lw",LW,LOAD,0 },{ "lwu",LWU,LOAD,0 },
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{ "ld",LD,LOAD,0 },{ "lq",LQ,LOAD,0 },
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{ "sb",SB,STORE,0 },{ "sh",SH,STORE,0 },{ "sw",SW,STORE,0 },
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{ "sd",SD,STORE,0 },{ "sq",SQ,STORE,0 },
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{ "div",DIV,MULDIV,0 },{ "divu",DIVU,MULDIV,0 },
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{ "mult",MULT,MULDIV,0 },{ "multu",MULTU,MULDIV,0 },
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/* The HI/LO moves. Nothing in the tree scored these either -- the
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* audit that turned up the second pipeline found them in the same
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* pass. */
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{ "mfhi",MFHI,HILO_MOVE,0 },{ "mflo",MFLO,HILO_MOVE,0 },
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{ "mthi",MTHI,HILO_MOVE,0 },{ "mtlo",MTLO,HILO_MOVE,0 },
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};
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/* C_PATTERN from the lsu harness, and the two bases its load and store
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* halves use -- byte 16 for loads, byte 4 for stores, which is a row index
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* against a flat word index rather than a mistake. */
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static const u32 kPattern[12] = {
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0x45678123u, 0x9ABCDEF0u, 0xDEADBEEFu, 0xC0DE1337u,
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0x23456789u, 0xABCDEF01u, 0xBEEFDEADu, 0xC0DEC0DEu,
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0x8899AABBu, 0xCCDDEEFFu, 0x00112233u, 0x44556677u,
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};
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#define LOAD_BASE 16
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/* The EE store harness bases at &buffer[1] of a u128 array, so byte 16 --
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* the same base its loads use. The IOP one bases at byte 4 because its
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* buffer is a flat u32 array; that difference cost a crash here, since SD
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* and SQ at byte 4 take their misaligned path. */
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#define STORE_BASE 16
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/* C_HILO, the seed the muldiv harness restores before each case. */
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#define HI0 0x0123456789ABCDEFull
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#define LO0 0x123456789ABCDEF0ull
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#define HI1 0x23456789ABCDEF01ull
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#define LO1 0x456789ABCDEF0123ull
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#define NOPS ((int)(sizeof(kOps)/sizeof(kOps[0])))
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#define RD 1
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#define RS 2
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#define RT 3
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typedef struct { u32 w[4]; } Q;
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static const struct { const char* name; Q v; } kConst[] = {
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{ "C_ZERO", {{0,0,0,0}} },
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{ "C_S16_MAX", {{0x7FFFu,0,0,0}} },
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{ "C_S16_MIN", {{0xFFFF8000u,0xFFFFFFFFu,0xFFFFFFFFu,0xFFFFFFFFu}} },
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{ "C_S32_MAX", {{0x7FFFFFFFu,0,0,0}} },
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{ "C_S32_MIN", {{0x80000000u,0xFFFFFFFFu,0xFFFFFFFFu,0xFFFFFFFFu}} },
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{ "C_S64_MAX", {{0xFFFFFFFFu,0x7FFFFFFFu,0,0}} },
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{ "C_S64_MIN", {{0,0x80000000u,0xFFFFFFFFu,0xFFFFFFFFu}} },
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{ "C_NEGONE", {{0xFFFFFFFFu,0xFFFFFFFFu,0xFFFFFFFFu,0xFFFFFFFFu}} },
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{ "C_ONE", {{1,0,0,0}} },
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{ "C_GARBAGE1", {{0x1337u,0x1338u,0x1339u,0x133Au}} },
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{ "C_GARBAGE2", {{0xDEADBEEFu,0xDEADBEEEu,0xDEADBEEDu,0xDEADBEECu}} },
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{ "C_TWOTWOTWOTWO", {{2u,2u,2u,2u}} },
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{ "C_ONEONEONEONE", {{1u,1u,1u,1u}} },
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};
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static int operand(char** pp, Q* out, int* named)
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{
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char* p = *pp;
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size_t i, best = (size_t)-1, bestlen = 0;
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while (*p == ' ' || *p == ',') p++;
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for (i = 0; i < sizeof(kConst)/sizeof(kConst[0]); i++)
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{
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const size_t n = strlen(kConst[i].name);
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if (!strncmp(p, kConst[i].name, n) && n > bestlen) { best = i; bestlen = n; }
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}
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if (best != (size_t)-1)
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{ *out = kConst[best].v; *named = 1; p += bestlen; *pp = p; return 1; }
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{
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char* e;
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long long v = strtoll(p, &e, 10);
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if (e == p) return 0;
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/* SET_U32: lui/ori, so the low doubleword sign-extended, nothing above. */
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out->w[0] = (u32)v;
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out->w[1] = (v < 0) ? 0xFFFFFFFFu : 0u;
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out->w[2] = out->w[3] = 0;
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*named = 0;
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*pp = e;
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return 1;
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}
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}
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static void set_reg(int r, const Q* q)
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{
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cpuRegs.GPR.r[r].UL[0] = q->w[0]; cpuRegs.GPR.r[r].UL[1] = q->w[1];
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cpuRegs.GPR.r[r].UL[2] = q->w[2]; cpuRegs.GPR.r[r].UL[3] = q->w[3];
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}
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/* Case count for a block, so the store seed can switch at its midpoint.
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* Each store block runs its offsets twice, first from SET_U32<0xABCD4321>
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* and then from SET_M(C_GARBAGE1), and the number of offsets is not
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* constant -- three for the byte through doubleword stores, four for SQ.
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* Assuming three seeds the wrong half of the larger block. */
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static int count_block(const char* path, const char* name)
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{
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FILE* f = fopen(path, "r");
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char buf[512];
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int in = 0, n = 0;
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if (!f) return 0;
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while (fgets(buf, sizeof(buf), f))
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{
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if (buf[0] != ' ')
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{
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char* c = strchr(buf, ':');
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if (in) break;
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if (c && c[1] == '\n') { *c = '\0'; in = !strcmp(buf, name); *c = ':'; }
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continue;
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}
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if (!in || strstr(buf, "-> $0")) continue;
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n++;
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}
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fclose(f);
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return n;
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}
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/* Memory backing for the load and store blocks. */
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static void reset_pattern(void) { memcpy(s_mem, kPattern, sizeof(kPattern)); }
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/* Read "+0", "-16" or "+-16": the second half of each block prints a
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* negative offset through a "+%d" format, so the sign can follow the plus. */
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static int read_off(char** pp, int* out)
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{
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char* p = *pp;
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while (*p == ' ') p++;
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if (*p == '+') p++;
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if (*p != '-' && (*p < '0' || *p > '9')) return 0;
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*out = (int)strtol(p, &p, 10);
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*pp = p;
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return 1;
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}
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/* The load, store and multiply/divide blocks: different files, different
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* line shapes, and for the stores the result is memory rather than a
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* register. Returns 0 when the line is not a case. */
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static int run_special(int op, char* buf, int* cases, int* pass, int* failures,
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int block_total)
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{
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unsigned w3, w2, w1, w0;
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int off = 0;
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char* p;
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if (strstr(buf, "-> $0")) return 0;
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p = buf + 2;
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while (*p && *p != ' ') p++;
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if (kOps[op].shape == HILO_MOVE)
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{
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/* "mfhi <n>: <rd quad> H: hi hi1 L: lo lo1". The MF forms write rd
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* from a pipeline register and the MT forms write the pipeline from
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* rs, so both directions are covered by comparing rd and the
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* pipelines together -- which is also what tells a move from HI
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* apart from a move from LO. */
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unsigned long long wh, wh1, wl, wl1;
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unsigned q3, q2, q1, q0;
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Q rs_q;
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char* q = strstr(buf, "H: ");
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const int is_mt = kOps[op].name[1] == 't';
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if (!q) return 0;
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if (sscanf(q, "H: %llx %llx L: %llx %llx", &wh, &wh1, &wl, &wl1) != 4)
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return 0;
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{
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char* c = strchr(buf, ':');
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if (!c || sscanf(c + 2, "%x %x %x %x", &q3, &q2, &q1, &q0) != 4)
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return 0;
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/* Half these lines name a constant rather than a decimal --
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* "mthi C_NEGONE:" -- and strtol reads those as zero, which
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* makes the MT forms score 8 of 18 while looking like a
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* pipeline-write bug. operand() resolves both. */
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{
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char* ap = p;
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int dummy = 0;
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if (!operand(&ap, &rs_q, &dummy)) return 0;
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}
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}
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memset(&cpuRegs.GPR, 0, sizeof(cpuRegs.GPR));
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cpuRegs.HI.UD[0] = HI0; cpuRegs.HI.UD[1] = HI1;
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cpuRegs.LO.UD[0] = LO0; cpuRegs.LO.UD[1] = LO1;
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cpuRegs.GPR.r[RS].UL[0] = rs_q.w[0];
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cpuRegs.GPR.r[RS].UL[1] = rs_q.w[1];
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cpuRegs.GPR.r[RS].UL[2] = rs_q.w[2];
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cpuRegs.GPR.r[RS].UL[3] = rs_q.w[3];
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/* rd carries the same seed the ee/muldiv program leaves. */
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cpuRegs.GPR.r[RD].UD[1] = 0x0000133A00001339ull;
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cpuRegs.code = ((u32)RS << 21) | ((u32)RD << 11);
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kOps[op].fn();
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(*cases)++;
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{
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const int hilo_ok = cpuRegs.HI.UD[0] == wh && cpuRegs.HI.UD[1] == wh1
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&& cpuRegs.LO.UD[0] == wl && cpuRegs.LO.UD[1] == wl1;
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/* The MT forms leave rd alone, so only the pipelines are the
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* result there. */
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const int rd_ok = is_mt
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|| (cpuRegs.GPR.r[RD].UL[0] == q0
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&& cpuRegs.GPR.r[RD].UL[1] == q1);
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if (hilo_ok && rd_ok) (*pass)++;
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else if ((*failures)++ < 6)
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printf(" %-5s %d: console rd %08x %08x H %016llx %016llx\n"
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" ours rd %08x %08x H %016llx %016llx\n",
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kOps[op].name, (int)rs_q.w[0], q1, q0, wh, wh1,
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cpuRegs.GPR.r[RD].UL[1], cpuRegs.GPR.r[RD].UL[0],
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(unsigned long long)cpuRegs.HI.UD[0],
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(unsigned long long)cpuRegs.HI.UD[1]);
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}
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return 0;
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}
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if (kOps[op].shape == MULDIV)
|
|
{
|
|
u32 a, b;
|
|
unsigned long long wh, wh1, wl, wl1;
|
|
char* q = p;
|
|
int na = 0, nb = 0;
|
|
Q qa, qb;
|
|
if (!operand(&q, &qa, &na)) return 0;
|
|
if (!operand(&q, &qb, &nb)) return 0;
|
|
a = qa.w[0]; b = qb.w[0];
|
|
/* Anchor on the H: marker rather than the first colon. The
|
|
* multiply lines print rd between the two -- "mult a, b: <quad>
|
|
* H: ... L: ..." -- while the divide lines go straight to H:, so
|
|
* scanning from the colon parses div and drops every mult and
|
|
* multu line. They scored 0 of 0 and the run still passed. */
|
|
q = strstr(buf, "H: ");
|
|
if (!q || sscanf(q, "H: %llx %llx L: %llx %llx",
|
|
&wh, &wh1, &wl, &wl1) != 4) return 0;
|
|
|
|
cpuRegs.HI.UD[0] = HI0; cpuRegs.HI.UD[1] = HI1;
|
|
cpuRegs.LO.UD[0] = LO0; cpuRegs.LO.UD[1] = LO1;
|
|
cpuRegs.GPR.r[RS].UD[0] = (u64)(s64)(s32)a;
|
|
cpuRegs.GPR.r[RT].UD[0] = (u64)(s64)(s32)b;
|
|
cpuRegs.code = ((u32)RS << 21) | ((u32)RT << 16);
|
|
kOps[op].fn();
|
|
|
|
(*cases)++;
|
|
if (cpuRegs.HI.UD[0] == wh && cpuRegs.HI.UD[1] == wh1
|
|
&& cpuRegs.LO.UD[0] == wl && cpuRegs.LO.UD[1] == wl1) (*pass)++;
|
|
else if ((*failures)++ < 6)
|
|
printf(" %-6s %d, %d: console H %016llx %016llx L %016llx %016llx\n"
|
|
" ours H %016llx %016llx L %016llx %016llx\n",
|
|
kOps[op].name, (int)a, (int)b, wh, wh1, wl, wl1,
|
|
(unsigned long long)cpuRegs.HI.UD[0],
|
|
(unsigned long long)cpuRegs.HI.UD[1],
|
|
(unsigned long long)cpuRegs.LO.UD[0],
|
|
(unsigned long long)cpuRegs.LO.UD[1]);
|
|
return 0;
|
|
}
|
|
|
|
if (!read_off(&p, &off)) return 0;
|
|
p = strchr(buf, ':');
|
|
if (!p) return 0;
|
|
|
|
reset_pattern();
|
|
if (kOps[op].shape == LOAD)
|
|
{
|
|
if (sscanf(p + 1, " %x %x %x %x", &w3, &w2, &w1, &w0) != 4) return 0;
|
|
/* rt carries between cases; seed it as the lsu harness leaves it. */
|
|
cpuRegs.GPR.r[RT].UD[1] = 0x0000133A00001339ull;
|
|
cpuRegs.GPR.r[RS].UD[0] = LOAD_BASE;
|
|
cpuRegs.code = ((u32)RS << 21) | ((u32)RT << 16) | (u32)(off & 0xFFFF);
|
|
kOps[op].fn();
|
|
(*cases)++;
|
|
{
|
|
const u32 g0 = cpuRegs.GPR.r[RT].UL[0], g1 = cpuRegs.GPR.r[RT].UL[1];
|
|
const u32 g2 = cpuRegs.GPR.r[RT].UL[2], g3 = cpuRegs.GPR.r[RT].UL[3];
|
|
if (g0 == w0 && g1 == w1 && g2 == w2 && g3 == w3) (*pass)++;
|
|
else if ((*failures)++ < 6)
|
|
printf(" %-4s %+d: console %08x %08x %08x %08x ours %08x %08x %08x %08x\n",
|
|
kOps[op].name, off, w3, w2, w1, w0, g3, g2, g1, g0);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* STORE: the line prints the whole sixteen-byte row the store landed
|
|
* in, high word first, which is row 1 + offset/16 of the pattern. */
|
|
{
|
|
unsigned m3, m2, m1, m0;
|
|
int row;
|
|
if (sscanf(p + 1, " %x %x %x %x", &m3, &m2, &m1, &m0) != 4) return 0;
|
|
cpuRegs.GPR.r[RT].UD[0] = (*cases < block_total / 2)
|
|
? (u64)(s64)(s32)0xABCD4321u
|
|
: ((u64)0x1338u << 32) | 0x1337u;
|
|
cpuRegs.GPR.r[RT].UD[1] = 0x0000133A00001339ull;
|
|
cpuRegs.GPR.r[RS].UD[0] = STORE_BASE;
|
|
cpuRegs.code = ((u32)RS << 21) | ((u32)RT << 16) | (u32)(off & 0xFFFF);
|
|
s_cancelled = 0;
|
|
kOps[op].fn();
|
|
(*cases)++;
|
|
row = 16 + (off / 16) * 16; /* base row plus the printed offset */
|
|
{
|
|
u32 g[4];
|
|
int i;
|
|
for (i = 0; i < 4; i++)
|
|
memcpy(&g[i], s_mem + ((row + i * 4) & (MEMSIZE - 1)), 4);
|
|
if (!s_cancelled && g[0] == m0 && g[1] == m1
|
|
&& g[2] == m2 && g[3] == m3) (*pass)++;
|
|
else if ((*failures)++ < 6)
|
|
printf(" %-4s %+d: console %08x %08x %08x %08x ours %08x %08x %08x %08x%s\n",
|
|
kOps[op].name, off, m3, m2, m1, m0,
|
|
g[3], g[2], g[1], g[0],
|
|
s_cancelled ? " (cancelled)" : "");
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int main(int argc, char** argv)
|
|
{
|
|
const char* dir = (argc > 1) ? argv[1] : ".";
|
|
int op, failures = 0, total = 0;
|
|
/* rd carries between cases across the whole file, as in hwalu.c. */
|
|
u64 rd_hi = 0;
|
|
|
|
for (op = 0; op < NOPS; op++)
|
|
{
|
|
char path[512], head[32], buf[512];
|
|
FILE* f;
|
|
int inblock = 0, pass = 0, cases = 0, block_total = 0;
|
|
|
|
snprintf(path, sizeof(path), "%s/%s.expected", dir,
|
|
(kOps[op].shape == LOAD || kOps[op].shape == STORE) ? "lsu"
|
|
: (kOps[op].shape == MULDIV
|
|
|| kOps[op].shape == HILO_MOVE) ? "muldiv" : "alu");
|
|
f = fopen(path, "r");
|
|
if (!f) { fprintf(stderr, "cannot open %s\n", path); return 2; }
|
|
snprintf(head, sizeof(head), "%s:", kOps[op].name);
|
|
block_total = count_block(path, kOps[op].name);
|
|
|
|
while (fgets(buf, sizeof(buf), f))
|
|
{
|
|
Q a, b; unsigned w3, w2, w1, w0;
|
|
int named_a = 0, named_b = 0;
|
|
char* p; u32 sa = 0, imm = 0;
|
|
int dest;
|
|
|
|
if (!inblock)
|
|
{ if (!strncmp(buf, head, strlen(head)) && buf[strlen(head)] == '\n')
|
|
inblock = 1;
|
|
continue; }
|
|
if (buf[0] != ' ') break;
|
|
if (strstr(buf, "-> $0")) continue;
|
|
|
|
if (kOps[op].shape == LOAD || kOps[op].shape == STORE
|
|
|| kOps[op].shape == MULDIV || kOps[op].shape == HILO_MOVE)
|
|
{
|
|
if (!run_special(op, buf, &cases, &pass, &failures, block_total)) continue;
|
|
continue;
|
|
}
|
|
|
|
p = buf + 2 + strlen(kOps[op].name);
|
|
if (kOps[op].shape == RI)
|
|
{
|
|
a.w[0] = a.w[1] = a.w[2] = a.w[3] = 0;
|
|
if (!operand(&p, &b, &named_b)) continue;
|
|
}
|
|
else
|
|
{
|
|
if (!operand(&p, &a, &named_a)) continue;
|
|
if (!operand(&p, &b, &named_b)) continue;
|
|
}
|
|
while (*p == ' ' || *p == ':') p++;
|
|
if (sscanf(p, "%x %x %x %x", &w3, &w2, &w1, &w0) != 4) continue;
|
|
|
|
/* rd's carried upper doubleword, as hwalu.c models it. */
|
|
if (named_a || named_b) rd_hi = 0x0000133A00001339ull;
|
|
cpuRegs.GPR.r[RD].UD[1] = rd_hi;
|
|
cpuRegs.GPR.r[RD].UD[0] = (named_a || named_b)
|
|
? ((u64)0x1338u << 32) | 0x1337u : 0x1337u;
|
|
|
|
switch (kOps[op].shape)
|
|
{
|
|
case RRR:
|
|
if (kOps[op].swap) { const Q t = a; a = b; b = t; }
|
|
set_reg(RS, &a); set_reg(RT, &b);
|
|
cpuRegs.code = ((u32)RS << 21) | ((u32)RT << 16) | ((u32)RD << 11);
|
|
dest = RD;
|
|
break;
|
|
case RRI:
|
|
set_reg(RS, &a);
|
|
imm = b.w[0] & 0xFFFF;
|
|
cpuRegs.code = ((u32)RS << 21) | ((u32)RT << 16) | imm;
|
|
dest = RT;
|
|
break;
|
|
case RI:
|
|
imm = b.w[0] & 0xFFFF;
|
|
cpuRegs.code = ((u32)RT << 16) | imm;
|
|
dest = RT;
|
|
break;
|
|
default: /* RRS */
|
|
set_reg(RT, &a);
|
|
sa = b.w[0] & 0x1F;
|
|
cpuRegs.code = ((u32)RT << 16) | ((u32)RD << 11) | (sa << 6);
|
|
dest = RD;
|
|
break;
|
|
}
|
|
/* The immediate forms write rt, so it has to carry the seed too. */
|
|
if (dest == RT)
|
|
{
|
|
cpuRegs.GPR.r[RT].UD[1] = rd_hi;
|
|
cpuRegs.GPR.r[RT].UD[0] = (named_a || named_b)
|
|
? ((u64)0x1338u << 32) | 0x1337u : 0x1337u;
|
|
}
|
|
|
|
kOps[op].fn();
|
|
|
|
cases++;
|
|
{
|
|
const u32 g0 = cpuRegs.GPR.r[dest].UL[0];
|
|
const u32 g1 = cpuRegs.GPR.r[dest].UL[1];
|
|
const u32 g2 = cpuRegs.GPR.r[dest].UL[2];
|
|
const u32 g3 = cpuRegs.GPR.r[dest].UL[3];
|
|
if (g0 == w0 && g1 == w1 && g2 == w2 && g3 == w3) pass++;
|
|
else if (failures++ < 6)
|
|
printf(" %-7s console %08x %08x %08x %08x ours %08x %08x %08x %08x\n",
|
|
kOps[op].name, w3, w2, w1, w0, g3, g2, g1, g0);
|
|
rd_hi = ((u64)w3 << 32) | w2;
|
|
}
|
|
}
|
|
fclose(f);
|
|
total += cases;
|
|
/* block_total is already the number of case lines the block has --
|
|
* it is computed above for the store seed's midpoint -- so compare
|
|
* against it rather than only checking for zero. Every
|
|
* under-coverage bug in this series was partial: a missing
|
|
* constant, an operand shape matching some lines and not others.
|
|
* Checking "did anything parse" would have caught none of them. */
|
|
if (block_total > 0 && cases != block_total)
|
|
{ printf("%-7s parsed %d of the %d lines its block has;"
|
|
" some operand shape does not match\n",
|
|
kOps[op].name, cases, block_total);
|
|
failures++; }
|
|
else if (cases == 0)
|
|
{ printf("%-7s parsed no cases; the block name or line shape changed\n",
|
|
kOps[op].name);
|
|
failures++; }
|
|
else if (pass != cases)
|
|
{ printf("%-7s %2d/%-3d console cases\n", kOps[op].name, pass, cases);
|
|
failures++; }
|
|
}
|
|
|
|
/* ---- cases the capture cannot supply -------------------------------
|
|
*
|
|
* MIPS splits the immediate forms: the arithmetic and compare ones --
|
|
* ADDIU, DADDIU, SLTI, SLTIU -- sign-extend their immediate, and the
|
|
* logical ones -- ANDI, ORI, XORI -- zero-extend it. Getting that
|
|
* split wrong is a classic implementation mistake and the capture
|
|
* cannot see it: not one of the 144 lines across those seven ops in
|
|
* tests/cpu/ee/alu.expected uses a negative or high-bit immediate, so
|
|
* swapping _Imm_ for _ImmU_ in SLTIU passes all 814 console cases.
|
|
*
|
|
* These come from the MIPS definition rather than from hardware, and
|
|
* every one uses an immediate with bit 15 set, which is the only place
|
|
* the two extensions differ.
|
|
*/
|
|
{
|
|
static const struct { const char* name; void (*fn)(); u64 rs; u32 imm; u64 want; }
|
|
kSpec[] = {
|
|
/* Sign-extending: 0xffff means -1. */
|
|
{ "addiu", ADDIU, 0x0000000000000001ull, 0xFFFFu, 0x0000000000000000ull },
|
|
{ "addiu", ADDIU, 0x0000000000000000ull, 0xFFFFu, 0xFFFFFFFFFFFFFFFFull },
|
|
{ "daddiu", DADDIU, 0x0000000000000001ull, 0xFFFFu, 0x0000000000000000ull },
|
|
{ "slti", SLTI, 0xFFFFFFFFFFFFFFFEull, 0xFFFFu, 1 }, /* -2 < -1 */
|
|
{ "slti", SLTI, 0x0000000000000000ull, 0xFFFFu, 0 },
|
|
{ "sltiu", SLTIU, 0x0000000000000000ull, 0xFFFFu, 1 }, /* 0 < ffff..ff */
|
|
{ "sltiu", SLTIU, 0x0000000000010000ull, 0xFFFFu, 1 }, /* zero-ext says 0 */
|
|
/* Zero-extending: 0xffff means 65535, not -1. */
|
|
{ "andi", ANDI, 0xFFFFFFFFFFFFFFFFull, 0xFFFFu, 0x000000000000FFFFull },
|
|
{ "ori", ORI, 0x0000000000000000ull, 0xFFFFu, 0x000000000000FFFFull },
|
|
{ "xori", XORI, 0x0000000000000000ull, 0xFFFFu, 0x000000000000FFFFull },
|
|
};
|
|
const int n = (int)(sizeof(kSpec)/sizeof(kSpec[0]));
|
|
int i, pass = 0;
|
|
|
|
for (i = 0; i < n; i++)
|
|
{
|
|
memset(&cpuRegs.GPR, 0, sizeof(cpuRegs.GPR));
|
|
cpuRegs.GPR.r[RS].UD[0] = kSpec[i].rs;
|
|
cpuRegs.code = ((u32)RS << 21) | ((u32)RT << 16) | kSpec[i].imm;
|
|
kSpec[i].fn();
|
|
if (cpuRegs.GPR.r[RT].UD[0] == kSpec[i].want) pass++;
|
|
else
|
|
printf(" %-7s %016llx, 0xffff: MIPS says %016llx, ours %016llx\n",
|
|
kSpec[i].name,
|
|
(unsigned long long)kSpec[i].rs,
|
|
(unsigned long long)kSpec[i].want,
|
|
(unsigned long long)cpuRegs.GPR.r[RT].UD[0]);
|
|
}
|
|
total += n;
|
|
printf("spec %2d/%-3d immediate-extension cases from the MIPS definition\n",
|
|
pass, n);
|
|
if (pass != n) failures++;
|
|
}
|
|
|
|
printf("hwrealee: %d cases across %d ops, driven through R5900OpcodeImpl.cpp\n",
|
|
total, NOPS);
|
|
return failures != 0;
|
|
}
|