mirror of
https://github.com/libretro/pcsx2.git
synced 2024-11-25 10:20:09 +00:00
microVU:
- Code refactoring (mostly changing macros to functions/constants...) - Made it so the disable-regAlloc option flushes every 32bit instruction, instead of every 64bit instruction (upper+lower instruction pair) git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3713 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
807bd9659c
commit
009d6ba5e6
@ -647,10 +647,6 @@
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RelativePath="..\..\x86\microVU_IR.h"
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>
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</File>
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<File
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RelativePath="..\..\x86\microVU_IR.inl"
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>
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</File>
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<File
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RelativePath="..\..\x86\microVU_Log.inl"
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>
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@ -24,7 +24,6 @@
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#include "microVU_Misc.inl"
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#include "microVU_Log.inl"
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#include "microVU_Analyze.inl"
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#include "microVU_IR.inl"
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#include "microVU_Alloc.inl"
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#include "microVU_Upper.inl"
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#include "microVU_Lower.inl"
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@ -103,7 +102,7 @@ void microVU::init(uint vuIndex) {
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dispCache = NULL;
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cache = NULL;
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cacheSize = mVUcacheSize;
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regAlloc = new microRegAlloc(this);
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regAlloc = new microRegAlloc(index);
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for (u32 i = 0; i < (progSize / 2); i++) {
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prog.prog[i] = new deque<microProgram*>();
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@ -90,7 +90,7 @@ public:
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for (int i = 0; i <= listI; i++) {
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if ((linkI->block->pState.q == pState->q)
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&& (linkI->block->pState.p == pState->p)
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&& ((linkI->block->pState.vi15 == pState->vi15) || !CHECK_VU_CONSTPROP)
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&& ((linkI->block->pState.vi15 == pState->vi15) || !doConstProp)
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&& (linkI->block->pState.flags == pState->flags)
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&& (linkI->block->pState.xgkick == pState->xgkick)
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&& (linkI->block->pState.viBackUp == pState->viBackUp)
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@ -229,12 +229,6 @@ struct microVU {
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return (((prog.IRinfo.curPC + 4) + (Imm11() * 2)) & progMemMask) * 4;
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}
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__ri void loadIreg(const xmm& reg, int xyzw)
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{
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xMOVSSZX(reg, ptr32[&getVI(REG_I)]);
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if (!_XYZWss(xyzw)) xSHUF.PS(reg, reg, 0);
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}
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void init(uint vuIndex);
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void reset();
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void close();
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@ -470,7 +470,7 @@ __fi void mVUanalyzeNormBranch(mV, int It, bool isBAL) {
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__ri void mVUanalyzeJump(mV, int Is, int It, bool isJALR) {
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mVUbranchCheck(mVU);
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mVUlow.branch = (isJALR) ? 10 : 9;
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if (mVUconstReg[Is].isValid && CHECK_VU_CONSTPROP) {
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if (mVUconstReg[Is].isValid && doConstProp) {
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mVUlow.constJump.isValid = 1;
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mVUlow.constJump.regValue = mVUconstReg[Is].regValue;
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//DevCon.Status("microVU%d: Constant JR/JALR Address Optimization", mVU->index);
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@ -15,31 +15,19 @@
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#pragma once
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//------------------------------------------------------------------
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// Helper Macros
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//------------------------------------------------------------------
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#define calcCycles(reg, x) { reg = ((reg > x) ? (reg - x) : 0); }
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#define optimizeReg(rState) { rState = (rState==1) ? 0 : rState; }
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#define tCycles(dest, src) { dest = aMax(dest, src); }
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#define incP() { mVU->p = (mVU->p+1) & 1; }
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#define incQ() { mVU->q = (mVU->q+1) & 1; }
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#define doUpperOp() { mVUopU(mVU, 1); mVUdivSet(mVU); }
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#define doLowerOp() { incPC(-1); mVUopL(mVU, 1); incPC(1); }
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//------------------------------------------------------------------
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// Messages Called at Execution Time...
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//------------------------------------------------------------------
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static void __fastcall mVUbadOp0(mV) { Console.Error("microVU0 Warning: Exiting... Block started with illegal opcode. [%04x] [%x]", xPC, mVU->prog.cur); }
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static void __fastcall mVUbadOp1(mV) { Console.Error("microVU1 Warning: Exiting... Block started with illegal opcode. [%04x] [%x]", xPC, mVU->prog.cur); }
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static void __fastcall mVUwarning0(mV) { Console.Error("microVU0 Warning: Exiting from Possible Infinite Loop [%04x] [%x]", xPC, mVU->prog.cur); }
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static void __fastcall mVUwarning1(mV) { Console.Error("microVU1 Warning: Exiting from Possible Infinite Loop [%04x] [%x]", xPC, mVU->prog.cur); }
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static void __fastcall mVUprintPC1(u32 PC) { Console.WriteLn("Block Start PC = 0x%04x", PC); }
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static void __fastcall mVUprintPC2(u32 PC) { Console.WriteLn("Block End PC = 0x%04x", PC); }
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static void __fastcall mVUbadOp0(mV, u32 PC) { Console.Error("microVU0 Warning: Exiting... Block started with illegal opcode. [%04x] [%x]", PC, mVU->prog.cur->idx); }
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static void __fastcall mVUbadOp1(mV, u32 PC) { Console.Error("microVU1 Warning: Exiting... Block started with illegal opcode. [%04x] [%x]", PC, mVU->prog.cur->idx); }
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static void __fastcall mVUwarning0(mV) { Console.Error("microVU0 Warning: Exiting from Possible Infinite Loop [%04x] [%x]", mVU->prog.cur->idx); }
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static void __fastcall mVUwarning1(mV) { Console.Error("microVU1 Warning: Exiting from Possible Infinite Loop [%04x] [%x]", mVU->prog.cur->idx); }
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static void __fastcall mVUprintPC1(u32 PC) { Console.WriteLn("Block Start PC = 0x%04x", PC); }
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static void __fastcall mVUprintPC2(u32 PC) { Console.WriteLn("Block End PC = 0x%04x", PC); }
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//------------------------------------------------------------------
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// Helper Functions
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// Program Range Checking and Setting up Ranges
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//------------------------------------------------------------------
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// Used by mVUsetupRange
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@ -106,13 +94,13 @@ static void mVUsetupRange(microVU* mVU, s32 pc, bool isStartPC) {
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}
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}
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static __fi void startLoop(mV) {
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if (curI & _Mbit_) { Console.WriteLn(Color_Green, "microVU%d: M-bit set!", getIndex); }
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if (curI & _Dbit_) { DevCon.WriteLn (Color_Green, "microVU%d: D-bit set!", getIndex); }
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if (curI & _Tbit_) { DevCon.WriteLn (Color_Green, "microVU%d: T-bit set!", getIndex); }
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memzero(mVUinfo);
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memzero(mVUregsTemp);
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}
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//------------------------------------------------------------------
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// Execute VU Opcode/Instruction (Upper and Lower)
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//------------------------------------------------------------------
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__ri void doUpperOp(mV) { mVUopU(mVU, 1); mVUdivSet(mVU); }
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__ri void doLowerOp(mV) { incPC(-1); mVUopL(mVU, 1); incPC(1); }
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__ri void flushRegs(mV) { if (!doRegAlloc) mVU->regAlloc->flushAll(); }
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static void doIbit(mV) {
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if (mVUup.iBit) {
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@ -126,7 +114,7 @@ static void doIbit(mV) {
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}
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else tempI = curI;
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xMOV(ptr32[&mVU->regs().VI[REG_I].UL], tempI);
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xMOV(ptr32[&mVU->getVI(REG_I)], tempI);
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incPC(1);
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}
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}
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@ -150,16 +138,27 @@ static void doSwapOp(mV) {
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mVU->regAlloc->clearNeeded(t3);
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incPC(1);
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doUpperOp();
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doUpperOp(mVU);
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const xmm& t4 = mVU->regAlloc->allocReg(-1, mVUlow.VF_write.reg, 0xf);
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xMOVAPS(t4, t2);
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mVU->regAlloc->clearNeeded(t4);
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mVU->regAlloc->clearNeeded(t2);
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}
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else { mVUopL(mVU, 1); incPC(1); doUpperOp(); }
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else { mVUopL(mVU, 1); incPC(1); flushRegs(mVU); doUpperOp(mVU); }
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}
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static void mVUexecuteInstruction(mV) {
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if (mVUlow.isNOP) { incPC(1); doUpperOp(mVU); flushRegs(mVU); doIbit(mVU); }
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elif(!mVUinfo.swapOps) { incPC(1); doUpperOp(mVU); flushRegs(mVU); doLowerOp(mVU); }
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else doSwapOp(mVU);
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flushRegs(mVU);
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}
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//------------------------------------------------------------------
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// Warnings / Errors / Illegal Instructions
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//------------------------------------------------------------------
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// If 1st op in block is a bad opcode, then don't compile rest of block (Dawn of Mana Level 2)
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static __fi void mVUcheckBadOp(mV) {
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if (mVUinfo.isBadOp && mVUcount == 0) {
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@ -172,6 +171,7 @@ static __fi void mVUcheckBadOp(mV) {
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static __fi void handleBadOp(mV, int count) {
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if (mVUinfo.isBadOp && count == 0) {
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xMOV(gprT2, (uptr)mVU);
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xMOV(gprT3, xPC);
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if (!isVU1) xCALL(mVUbadOp0);
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else xCALL(mVUbadOp1);
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}
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@ -211,8 +211,21 @@ static __ri void eBitWarning(mV) {
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incPC(-2);
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}
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//------------------------------------------------------------------
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// Cycles / Pipeline State / Early Exit from Execution
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//------------------------------------------------------------------
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__fi void optimizeReg(u8& rState) { rState = (rState==1) ? 0 : rState; }
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__fi void calcCycles(u8& reg, u8 x) { reg = ((reg > x) ? (reg - x) : 0); }
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__fi void tCycles(u8& dest, u8& src) { dest = aMax(dest, src); }
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__fi void incP(mV) { mVU->p ^= 1; }
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__fi void incQ(mV) { mVU->q ^= 1; }
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// Optimizes the End Pipeline State Removing Unnecessary Info
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static __fi void mVUoptimizePipeState(mV) {
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// If the cycles remaining is just '1', we don't have to transfer it to the next block
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// because mVU automatically decrements this number at the start of its loop,
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// so essentially '1' will be the same as '0'...
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static void mVUoptimizePipeState(mV) {
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for (int i = 0; i < 32; i++) {
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optimizeReg(mVUregs.VF[i].x);
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optimizeReg(mVUregs.VF[i].y);
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@ -222,12 +235,12 @@ static __fi void mVUoptimizePipeState(mV) {
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for (int i = 0; i < 16; i++) {
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optimizeReg(mVUregs.VI[i]);
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}
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if (mVUregs.q) { optimizeReg(mVUregs.q); if (!mVUregs.q) { incQ(); } }
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if (mVUregs.p) { optimizeReg(mVUregs.p); if (!mVUregs.p) { incP(); } }
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if (mVUregs.q) { optimizeReg(mVUregs.q); if (!mVUregs.q) { incQ(mVU); } }
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if (mVUregs.p) { optimizeReg(mVUregs.p); if (!mVUregs.p) { incP(mVU); } }
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mVUregs.r = 0; // There are no stalls on the R-reg, so its Safe to discard info
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}
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__fi void mVUincCycles(mV, int x) {
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static void mVUincCycles(mV, int x) {
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mVUcycles += x;
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for (int z = 31; z > 0; z--) {
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calcCycles(mVUregs.VF[z].x, x);
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@ -241,11 +254,11 @@ __fi void mVUincCycles(mV, int x) {
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if (mVUregs.q) {
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if (mVUregs.q > 4) { calcCycles(mVUregs.q, x); if (mVUregs.q <= 4) { mVUinfo.doDivFlag = 1; } }
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else { calcCycles(mVUregs.q, x); }
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if (!mVUregs.q) { incQ(); }
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if (!mVUregs.q) { incQ(mVU); }
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}
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if (mVUregs.p) {
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calcCycles(mVUregs.p, x);
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if (!mVUregs.p || mVUregsTemp.p) { incP(); }
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if (!mVUregs.p || mVUregsTemp.p) { incP(mVU); }
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}
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if (mVUregs.xgkick) {
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calcCycles(mVUregs.xgkick, x);
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@ -254,14 +267,13 @@ __fi void mVUincCycles(mV, int x) {
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calcCycles(mVUregs.r, x);
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}
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#define cmpVFregs(VFreg1, VFreg2, xVar) { \
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if (VFreg1.reg == VFreg2.reg) { \
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if ((VFreg1.x && VFreg2.x) \
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|| (VFreg1.y && VFreg2.y) \
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|| (VFreg1.z && VFreg2.z) \
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|| (VFreg1.w && VFreg2.w)) \
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{ xVar = 1; } \
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} \
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// Helps check if upper/lower ops read/write to same regs...
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void cmpVFregs(microVFreg& VFreg1, microVFreg& VFreg2, bool& xVar) {
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if (VFreg1.reg == VFreg2.reg) {
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if ((VFreg1.x && VFreg2.x) || (VFreg1.y && VFreg2.y)
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|| (VFreg1.z && VFreg2.z) || (VFreg1.w && VFreg2.w))
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{ xVar = 1; }
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}
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}
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void mVUsetCycles(mV) {
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@ -299,6 +311,15 @@ void mVUsetCycles(mV) {
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tCycles(mVUregs.xgkick, mVUregsTemp.xgkick);
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}
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// Prints Start/End PC of blocks executed, for debugging...
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static void mVUdebugPrintBlocks(microVU* mVU, bool isEndPC) {
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if (mVUdebugNow) {
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xMOV(gprT2, xPC);
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if (isEndPC) xCALL(mVUprintPC2);
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else xCALL(mVUprintPC1);
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}
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}
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// vu0 is allowed to exit early, so are dev builds (for inf loops)
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__fi bool doEarlyExit(microVU* mVU) {
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return IsDevBuild || !isVU1;
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@ -312,15 +333,6 @@ static __fi void mVUsavePipelineState(microVU* mVU) {
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}
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}
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// Prints Start/End PC of blocks executed, for debugging...
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static void mVUdebugPrintBlocks(microVU* mVU, bool isEndPC) {
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if (mVUdebugNow) {
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xMOV(gprT2, xPC);
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if (isEndPC) xCALL(mVUprintPC2);
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else xCALL(mVUprintPC1);
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}
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}
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// Test cycles to see if we need to exit-early...
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static void mVUtestCycles(microVU* mVU) {
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iPC = mVUstartPC;
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@ -332,8 +344,8 @@ static void mVUtestCycles(microVU* mVU) {
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// xFowardJZ32 vu0jmp;
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// xMOV(gprT2, (uptr)mVU);
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// xCALL(mVUwarning0); // VU0 is allowed early exit for COP2 Interlock Simulation
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mVUsavePipelineState(mVU);
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mVUendProgram(mVU, NULL, 0);
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mVUsavePipelineState(mVU);
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mVUendProgram(mVU, NULL, 0);
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// vu0jmp.SetTarget();
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}
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else {
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@ -347,6 +359,19 @@ static void mVUtestCycles(microVU* mVU) {
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xSUB(ptr32[&mVU->cycles], mVUcycles);
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}
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//------------------------------------------------------------------
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// Initializing
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//------------------------------------------------------------------
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// This gets run at the start of every loop of mVU's first pass
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static __fi void startLoop(mV) {
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if (curI & _Mbit_) { Console.WriteLn(Color_Green, "microVU%d: M-bit set!", getIndex); }
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if (curI & _Dbit_) { DevCon.WriteLn (Color_Green, "microVU%d: D-bit set!", getIndex); }
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if (curI & _Tbit_) { DevCon.WriteLn (Color_Green, "microVU%d: T-bit set!", getIndex); }
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memzero(mVUinfo);
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memzero(mVUregsTemp);
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}
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// Initialize VI Constants (vi15 propagates through blocks)
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static __fi void mVUinitConstValues(microVU* mVU) {
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for (int i = 0; i < 16; i++) {
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@ -393,7 +418,7 @@ void* mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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// First Pass
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iPC = startPC / 4;
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mVUsetupRange(mVU, startPC, 1); // Setup Program Bounds/Range
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mVUsetupRange(mVU, startPC, 1); // Setup Program Bounds/Range
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mVU->regAlloc->reset(); // Reset regAlloc
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mVUinitFirstPass(mVU, pState, thisPtr);
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for (int branch = 0; mVUcount < endCount; mVUcount++) {
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@ -419,7 +444,7 @@ void* mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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}
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// Fix up vi15 const info for propagation through blocks
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mVUregs.vi15 = (mVUconstReg[15].isValid && CHECK_VU_CONSTPROP) ? ((1<<31) | (mVUconstReg[15].regValue&0xffff)) : 0;
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mVUregs.vi15 = (mVUconstReg[15].isValid && doConstProp) ? ((1<<31) | (mVUconstReg[15].regValue&0xffff)) : 0;
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mVUsetFlags(mVU, mFC); // Sets Up Flag instances
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mVUoptimizePipeState(mVU); // Optimize the End Pipeline State for nicer Block Linking
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@ -434,11 +459,8 @@ void* mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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for (; x < endCount; x++) {
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if (mVUinfo.isEOB) { handleBadOp(mVU, x); x = 0xffff; }
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if (mVUup.mBit) { xOR(ptr32[&mVU->regs().flags], VUFLAG_MFLAGSET); }
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if (mVUlow.isNOP) { incPC(1); doUpperOp(); doIbit(mVU); }
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else if (!mVUinfo.swapOps) { incPC(1); doUpperOp(); doLowerOp(); }
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else { doSwapOp(mVU); }
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mVUexecuteInstruction(mVU);
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if (mVUinfo.doXGKICK) { mVU_XGKICK_DELAY(mVU, 1); }
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if (!doRegAlloc) { mVU->regAlloc->flushAll(); }
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if (isEvilBlock) { mVUsetupRange(mVU, xPC, 0); normJumpCompile(mVU, mFC, 1); return thisPtr; }
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else if (!mVUinfo.isBdelay) { incPC(1); }
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else {
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@ -286,7 +286,7 @@ void mVUflagPass(mV, u32 startPC, u32 sCount = 0, u32 found = 0) {
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__fi void mVUsetFlagInfo(mV) {
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branchType1 { incPC(-1); mVUflagPass(mVU, branchAddr); incPC(1); }
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branchType2 { // This case can possibly be turned off via a hack for a small speedup...
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if (!mVUlow.constJump.isValid || !CHECK_VU_CONSTPROP) { mVUregs.needExactMatch |= 0x7; }
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if (!mVUlow.constJump.isValid || !doConstProp) { mVUregs.needExactMatch |= 0x7; }
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else { mVUflagPass(mVU, (mVUlow.constJump.regValue*8)&(mVU->microMemSize-8)); }
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}
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branchType3 {
|
||||
|
||||
@ -170,39 +170,194 @@ struct microMapXMM {
|
||||
bool isNeeded; // Is needed for current instruction
|
||||
};
|
||||
|
||||
#define xmmTotal 7 // Don't allocate PQ?
|
||||
class microRegAlloc {
|
||||
protected:
|
||||
static const u32 xmmTotal = 7; // Don't allocate PQ?
|
||||
microMapXMM xmmMap[xmmTotal];
|
||||
int counter;
|
||||
microVU* mVU;
|
||||
int counter; // Current allocation count
|
||||
int index; // VU0 or VU1
|
||||
|
||||
// Helper functions to get VU regs
|
||||
VURegs& regs() const { return ::vuRegs[index]; }
|
||||
__fi REG_VI& getVI(uint reg) const { return regs().VI[reg]; }
|
||||
__fi VECTOR& getVF(uint reg) const { return regs().VF[reg]; }
|
||||
|
||||
__ri void loadIreg(const xmm& reg, int xyzw) {
|
||||
xMOVSSZX(reg, ptr32[&getVI(REG_I)]);
|
||||
if (!_XYZWss(xyzw)) xSHUF.PS(reg, reg, 0);
|
||||
}
|
||||
|
||||
int findFreeRegRec(int startIdx);
|
||||
int findFreeReg();
|
||||
int findFreeRegRec(int startIdx) {
|
||||
for (int i = startIdx; i < xmmTotal; i++) {
|
||||
if (!xmmMap[i].isNeeded) {
|
||||
int x = findFreeRegRec(i+1);
|
||||
if (x == -1) return i;
|
||||
return ((xmmMap[i].count < xmmMap[x].count) ? i : x);
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int findFreeReg() {
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
if (!xmmMap[i].isNeeded && (xmmMap[i].VFreg < 0)) {
|
||||
return i; // Reg is not needed and was a temp reg
|
||||
}
|
||||
}
|
||||
int x = findFreeRegRec(0);
|
||||
pxAssumeDev( x >= 0, "microVU register allocation failure!" );
|
||||
return x;
|
||||
}
|
||||
|
||||
public:
|
||||
microRegAlloc(microVU* _mVU);
|
||||
|
||||
microRegAlloc(int _index) {
|
||||
index = _index;
|
||||
}
|
||||
|
||||
void reset() {
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
clearReg(i);
|
||||
}
|
||||
counter = 0;
|
||||
}
|
||||
|
||||
void flushAll(bool clearState = 1) {
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
writeBackReg(xmm(i));
|
||||
if (clearState) clearReg(i);
|
||||
}
|
||||
}
|
||||
void clearReg(int regId);
|
||||
|
||||
void clearReg(const xmm& reg) { clearReg(reg.Id); }
|
||||
void clearReg(int regId) {
|
||||
microMapXMM& clear( xmmMap[regId] );
|
||||
clear.VFreg = -1;
|
||||
clear.count = 0;
|
||||
clear.xyzw = 0;
|
||||
clear.isNeeded = 0;
|
||||
}
|
||||
|
||||
void clearRegVF(int VFreg) {
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
if (xmmMap[i].VFreg == VFreg) clearReg(i);
|
||||
}
|
||||
}
|
||||
void writeBackReg(const xmm& reg, bool invalidateRegs = 1);
|
||||
void clearNeeded(const xmm& reg);
|
||||
const xmm& allocReg(int vfLoadReg = -1, int vfWriteReg = -1, int xyzw = 0, bool cloneWrite = 1);
|
||||
|
||||
void writeBackReg(const xmm& reg, bool invalidateRegs = 1) {
|
||||
microMapXMM& write( xmmMap[reg.Id] );
|
||||
|
||||
if ((write.VFreg > 0) && write.xyzw) { // Reg was modified and not Temp or vf0
|
||||
if (write.VFreg == 33) xMOVSS(ptr32[&getVI(REG_I)], reg);
|
||||
else if (write.VFreg == 32) mVUsaveReg(reg, ptr[®s().ACC], write.xyzw, 1);
|
||||
else mVUsaveReg(reg, ptr[&getVF(write.VFreg)], write.xyzw, 1);
|
||||
if (invalidateRegs) {
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
microMapXMM& imap (xmmMap[i]);
|
||||
if ((i == reg.Id) || imap.isNeeded) continue;
|
||||
if (imap.VFreg == write.VFreg) {
|
||||
if (imap.xyzw && imap.xyzw < 0xf) DevCon.Error("microVU Error: writeBackReg() [%d]", imap.VFreg);
|
||||
clearReg(i); // Invalidate any Cached Regs of same vf Reg
|
||||
}
|
||||
}
|
||||
}
|
||||
if (write.xyzw == 0xf) { // Make Cached Reg if All Vectors were Modified
|
||||
write.count = counter;
|
||||
write.xyzw = 0;
|
||||
write.isNeeded = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
clearReg(reg); // Clear Reg
|
||||
}
|
||||
|
||||
void clearNeeded(const xmm& reg) {
|
||||
|
||||
if ((reg.Id < 0) || (reg.Id >= xmmTotal)) return;
|
||||
|
||||
microMapXMM& clear (xmmMap[reg.Id]);
|
||||
clear.isNeeded = 0;
|
||||
if (clear.xyzw) { // Reg was modified
|
||||
if (clear.VFreg > 0) {
|
||||
int mergeRegs = 0;
|
||||
if (clear.xyzw < 0xf) { mergeRegs = 1; } // Try to merge partial writes
|
||||
for (int i = 0; i < xmmTotal; i++) { // Invalidate any other read-only regs of same vfReg
|
||||
if (i == reg.Id) continue;
|
||||
microMapXMM& imap (xmmMap[i]);
|
||||
if (imap.VFreg == clear.VFreg) {
|
||||
if (imap.xyzw && imap.xyzw < 0xf) DevCon.Error("microVU Error: clearNeeded() [%d]", imap.VFreg);
|
||||
if (mergeRegs == 1) {
|
||||
mVUmergeRegs(xmm(i), reg, clear.xyzw, 1);
|
||||
imap.xyzw = 0xf;
|
||||
imap.count = counter;
|
||||
mergeRegs = 2;
|
||||
}
|
||||
else clearReg(i);
|
||||
}
|
||||
}
|
||||
if (mergeRegs == 2) clearReg(reg); // Clear Current Reg if Merged
|
||||
else if (mergeRegs) writeBackReg(reg); // Write Back Partial Writes if couldn't merge
|
||||
}
|
||||
else clearReg(reg); // If Reg was temp or vf0, then invalidate itself
|
||||
}
|
||||
}
|
||||
|
||||
const xmm& allocReg(int vfLoadReg = -1, int vfWriteReg = -1, int xyzw = 0, bool cloneWrite = 1) {
|
||||
counter++;
|
||||
if (vfLoadReg >= 0) { // Search For Cached Regs
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
const xmm& xmmi(xmm::GetInstance(i));
|
||||
microMapXMM& imap (xmmMap[i]);
|
||||
if ((imap.VFreg == vfLoadReg) && (!imap.xyzw // Reg Was Not Modified
|
||||
|| (imap.VFreg && (imap.xyzw==0xf)))) { // Reg Had All Vectors Modified and != VF0
|
||||
int z = i;
|
||||
if (vfWriteReg >= 0) { // Reg will be modified
|
||||
if (cloneWrite) { // Clone Reg so as not to use the same Cached Reg
|
||||
z = findFreeReg();
|
||||
const xmm& xmmz(xmm::GetInstance(z));
|
||||
writeBackReg(xmmz);
|
||||
if (z!=i && xyzw==8) xMOVAPS (xmmz, xmmi);
|
||||
else if (xyzw == 4) xPSHUF.D(xmmz, xmmi, 1);
|
||||
else if (xyzw == 2) xPSHUF.D(xmmz, xmmi, 2);
|
||||
else if (xyzw == 1) xPSHUF.D(xmmz, xmmi, 3);
|
||||
else if (z != i) xMOVAPS (xmmz, xmmi);
|
||||
imap.count = counter; // Reg i was used, so update counter
|
||||
}
|
||||
else { // Don't clone reg, but shuffle to adjust for SS ops
|
||||
if ((vfLoadReg != vfWriteReg) || (xyzw != 0xf)) { writeBackReg(xmmi); }
|
||||
if (xyzw == 4) xPSHUF.D(xmmi, xmmi, 1);
|
||||
else if (xyzw == 2) xPSHUF.D(xmmi, xmmi, 2);
|
||||
else if (xyzw == 1) xPSHUF.D(xmmi, xmmi, 3);
|
||||
}
|
||||
xmmMap[z].VFreg = vfWriteReg;
|
||||
xmmMap[z].xyzw = xyzw;
|
||||
}
|
||||
xmmMap[z].count = counter;
|
||||
xmmMap[z].isNeeded = 1;
|
||||
return xmm::GetInstance(z);
|
||||
}
|
||||
}
|
||||
}
|
||||
int x = findFreeReg();
|
||||
const xmm& xmmx = xmm::GetInstance(x);
|
||||
writeBackReg(xmmx);
|
||||
|
||||
if (vfWriteReg >= 0) { // Reg Will Be Modified (allow partial reg loading)
|
||||
if ((vfLoadReg == 0) && !(xyzw & 1)) { xPXOR(xmmx, xmmx); }
|
||||
else if (vfLoadReg == 33) loadIreg (xmmx, xyzw);
|
||||
else if (vfLoadReg == 32) mVUloadReg(xmmx, ptr[®s().ACC], xyzw);
|
||||
else if (vfLoadReg >= 0) mVUloadReg(xmmx, ptr[&getVF(vfLoadReg)], xyzw);
|
||||
xmmMap[x].VFreg = vfWriteReg;
|
||||
xmmMap[x].xyzw = xyzw;
|
||||
}
|
||||
else { // Reg Will Not Be Modified (always load full reg for caching)
|
||||
if (vfLoadReg == 33) loadIreg(xmmx, 0xf);
|
||||
else if (vfLoadReg == 32) xMOVAPS (xmmx, ptr128[®s().ACC]);
|
||||
else if (vfLoadReg >= 0) xMOVAPS (xmmx, ptr128[&getVF(vfLoadReg)]);
|
||||
xmmMap[x].VFreg = vfLoadReg;
|
||||
xmmMap[x].xyzw = 0;
|
||||
}
|
||||
xmmMap[x].count = counter;
|
||||
xmmMap[x].isNeeded = 1;
|
||||
return xmmx;
|
||||
}
|
||||
};
|
||||
|
||||
@ -1,165 +0,0 @@
|
||||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
* ation, either version 3 of the License, or (at your option) any later version.
|
||||
*
|
||||
* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with PCSX2.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
|
||||
int microRegAlloc::findFreeRegRec(int startIdx) {
|
||||
for (int i = startIdx; i < xmmTotal; i++) {
|
||||
if (!xmmMap[i].isNeeded) {
|
||||
int x = findFreeRegRec(i+1);
|
||||
if (x == -1) return i;
|
||||
return ((xmmMap[i].count < xmmMap[x].count) ? i : x);
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
int microRegAlloc::findFreeReg() {
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
if (!xmmMap[i].isNeeded && (xmmMap[i].VFreg < 0)) {
|
||||
return i; // Reg is not needed and was a temp reg
|
||||
}
|
||||
}
|
||||
int x = findFreeRegRec(0);
|
||||
pxAssumeDev( x >= 0, "microVU register allocation failure!" );
|
||||
return x;
|
||||
}
|
||||
|
||||
microRegAlloc::microRegAlloc(microVU* _mVU) {
|
||||
mVU = _mVU;
|
||||
}
|
||||
|
||||
void microRegAlloc::clearReg(int regId) {
|
||||
microMapXMM& clear( xmmMap[regId] );
|
||||
clear.VFreg = -1;
|
||||
clear.count = 0;
|
||||
clear.xyzw = 0;
|
||||
clear.isNeeded = 0;
|
||||
}
|
||||
void microRegAlloc::writeBackReg(const xmm& reg, bool invalidateRegs) {
|
||||
microMapXMM& write( xmmMap[reg.Id] );
|
||||
|
||||
if ((write.VFreg > 0) && write.xyzw) { // Reg was modified and not Temp or vf0
|
||||
if (write.VFreg == 33) xMOVSS(ptr32[&mVU->getVI(REG_I)], reg);
|
||||
else if (write.VFreg == 32) mVUsaveReg(reg, ptr[&mVU->regs().ACC], write.xyzw, 1);
|
||||
else mVUsaveReg(reg, ptr[&mVU->getVF(write.VFreg)], write.xyzw, 1);
|
||||
if (invalidateRegs) {
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
microMapXMM& imap (xmmMap[i]);
|
||||
if ((i == reg.Id) || imap.isNeeded) continue;
|
||||
if (imap.VFreg == write.VFreg) {
|
||||
if (imap.xyzw && imap.xyzw < 0xf) DevCon.Error("microVU Error: writeBackReg() [%d]", imap.VFreg);
|
||||
clearReg(i); // Invalidate any Cached Regs of same vf Reg
|
||||
}
|
||||
}
|
||||
}
|
||||
if (write.xyzw == 0xf) { // Make Cached Reg if All Vectors were Modified
|
||||
write.count = counter;
|
||||
write.xyzw = 0;
|
||||
write.isNeeded = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
clearReg(reg); // Clear Reg
|
||||
}
|
||||
void microRegAlloc::clearNeeded(const xmm& reg)
|
||||
{
|
||||
if ((reg.Id < 0) || (reg.Id >= xmmTotal)) return;
|
||||
|
||||
microMapXMM& clear (xmmMap[reg.Id]);
|
||||
clear.isNeeded = 0;
|
||||
if (clear.xyzw) { // Reg was modified
|
||||
if (clear.VFreg > 0) {
|
||||
int mergeRegs = 0;
|
||||
if (clear.xyzw < 0xf) { mergeRegs = 1; } // Try to merge partial writes
|
||||
for (int i = 0; i < xmmTotal; i++) { // Invalidate any other read-only regs of same vfReg
|
||||
if (i == reg.Id) continue;
|
||||
microMapXMM& imap (xmmMap[i]);
|
||||
if (imap.VFreg == clear.VFreg) {
|
||||
if (imap.xyzw && imap.xyzw < 0xf) DevCon.Error("microVU Error: clearNeeded() [%d]", imap.VFreg);
|
||||
if (mergeRegs == 1) {
|
||||
mVUmergeRegs(xmm(i), reg, clear.xyzw, 1);
|
||||
imap.xyzw = 0xf;
|
||||
imap.count = counter;
|
||||
mergeRegs = 2;
|
||||
}
|
||||
else clearReg(i);
|
||||
}
|
||||
}
|
||||
if (mergeRegs == 2) clearReg(reg); // Clear Current Reg if Merged
|
||||
else if (mergeRegs) writeBackReg(reg); // Write Back Partial Writes if couldn't merge
|
||||
}
|
||||
else clearReg(reg); // If Reg was temp or vf0, then invalidate itself
|
||||
}
|
||||
}
|
||||
const xmm& microRegAlloc::allocReg(int vfLoadReg, int vfWriteReg, int xyzw, bool cloneWrite) {
|
||||
counter++;
|
||||
if (vfLoadReg >= 0) { // Search For Cached Regs
|
||||
for (int i = 0; i < xmmTotal; i++) {
|
||||
const xmm& xmmi(xmm::GetInstance(i));
|
||||
microMapXMM& imap (xmmMap[i]);
|
||||
if ((imap.VFreg == vfLoadReg) && (!imap.xyzw // Reg Was Not Modified
|
||||
|| (imap.VFreg && (imap.xyzw==0xf)))) { // Reg Had All Vectors Modified and != VF0
|
||||
int z = i;
|
||||
if (vfWriteReg >= 0) { // Reg will be modified
|
||||
if (cloneWrite) { // Clone Reg so as not to use the same Cached Reg
|
||||
z = findFreeReg();
|
||||
const xmm& xmmz(xmm::GetInstance(z));
|
||||
writeBackReg(xmmz);
|
||||
if (z!=i && xyzw==8) xMOVAPS (xmmz, xmmi);
|
||||
else if (xyzw == 4) xPSHUF.D(xmmz, xmmi, 1);
|
||||
else if (xyzw == 2) xPSHUF.D(xmmz, xmmi, 2);
|
||||
else if (xyzw == 1) xPSHUF.D(xmmz, xmmi, 3);
|
||||
else if (z != i) xMOVAPS (xmmz, xmmi);
|
||||
imap.count = counter; // Reg i was used, so update counter
|
||||
}
|
||||
else { // Don't clone reg, but shuffle to adjust for SS ops
|
||||
if ((vfLoadReg != vfWriteReg) || (xyzw != 0xf)) { writeBackReg(xmmi); }
|
||||
if (xyzw == 4) xPSHUF.D(xmmi, xmmi, 1);
|
||||
else if (xyzw == 2) xPSHUF.D(xmmi, xmmi, 2);
|
||||
else if (xyzw == 1) xPSHUF.D(xmmi, xmmi, 3);
|
||||
}
|
||||
xmmMap[z].VFreg = vfWriteReg;
|
||||
xmmMap[z].xyzw = xyzw;
|
||||
}
|
||||
xmmMap[z].count = counter;
|
||||
xmmMap[z].isNeeded = 1;
|
||||
return xmm::GetInstance(z);
|
||||
}
|
||||
}
|
||||
}
|
||||
int x = findFreeReg();
|
||||
const xmm& xmmx = xmm::GetInstance(x);
|
||||
writeBackReg(xmmx);
|
||||
|
||||
if (vfWriteReg >= 0) { // Reg Will Be Modified (allow partial reg loading)
|
||||
if ((vfLoadReg == 0) && !(xyzw & 1)) { xPXOR(xmmx, xmmx); }
|
||||
else if (vfLoadReg == 33) mVU->loadIreg(xmmx, xyzw);
|
||||
else if (vfLoadReg == 32) mVUloadReg (xmmx, ptr[&mVU->regs().ACC], xyzw);
|
||||
else if (vfLoadReg >= 0) mVUloadReg (xmmx, ptr[&mVU->getVF(vfLoadReg)], xyzw);
|
||||
xmmMap[x].VFreg = vfWriteReg;
|
||||
xmmMap[x].xyzw = xyzw;
|
||||
}
|
||||
else { // Reg Will Not Be Modified (always load full reg for caching)
|
||||
if (vfLoadReg == 33) mVU->loadIreg(xmmx, 0xf);
|
||||
else if (vfLoadReg == 32) xMOVAPS(xmmx, ptr128[&mVU->regs().ACC]);
|
||||
else if (vfLoadReg >= 0) xMOVAPS(xmmx, ptr128[&mVU->getVF(vfLoadReg)]);
|
||||
xmmMap[x].VFreg = vfLoadReg;
|
||||
xmmMap[x].xyzw = 0;
|
||||
}
|
||||
xmmMap[x].count = counter;
|
||||
xmmMap[x].isNeeded = 1;
|
||||
return xmmx;
|
||||
}
|
||||
@ -248,12 +248,14 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
|
||||
//------------------------------------------------------------------
|
||||
|
||||
// Reg Alloc
|
||||
#define doRegAlloc 1 // Set to 0 to flush every 64bit Instruction
|
||||
static const bool doRegAlloc = 1; // Set to 0 to flush every 32bit Instruction
|
||||
// This turns off reg alloc for the most part, but reg alloc will still
|
||||
// be done between Upper/Lower and within instructions...
|
||||
// be done within instructions... Also on doSwapOp() regAlloc is needed between
|
||||
// Lower and Upper instructions, so in this case it flushes after the full
|
||||
// 64bit instruction (lower and upper)
|
||||
|
||||
// No Flag Optimizations
|
||||
#define noFlagOpts 0 // Set to 1 to disable all flag setting optimizations
|
||||
static const bool noFlagOpts = 0; // Set to 1 to disable all flag setting optimizations
|
||||
// Note: The flag optimizations this disables should all be harmless, so
|
||||
// this option is mainly just for debugging... it effectively forces mVU
|
||||
// to always update Mac and Status Flags (both sticky and non-sticky) whenever
|
||||
@ -261,7 +263,7 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
|
||||
// flag instances between blocks...
|
||||
|
||||
// Constant Propagation
|
||||
#define CHECK_VU_CONSTPROP 0 // Set to 1 to turn on vi15 const propagation
|
||||
static const bool doConstProp = 0; // Set to 1 to turn on vi15 const propagation
|
||||
// Enables Constant Propagation for Jumps based on vi15 'link-register'
|
||||
// allowing us to know many indirect jump target addresses.
|
||||
// Makes GoW a lot slower due to extra recompilation time and extra code-gen!
|
||||
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Reference in New Issue
Block a user