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int -> bool.

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git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1895 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-09-20 21:24:00 +00:00
parent 0f259e62d5
commit 17b8cd9fa3
4 changed files with 41 additions and 43 deletions
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18
pcsx2/Gif.cpp
View File

@ -34,7 +34,7 @@ static int gifstate = GIF_STATE_READY;
//static u64 s_gstag = 0; // used for querying the last tag
// This should be a bool. Next time I feel like breaking the save state, it will be. --arcum42
static int gspath3done = 0;
static bool gspath3done = false;
static u32 gscycles = 0, prevcycles = 0, mfifocycles = 0;
static u32 gifqwc = 0;
@ -67,7 +67,7 @@ __forceinline void gsInterrupt()
if (Path3progress == STOPPED_MODE) gifRegs->stat._u32 &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
if ((gif->qwc > 0) || (gspath3done == 0))
if ((gif->qwc > 0) || (!gspath3done))
{
if (!dmacRegs->ctrl.DMAE)
{
@ -81,7 +81,7 @@ __forceinline void gsInterrupt()
return;
}
gspath3done = 0;
gspath3done = false;
gscycles = 0;
gif->chcr.STR = 0;
vif1Regs->stat &= ~VIF1_STAT_VGW;
@ -140,7 +140,7 @@ static __forceinline bool checkTieBit(u32* &ptag)
if (gif->chcr.TIE && (Tag::IRQ(ptag))) //Check TIE bit of CHCR and IRQ bit of tag
{
GIF_LOG("dmaIrq Set");
gspath3done = 1;
gspath3done = true;
return true;
}
@ -251,7 +251,7 @@ void GIFdma()
return;
}
if ((gif->chcr.MOD == CHAIN_MODE) && (gspath3done == 0)) // Chain Mode
if ((gif->chcr.MOD == CHAIN_MODE) && (!gspath3done)) // Chain Mode
{
if (!ReadTag(ptag, id)) return;
GIF_LOG("gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx", ptag[1], ptag[0], gif->qwc, id, gif->madr);
@ -277,7 +277,7 @@ void GIFdma()
prevcycles = 0;
if ((gspath3done == 0) && (gif->qwc == 0))
if ((!gspath3done) && (gif->qwc == 0))
{
ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
@ -305,7 +305,7 @@ void dmaGIF()
GIF_LOG("dmaGIFstart chcr = %lx, madr = %lx, qwc = %lx\n tadr = %lx, asr0 = %lx, asr1 = %lx", gif->chcr._u32, gif->madr, gif->qwc, gif->tadr, gif->asr0, gif->asr1);
Path3progress = STOPPED_MODE;
gspath3done = 0; // For some reason this doesn't clear? So when the system starts the thread, we will clear it :)
gspath3done = false; // For some reason this doesn't clear? So when the system starts the thread, we will clear it :)
gifRegs->stat.P3Q = 1;
gifRegs->stat.FQC |= 0x10;// FQC=31, hack ;) ( 31? 16! arcum42) [used to be 0xE00; // OPH=1 | APATH=3]
@ -332,7 +332,7 @@ void dmaGIF()
}
//Halflife sets a QWC amount in chain mode, no tadr set.
if (gif->qwc > 0) gspath3done = 1;
if (gif->qwc > 0) gspath3done = true;
GIFdma();
}
@ -558,7 +558,7 @@ void gifMFIFOInterrupt()
//if(gifqwc > 0) Console::WriteLn("GIF MFIFO ending with stuff in it %x", gifqwc);
if (!gifmfifoirq) gifqwc = 0;
gspath3done = 0;
gspath3done = false;
gscycles = 0;
gifRegs->stat._u32 &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); // OPH, APATH, P3Q, FQC = 0

13
pcsx2/IopDma.cpp
View File

@ -23,9 +23,8 @@ using namespace R3000A;
// Dma8 in PsxSpd.c
// Dma11/12 in PsxSio2.c
// Should be a bool, and will be next time I break savestate. --arcum42
int iopsifbusy[2] = { 0, 0 };
extern int eesifbusy[2];
bool iopsifbusy[2] = { false, false };
extern bool eesifbusy[2];
static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _SPU2writeDMA4Mem spu2WriteFunc, _SPU2readDMA4Mem spu2ReadFunc)
{
@ -166,10 +165,10 @@ void psxDma9(u32 madr, u32 bcr, u32 chcr)
{
SIF_LOG("IOP: dmaSIF0 chcr = %lx, madr = %lx, bcr = %lx, tadr = %lx", chcr, madr, bcr, HW_DMA9_TADR);
iopsifbusy[0] = 1;
iopsifbusy[0] = true;
psHu32(SBUS_F240) |= 0x2000;
if (eesifbusy[0] == 1)
if (eesifbusy[0])
{
SIF0Dma();
psHu32(SBUS_F240) &= ~0x20;
@ -181,10 +180,10 @@ void psxDma10(u32 madr, u32 bcr, u32 chcr)
{
SIF_LOG("IOP: dmaSIF1 chcr = %lx, madr = %lx, bcr = %lx", chcr, madr, bcr);
iopsifbusy[1] = 1;
iopsifbusy[1] = true;
psHu32(SBUS_F240) |= 0x4000;
if (eesifbusy[1] == 1)
if (eesifbusy[1])
{
FreezeXMMRegs(1);
SIF1Dma();

25
pcsx2/SPR.cpp
View File

@ -23,9 +23,8 @@
extern void mfifoGIFtransfer(int);
/* Both of these should be bools. Again, next savestate break. --arcum42 */
static int spr0finished = 0;
static int spr1finished = 0;
static bool spr0finished = false;
static bool spr1finished = false;
static u32 mfifotransferred = 0;
@ -132,7 +131,7 @@ void _SPR0interleave()
}
spr0->qwc = 0;
spr0finished = 1;
spr0finished = true;
}
static __forceinline void _dmaSPR0()
@ -148,7 +147,7 @@ static __forceinline void _dmaSPR0()
case NORMAL_MODE:
{
SPR0chain();
spr0finished = 1;
spr0finished = true;
return;
}
case CHAIN_MODE:
@ -160,7 +159,7 @@ static __forceinline void _dmaSPR0()
if (spr0->qwc > 0)
{
SPR0chain();
spr0finished = 1;
spr0finished = true;
return;
}
// Destination Chain Mode
@ -201,7 +200,7 @@ static __forceinline void _dmaSPR0()
done = TRUE;
}
spr0finished = (done) ? 1 : 0;
spr0finished = done;
if (!done)
{
@ -254,7 +253,7 @@ void SPRFROMinterrupt()
break;
}
}
if (spr0finished == 0) return;
if (!spr0finished) return;
spr0->chcr.STR = 0;
hwDmacIrq(DMAC_FROM_SPR);
}
@ -329,7 +328,7 @@ void _SPR1interleave()
}
spr1->qwc = 0;
spr1finished = 1;
spr1finished = true;
}
void _dmaSPR1() // toSPR work function
@ -341,7 +340,7 @@ void _dmaSPR1() // toSPR work function
//int cycles = 0;
// Transfer Dn_QWC from Dn_MADR to SPR1
SPR1chain();
spr1finished = 1;
spr1finished = true;
return;
}
case CHAIN_MODE:
@ -354,7 +353,7 @@ void _dmaSPR1() // toSPR work function
{
// Transfer Dn_QWC from Dn_MADR to SPR1
SPR1chain();
spr1finished = 1;
spr1finished = true;
return;
}
// Chain Mode
@ -364,7 +363,7 @@ void _dmaSPR1() // toSPR work function
if (!(Tag::Transfer("SPR1 Tag", spr1, ptag)))
{
done = true;
spr1finished = (done) ? 1: 0;
spr1finished = done;
}
id = Tag::Id(ptag);
@ -432,7 +431,7 @@ void dmaSPR1() // toSPR
void SPRTOinterrupt()
{
_dmaSPR1();
if (spr1finished == 0) return;
if (!spr1finished) return;
spr1->chcr.STR = 0;
hwDmacIrq(DMAC_TO_SPR);
}

28
pcsx2/Sif.cpp
View File

@ -59,8 +59,8 @@ struct _sif1
static _sif0 sif0;
static _sif1 sif1;
int eesifbusy[2] = { 0, 0 };
extern int iopsifbusy[2];
bool eesifbusy[2] = { false, false };
extern bool iopsifbusy[2];
void sifInit()
{
@ -132,7 +132,7 @@ __forceinline void SIF0Dma()
do
{
if (iopsifbusy[0] == 1) // If EE SIF0 is enabled
if (iopsifbusy[0]) // If EE SIF0 is enabled
{
if (sif0.counter == 0) // If there's no more to transfer
{
@ -143,7 +143,7 @@ __forceinline void SIF0Dma()
SIF_LOG(" IOP SIF Stopped");
// Stop & signal interrupts on IOP
iopsifbusy[0] = 0;
iopsifbusy[0] = false;
// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords)
// So when we're all done, the equation looks like thus:
@ -187,7 +187,7 @@ __forceinline void SIF0Dma()
}
}
if (eesifbusy[0] == 1) // If EE SIF enabled and there's something to transfer
if (eesifbusy[0]) // If EE SIF enabled and there's something to transfer
{
int size = sif0dma->qwc;
if (dmacRegs->ctrl.STS == STS_SIF0) // STS == fromSIF0
@ -226,7 +226,7 @@ __forceinline void SIF0Dma()
else
SIF_LOG(" EE SIF interrupt");
eesifbusy[0] = 0;
eesifbusy[0] = false;
CPU_INT(5, cycles*BIAS);
done = true;
}
@ -263,7 +263,7 @@ __forceinline void SIF1Dma()
int cycles = 0, psxCycles = 0;
do
{
if (eesifbusy[1] == 1) // If EE SIF1 is enabled
if (eesifbusy[1]) // If EE SIF1 is enabled
{
if (dmacRegs->ctrl.STD == STD_SIF1)
@ -275,7 +275,7 @@ __forceinline void SIF1Dma()
{
// Stop & signal interrupts on EE
SIF_LOG("EE SIF1 End %x", sif1.end);
eesifbusy[1] = 0;
eesifbusy[1] = false;
done = true;
CPU_INT(6, cycles*BIAS);
sif1.chain = 0;
@ -368,7 +368,7 @@ __forceinline void SIF1Dma()
}
}
if (iopsifbusy[1] == 1) // If IOP SIF enabled and there's something to transfer
if (iopsifbusy[1]) // If IOP SIF enabled and there's something to transfer
{
int size = sif1.counter;
@ -396,7 +396,7 @@ __forceinline void SIF1Dma()
else
SIF_LOG(" IOP SIF interrupt");
iopsifbusy[1] = 0;
iopsifbusy[1] = false;
PSX_INT(IopEvt_SIF1, psxCycles);
sif1.tagMode = 0;
done = true;
@ -452,8 +452,8 @@ __forceinline void dmaSIF0()
}
psHu32(SBUS_F240) |= 0x2000;
eesifbusy[0] = 1;
if (iopsifbusy[0] == 1)
eesifbusy[0] = true;
if (iopsifbusy[0])
{
FreezeXMMRegs(1);
hwIntcIrq(INTC_SBUS);
@ -475,8 +475,8 @@ __forceinline void dmaSIF1()
}
psHu32(SBUS_F240) |= 0x4000;
eesifbusy[1] = 1;
if (iopsifbusy[1] == 1)
eesifbusy[1] = true;
if (iopsifbusy[1])
{
FreezeXMMRegs(1);
SIF1Dma();