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Apply r1046 to ZeroGS DX as well. Ifdef a few things from r1047 so Linux compiles. A few minor changes.

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git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1048 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-04-23 13:15:44 +00:00
parent ef565303a5
commit 52fcc69628
8 changed files with 53 additions and 47 deletions
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40
pcsx2/COP0.cpp
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@ -308,8 +308,8 @@ namespace COP0 {
void MFC0()
{
// Note on _Rd_ Condition 9: CP0.Count should be updated even if _Rt_ is 0.
if( (_Rd_ != 9) && !_Rt_ ) return;
if(_Rd_ != 9) { COP0_LOG("%s", disR5900Current.getCString() ); }
if ((_Rd_ != 9) && !_Rt_ ) return;
if (_Rd_ != 9) { COP0_LOG("%s", disR5900Current.getCString() ); }
//if(bExecBIOS == FALSE && _Rd_ == 25) Console::WriteLn("MFC0 _Rd_ %x = %x", params _Rd_, cpuRegs.CP0.r[_Rd_]);
switch (_Rd_)
@ -412,33 +412,40 @@ int CPCOND0() {
//#define CPCOND0 1
#define BC0(cond) \
/*#define BC0(cond) \
if (CPCOND0() cond) { \
intDoBranch(_BranchTarget_); \
}
}*/
void BC0F() {
BC0(== 0);
if (CPCOND0() == 0) intDoBranch(_BranchTarget_);
COP0_LOG( "COP0 > BC0F" );
}
void BC0T() {
BC0(== 1);
if (CPCOND0() == 1) intDoBranch(_BranchTarget_);
COP0_LOG( "COP0 > BC0T" );
}
#define BC0L(cond) \
/*#define BC0L(cond) \
if (CPCOND0() cond) { \
intDoBranch(_BranchTarget_); \
} else cpuRegs.pc+= 4;
} else cpuRegs.pc+= 4;*/
void BC0FL() {
BC0L(== 0);
if (CPCOND0() == 0)
intDoBranch(_BranchTarget_);
else
cpuRegs.pc+= 4;
COP0_LOG( "COP0 > BC0FL" );
}
void BC0TL() {
BC0L(== 1);
if (CPCOND0() == 1)
intDoBranch(_BranchTarget_);
else
cpuRegs.pc+= 4;
COP0_LOG( "COP0 > BCOTL" );
}
@ -487,8 +494,7 @@ void TLBWR() {
void TLBP() {
int i;
union {
struct {
u32 VPN2:19;
@ -499,13 +505,13 @@ void TLBP() {
u32 u;
} EntryHi32;
EntryHi32.u=cpuRegs.CP0.n.EntryHi;
EntryHi32.u = cpuRegs.CP0.n.EntryHi;
cpuRegs.CP0.n.Index=0xFFFFFFFF;
for(i=0;i<48;i++){
if(tlb[i].VPN2==((~tlb[i].Mask)&(EntryHi32.s.VPN2))
&&((tlb[i].G&1)||((tlb[i].ASID & 0xff) == EntryHi32.s.ASID))) {
cpuRegs.CP0.n.Index=i;
if (tlb[i].VPN2 == ((~tlb[i].Mask) & (EntryHi32.s.VPN2))
&& ((tlb[i].G&1) || ((tlb[i].ASID & 0xff) == EntryHi32.s.ASID))) {
cpuRegs.CP0.n.Index = i;
break;
}
}

6
pcsx2/COP2.cpp
View File

@ -25,10 +25,6 @@
#include "VUops.h"
#include "VUmicro.h"
//namespace R5900 {
//namespace Interpreter {
//namespace OpcodeImpl{
using namespace R5900;
using namespace R5900::Interpreter;
@ -85,5 +81,3 @@ void BC2TL()
cpuRegs.pc+= 4;
}
}
//}}}

14
pcsx2/MMI.cpp
View File

@ -177,11 +177,15 @@ void PLZCW() {
_PLZCW (1);
}
#define PMFHL_CLAMP(dst, src) \
if ((int)src > (int)0x00007fff) dst = 0x7fff; \
else \
if ((int)src < (int)0xffff8000) dst = 0x8000; \
else dst = (u16)src;
__forceinline void PMFHL_CLAMP(u16 dst, u16 src)
{
if ((int)src > (int)0x00007fff)
dst = 0x7fff;
else if ((int)src < (int)0xffff8000)
dst = 0x8000;
else
dst = (u16)src;
}
void PMFHL() {
if (!_Rd_) return;

12
pcsx2/R3000A.h
View File

@ -126,14 +126,14 @@ extern s32 psxCycleEE; // tracks IOP's current sych status with the EE
#ifndef _PC_
#define _i32(x) (s32)x
#define _u32(x) (u32)x
#define _i32(x) (s32)x //R3000A
#define _u32(x) (u32)x //R3000A
#define _i16(x) (s16)x
#define _u16(x) (u16)x
#define _i16(x) (s16)x // Not used
#define _u16(x) (u16)x // Not used
#define _i8(x) (s8)x
#define _u8(x) (u8)x
#define _i8(x) (s8)x // Not used
#define _u8(x) (u8)x //R3000A - once
/**** R3000A Instruction Macros ****/
#define _PC_ psxRegs.pc // The next PC to be executed

14
pcsx2/R5900.h
View File

@ -121,16 +121,16 @@ union CP0regs {
};
struct cpuRegisters {
GPRregs GPR; // GPR regs
GPRregs GPR; // GPR regs
// NOTE: don't change order since recompiler uses it
GPR_reg HI;
GPR_reg LO; // hi & log 128bit wide
CP0regs CP0; // is COP0 32bit?
u32 sa; // shift amount (32bit), needs to be 16 byte aligned
u32 IsDelaySlot; // set true when the current instruction is a delay slot.
u32 pc; // Program counter, when changing offset in struct, check iR5900-X.S to make sure offset is correct
u32 code; // current instruction
PERFregs PERF;
u32 pc; // Program counter, when changing offset in struct, check iR5900-X.S to make sure offset is correct
u32 code; // current instruction
PERFregs PERF;
u32 eCycle[32];
u32 sCycle[32]; // for internal counters
u32 cycle; // calculate cpucycles..
@ -180,7 +180,7 @@ struct tlbs
#ifndef _PC_
#define _i64(x) (s64)x
/*#define _i64(x) (s64)x
#define _u64(x) (u64)x
#define _i32(x) (s32)x
@ -190,12 +190,12 @@ struct tlbs
#define _u16(x) (u16)x
#define _i8(x) (s8)x
#define _u8(x) (u8)x
#define _u8(x) (u8)x*/
////////////////////////////////////////////////////////////////////
// R5900 Instruction Macros
#define _PC_ cpuRegs.pc // The next PC to be executed
#define _PC_ cpuRegs.pc // The next PC to be executed - only used in this header and R3000A.h
#define _Funct_ ((cpuRegs.code ) & 0x3F) // The funct part of the instruction register
#define _Rd_ ((cpuRegs.code >> 11) & 0x1F) // The rd part of the instruction register

6
pcsx2/x86/ix86/Makefile.am
View File

@ -2,9 +2,9 @@ INCLUDES = -I@srcdir@/.. -I@srcdir@/../../ -I@srcdir@/../../../common/include
noinst_LIBRARIES = libix86.a
libix86_a_SOURCES = \
ix86.cpp ix86_cpudetect.cpp ix86_fpu.cpp ix86_jmp.cpp ix86_legacy_mmx.cpp ix86_tools.cpp ix86_3dnow.cpp \
ix86_legacy.cpp ix86_legacy_sse.cpp \
ix86.cpp ix86_cpudetect.cpp ix86_fpu.cpp ix86_jmp.cpp ix86_tools.cpp ix86_3dnow.cpp \
ix86_legacy.cpp ix86_legacy_sse.cpp ix86_simd.cpp \
ix86_internal.h ix86_legacy_instructions.h ix86_macros.h ix86_sse_helpers.h ix86.h ix86_legacy_internal.h \
ix86_instructions.h ix86_legacy_types.h ix86_types.h \
bittest.h dwshift.h group1.h group2.h group3.h incdec.h jmpcall.h movs.h test.h \
movqss.h arithmetic.h shufflepack.h basehelpers.h comparisons.h moremovs.h
movqss.h arithmetic.h shufflepack.h basehelpers.h comparisons.h moremovs.h xchg.h

6
pcsx2/x86/ix86/implement/xmm/moremovs.h
View File

@ -122,7 +122,7 @@ public:
{
if( to != from ) xOpWrite0F( PrefixA, Opcode, to, from );
}
#ifndef __LINUX__ // Ifdef till Jake fixes; you can't use & on a const void*!
__forceinline void operator()( const xRegisterSSE& to, const void* from ) const
{
xOpWrite0F( (isAligned || (from & 0x0f) == 0) ? PrefixA : PrefixU, Opcode, to, from );
@ -132,7 +132,7 @@ public:
{
xOpWrite0F( (isAligned || (from & 0x0f) == 0) ? PrefixA : PrefixU, Opcode_Alt, to, from );
}
#endif
__forceinline void operator()( const xRegisterSSE& to, const ModSibBase& from ) const
{
// ModSib form is aligned if it's displacement-only and the displacement is aligned:
@ -140,12 +140,14 @@ public:
xOpWrite0F( isReallyAligned ? PrefixA : PrefixU, Opcode, to, from );
}
#ifndef __LINUX__ // II'll ifdef this one, too. xOpWrite0F doesn't take ModSibBase & xRegisterSSE in that order.
__forceinline void operator()( const ModSibBase& to, const xRegisterSSE& from ) const
{
// ModSib form is aligned if it's displacement-only and the displacement is aligned:
bool isReallyAligned = isAligned || ( (to.Displacement & 0x0f) == 0 && to.Index.IsEmpty() && to.Base.IsEmpty() );
xOpWrite0F( isReallyAligned ? PrefixA : PrefixU, Opcode_Alt, to, from );
}
#endif
};

2
plugins/zerogs/dx/GSmain.cpp
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@ -842,7 +842,7 @@ void _GSgifTransfer(pathInfo *path, u32 *pMem, u32 size)
continue;
}
break;
continue;
}
}