SPU2-X: Testing showed that writing effect area registers is not entirely ineffective as previously assumed while effect area writing is enabled on that core. The new assumption is that internal registers reflect the values of the external ones while effect area writing is disabled. Also increased logging level of these registers.

Save state compatibility broken.

Fixes issue 796, grandia 3 noise before squenix logo.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4759 96395faa-99c1-11dd-bbfe-3dabce05a288

plugins/spu2-x/src/RegLog.cpp

@@ -206,13 +206,13 @@ void SPU2writeLog( const char* action, u32 rmem, u16 value )
 				RegLog(3,"STATX",rmem,core,value);
 				break;
 			case REG_A_ESA:
-				RegLog(1,"ESAH",rmem,core,value);
+				RegLog(2,"ESAH",rmem,core,value);
 				break;
 			case (REG_A_ESA + 2):
-				RegLog(1,"ESAL",rmem,core,value);
+				RegLog(2,"ESAL",rmem,core,value);
 				break;
 			case REG_A_EEA:
-				RegLog(1,"EEAH",rmem,core,value);
+				RegLog(2,"EEAH",rmem,core,value);
 				break;
 
 	#define LOG_REVB_REG(n,t) \

plugins/spu2-x/src/RegTable.cpp

@@ -95,8 +95,8 @@ u16 const* const regtable_original[0x401] =
 	PVCA(0,12),PVCA(0,13),PVCA(0,14),PVCA(0,15),PVCA(0,16),PVCA(0,17),
 	PVCA(0,18),PVCA(0,19),PVCA(0,20),PVCA(0,21),PVCA(0,22),PVCA(0,23),
 
-	PCORE(0,EffectsStartA)+1,
-	PCORE(0,EffectsStartA),
+	PCORE(0,ExtEffectsStartA)+1,
+	PCORE(0,ExtEffectsStartA),
 
 	PREVB_REG(0,FB_SRC_A),
 	PREVB_REG(0,FB_SRC_B),
@@ -121,8 +121,8 @@ u16 const* const regtable_original[0x401] =
 	PREVB_REG(0,MIX_DEST_B0),
 	PREVB_REG(0,MIX_DEST_B1),
 
-	PCORE(0,EffectsEndA)+1,
-	PCORE(0,EffectsEndA),
+	PCORE(0,ExtEffectsEndA)+1,
+	PCORE(0,ExtEffectsEndA),
 
 	PCORE(0,Regs.ENDX),
 	PCORE(0,Regs.ENDX)+1,
@@ -198,8 +198,8 @@ u16 const* const regtable_original[0x401] =
 	PVCA(1,12),PVCA(1,13),PVCA(1,14),PVCA(1,15),PVCA(1,16),PVCA(1,17),
 	PVCA(1,18),PVCA(1,19),PVCA(1,20),PVCA(1,21),PVCA(1,22),PVCA(1,23),
 
-	PCORE(1,EffectsStartA)+1,
-	PCORE(1,EffectsStartA),
+	PCORE(1,ExtEffectsStartA)+1,
+	PCORE(1,ExtEffectsStartA),
 
 	PREVB_REG(1,FB_SRC_A),
 	PREVB_REG(1,FB_SRC_B),
@@ -224,8 +224,8 @@ u16 const* const regtable_original[0x401] =
 	PREVB_REG(1,MIX_DEST_B0),
 	PREVB_REG(1,MIX_DEST_B1),
 
-	PCORE(1,EffectsEndA)+1,
-	PCORE(1,EffectsEndA),
+	PCORE(1,ExtEffectsEndA)+1,
+	PCORE(1,ExtEffectsEndA),
 
 	PCORE(1,Regs.ENDX),
 	PCORE(1,Regs.ENDX)+1,

plugins/spu2-x/src/defs.h

@@ -407,6 +407,8 @@ struct V_Core
 	V_ReverbBuffers	RevBuffers;		// buffer pointers for reverb, pre-calculated and pre-clipped.
 	u32				EffectsStartA;
 	u32				EffectsEndA;
+	u32				ExtEffectsStartA;
+	u32				ExtEffectsEndA;
 	u32				ReverbX;
 
 	// Current size of the effects buffer.  Pre-caculated when the effects start

plugins/spu2-x/src/spu2freeze.cpp

@@ -25,7 +25,7 @@ namespace Savestate
 
 	// versioning for saves.
 	// Increment this when changes to the savestate system are made.
-	static const u32 SAVE_VERSION = 0x0008;
+	static const u32 SAVE_VERSION = 0x0009;
 
 	static void wipe_the_cache()
 	{

plugins/spu2-x/src/spu2sys.cpp

@@ -144,6 +144,8 @@ void V_Core::Init( int index )
 	Regs.VMIXER		= 0xFFFFFF;
 	EffectsStartA	= c ? 0xFFFF8 : 0xEFFF8;
 	EffectsEndA		= c ? 0xFFFFF : 0xEFFFF;
+	ExtEffectsStartA = EffectsStartA;
+	ExtEffectsEndA = EffectsEndA;
 
 	FxEnable		= 0; // Uninitialized it's 0 for both cores. Resetting libs however may set this to 0 or 1.
 	// These are real PS2 values, mainly constant apart from a few bits: 0x3220EAA4, 0x40505E9C.
@@ -257,13 +259,13 @@ void V_Core::UpdateEffectsBufferSize()
 {
 	const s32 newbufsize = EffectsEndA - EffectsStartA + 1;
 	//printf("Rvb Area change: ESA = %x, EEA = %x, Size(dec) = %d, Size(hex) = %x FxEnable = %d\n", EffectsStartA, EffectsEndA, newbufsize * 2, newbufsize * 2, FxEnable);
-	
+
 	if( (newbufsize*2) > 0x20000 ) // max 128kb per core
 	{ 
 		//printf("too big, returning\n");
 		//return;
 	}
-	if( !RevBuffers.NeedsUpdated && (newbufsize == EffectsBufferSize) ) return;
+	if (newbufsize == EffectsBufferSize) return;
 	
 	RevBuffers.NeedsUpdated = false;
 	EffectsBufferSize = newbufsize;
@@ -693,12 +695,17 @@ u16 V_Core::ReadRegPS1(u32 mem)
 		case 0x1d9e: value = Regs.VMIXL>>16;     break;
 
 		case 0x1da2:
+#if 0
+			// This smells of old hack
 			if( value != EffectsStartA>>3 )
 			{
 				value = EffectsStartA>>3;
 				UpdateEffectsBufferSize();
 				ReverbX = 0;
 			}
+#else
+			value = EffectsStartA >> 3;
+#endif
 		break;
 		case 0x1da4: value = IRQA>>3;            break;
 		case 0x1da6: value = TSA>>3;             break;
@@ -906,6 +913,7 @@ static void __fastcall RegWrite_Core( u16 value )
 		{
 			bool irqe		= thiscore.IRQEnable;
 			int bit0		= thiscore.AttrBit0;
+			bool fxenable	= thiscore.FxEnable;
 			u8 oldDmaMode	= thiscore.DmaMode;
 			
 			thiscore.AttrBit0   =(value>> 0) & 0x01; //1 bit
@@ -922,6 +930,16 @@ static void __fastcall RegWrite_Core( u16 value )
 				thiscore.Regs.STATX = 0;
 			thiscore.Regs.ATTR  =value&0x7fff;
 
+			if (fxenable && !thiscore.FxEnable
+				&& (thiscore.EffectsStartA != thiscore.ExtEffectsStartA
+				 || thiscore.EffectsEndA   != thiscore.ExtEffectsEndA))
+			{
+				thiscore.EffectsStartA = thiscore.ExtEffectsStartA;
+				thiscore.EffectsEndA = thiscore.ExtEffectsEndA;
+				thiscore.ReverbX = 0;
+				thiscore.RevBuffers.NeedsUpdated = true;
+			}
+
 			if(oldDmaMode != thiscore.DmaMode)
 			{
 				// FIXME... maybe: if this mode was cleared in the middle of a DMA, should we interrupt it?
@@ -944,13 +962,6 @@ static void __fastcall RegWrite_Core( u16 value )
 				
 				if(!thiscore.IRQEnable)
 					Spdif.Info &= ~(4 << thiscore.Index);
-	
-				// Hack for F1 2005.
-				//if (thiscore.IRQEnable && (thiscore.IRQA == thiscore.EffectsStartA + thiscore.ReverbX))
-				//{
-				//	printf("F1 2005 IRQ Hack (Reverb). IRQA = %x\n",thiscore.IRQA);
-				//	SetIrqCall(core);
-				//}
 			}
 
 		}
@@ -1082,6 +1093,9 @@ static void __fastcall RegWrite_Core( u16 value )
 		// Reverb Start and End Address Writes!
 		//  * These regs are only writable when Effects are *DISABLED* (FxEnable is false).
 		//    Writes while enabled should be ignored.
+		//    NOTE: Above is false by testing but there are references saying this, so for
+		//    now we think that writing is allowed but the internal register doesn't reflect
+		//    the value until effects area writing is disabled.
 		//  * Yes, these are backwards from all the volumes -- the hiword comes FIRST (wtf!)
 		//  * End position is a hiword only!  Loword is always ffff.
 		//  * The Reverb buffer position resets on writes to StartA.  It probably resets
@@ -1089,27 +1103,30 @@ static void __fastcall RegWrite_Core( u16 value )
 		//    change the end address anyway.
 		//
 		case REG_A_ESA:
+			SetHiWord( thiscore.ExtEffectsStartA, value );
 			if (!thiscore.FxEnable)
 			{
-				SetHiWord( thiscore.EffectsStartA, value );
+				thiscore.EffectsStartA = thiscore.ExtEffectsStartA;
 				thiscore.ReverbX = 0;
 				thiscore.RevBuffers.NeedsUpdated = true;
 			}
 		break;
 
 		case (REG_A_ESA + 2):
+			SetLoWord( thiscore.ExtEffectsStartA, value );
 			if (!thiscore.FxEnable)
 			{
-				SetLoWord( thiscore.EffectsStartA, value );
+				thiscore.EffectsStartA = thiscore.ExtEffectsStartA;
 				thiscore.ReverbX = 0;
 				thiscore.RevBuffers.NeedsUpdated = true;
 			}
 		break;
 
 		case REG_A_EEA:
+			thiscore.ExtEffectsEndA = ((u32)value<<16) | 0xFFFF;
 			if (!thiscore.FxEnable)
 			{
-				thiscore.EffectsEndA = ((u32)value<<16) | 0xFFFF;
+				thiscore.EffectsEndA = thiscore.ExtEffectsEndA;
 				thiscore.ReverbX = 0;
 				thiscore.RevBuffers.NeedsUpdated = true;
 			}