mirror of
https://github.com/libretro/pcsx2.git
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4457fe40fc
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2897 96395faa-99c1-11dd-bbfe-3dabce05a288
294 lines
7.4 KiB
C
294 lines
7.4 KiB
C
/* SPU2null
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* Copyright (C) 2002-2005 SPU2null Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __SPU2_H__
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#define __SPU2_H__
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#define _CRT_SECURE_NO_DEPRECATE
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#include <stdio.h>
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#include <string.h>
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extern "C"
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{
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#define SPU2defs
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#include "PS2Edefs.h"
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}
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#ifdef __LINUX__
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#include <gtk/gtk.h>
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#else
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#include <windows.h>
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#include <windowsx.h>
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#endif
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#ifdef _MSC_VER
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#define EXPORT_C_(type) extern "C" __declspec(dllexport) type CALLBACK
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#else
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#define EXPORT_C_(type) extern "C" type
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#endif
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extern FILE *spu2Log;
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#define SPU2_LOG __Log //debug mode
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extern const u8 version;
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extern const u8 revision;
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extern const u8 build;
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extern const u32 minor;
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extern char *libraryName;
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typedef struct
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{
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s32 Log;
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} Config;
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extern Config conf;
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void __Log(char *fmt, ...);
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void SaveConfig();
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void LoadConfig();
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void SysMessage(char *fmt, ...);
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////////////////////
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// SPU2 Registers //
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////////////////////
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#define REG_VP_VOLL 0x0000
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#define REG_VP_VOLR 0x0002
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#define REG_VP_PITCH 0x0004
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#define REG_VP_ADSR1 0x0006
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#define REG_VP_ADSR2 0x0008
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#define REG_VP_ENVX 0x000A
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#define REG_VP_VOLXL 0x000C
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#define REG_VP_VOLXR 0x000E
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#define REG_C0_FMOD1 0x0180
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#define REG_C0_FMOD2 0x0182
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#define REG_C1_FMOD1 0x0580
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#define REG_C1_FMOD2 0x0582
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#define REG_S_NON 0x0184
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#define REG_S_VMIXL 0x0188
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#define REG_S_VMIXEL 0x018C
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#define REG_S_VMIXR 0x0190
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#define REG_S_VMIXER 0x0194
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#define REG_C0_MMIX 0x0198
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#define REG_C1_MMIX 0x0598
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#define REG_C0_CTRL 0x019A
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#define REG_C0_IRQA_HI 0x019C
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#define REG_C0_IRQA_LO 0x019D
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#define REG_C1_IRQA_HI 0x059C
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#define REG_C1_IRQA_LO 0x059D
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#define REG_C0_SPUON1 0x1A0
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#define REG_C0_SPUON2 0x1A2
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#define REG_C1_SPUON1 0x5A0
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#define REG_C1_SPUON2 0x5A2
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#define REG_C0_SPUOFF1 0x1A4
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#define REG_C0_SPUOFF2 0x1A6
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#define REG_C1_SPUOFF1 0x5A4
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#define REG_C1_SPUOFF2 0x5A6
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#define REG_C0_SPUADDR_HI 0x01A8
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#define REG_C0_SPUADDR_LO 0x01AA
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#define REG_C1_SPUADDR_HI 0x05A8
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#define REG_C1_SPUADDR_LO 0x05AA
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#define REG_C0_SPUDATA 0x01AC
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#define REG_C1_SPUDATA 0x05AC
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#define REG_C0_DMACTRL 0x01AE
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#define REG_C1_DMACTRL 0x05AE
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#define REG_C0_ADMAS 0x01B0
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#define REG_VA_SSA 0x01C0
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#define REG_VA_LSAX 0x01C4
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#define REG_VA_NAX 0x01C8
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#define REG_A_ESA 0x02E0
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#define REG_A_EEA 0x033C
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#define REG_C0_END1 0x0340
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#define REG_C0_END2 0x0342
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#define REG_C1_END1 0x0740
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#define REG_C1_END2 0x0742
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#define REG_C0_SPUSTAT 0x0344 //not sure!
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#define REG_C1_CTRL 0x059A
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#define REG_C1_ADMAS 0x05B0
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#define REG_C1_SPUSTAT 0x0744 //not sure!
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#define REG_P_MVOLL 0x0760
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#define REG_P_MVOLR 0x0762
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#define REG_P_EVOLL 0x0764
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#define REG_P_EVOLR 0x0766
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#define REG_P_AVOLL 0x0768
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#define REG_P_AVOLR 0x076A
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#define REG_P_BVOLL 0x076C
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#define REG_P_BVOLR 0x076E
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#define REG_P_MVOLXL 0x0770
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#define REG_P_MVOLXR 0x0772
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#define SPDIF_OUT 0x07C0
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#define REG_IRQINFO 0x07C2
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#define SPDIF_MODE 0x07C6
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#define SPDIF_MEDIA 0x07C8
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#define spu2Rs16(mem) (*(s16*)&spu2regs[(mem) & 0xffff])
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#define spu2Ru16(mem) (*(u16*)&spu2regs[(mem) & 0xffff])
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//#define spu2Rs32(mem) (*(s32*)&spu2regs[(mem) & 0xffff])
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//#define spu2Ru32(mem) (*(u32*)&spu2regs[(mem) & 0xffff])
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#define IRQINFO spu2Ru16(REG_IRQINFO)
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#define SPU2_GET32BIT(lo,hi) (((u32)(spu2Ru16(hi)&0x3f)<<16)|(u32)spu2Ru16(lo))
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#define SPU2_SET32BIT(value, lo, hi) { \
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spu2Ru16(hi) = ((value)>>16)&0x3f; \
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spu2Ru16(lo) = (value)&0xffff; \
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} \
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#define C0_IRQA SPU2_GET32BIT(REG_C0_IRQA_LO, REG_C0_IRQA_HI)
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#define C1_IRQA SPU2_GET32BIT(REG_C1_IRQA_LO, REG_C1_IRQA_HI)
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#define C0_SPUADDR SPU2_GET32BIT(REG_C0_SPUADDR_LO, REG_C0_SPUADDR_HI)
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#define C1_SPUADDR SPU2_GET32BIT(REG_C1_SPUADDR_LO, REG_C1_SPUADDR_HI)
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#define C0_SPUADDR_SET(value) SPU2_SET32BIT(value, REG_C0_IRQA_LO, REG_C0_IRQA_HI)
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#define C1_SPUADDR_SET(value) SPU2_SET32BIT(value, REG_C1_IRQA_LO, REG_C1_IRQA_HI)
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#define SPU_NUMBER_VOICES 48
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struct SPU_CONTROL_
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{
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u16 spuon : 1;
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u16 spuUnmute : 1;
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u16 noiseFreq : 6;
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u16 reverb : 1;
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u16 irq : 1;
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u16 dma : 2; // 1 - no dma, 2 - write, 3 - read
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u16 extr : 1; // external reverb
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u16 cdreverb : 1;
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u16 extAudio : 1;
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u16 extCd : 1;
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};
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// the layout of each voice in wSpuRegs
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struct _SPU_VOICE
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{
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union
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{
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struct {
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u16 Vol : 14;
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u16 Inverted : 1;
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u16 Sweep0 : 1;
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} vol;
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struct {
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u16 Vol : 7;
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u16 res1 : 5;
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u16 Inverted : 1;
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u16 Decrease : 1; // if 0, increase
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u16 ExpSlope : 1; // if 0, linear slope
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u16 Sweep1 : 1; // always one
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} sweep;
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u16 word;
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} left, right;
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u16 pitch : 14; // 1000 - no pitch, 2000 - pitch + 1, etc
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u16 res0 : 2;
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u16 SustainLvl : 4;
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u16 DecayRate : 4;
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u16 AttackRate : 7;
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u16 AttackExp : 1; // if 0, linear
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u16 ReleaseRate : 5;
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u16 ReleaseExp : 1; // if 0, linear
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u16 SustainRate : 7;
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u16 res1 : 1;
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u16 SustainDec : 1; // if 0, inc
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u16 SustainExp : 1; // if 0, linear
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u16 AdsrVol;
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u16 Address; // add / 8
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u16 RepeatAddr; // gets reset when sample starts
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};
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// ADSR INFOS PER CHANNEL
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struct ADSRInfoEx
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{
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s32 State;
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s32 AttackModeExp;
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s32 AttackRate;
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s32 DecayRate;
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s32 SustainLevel;
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s32 SustainModeExp;
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s32 SustainIncrease;
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s32 SustainRate;
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s32 ReleaseModeExp;
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s32 ReleaseRate;
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s32 EnvelopeVol;
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s32 lVolume;
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};
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#define NSSIZE 48 // ~ 1 ms of data
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#define NSFRAMES 16 // gather at least NSFRAMES of NSSIZE before submitting
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#define NSPACKETS 4
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#define SPU_VOICE_STATE_SIZE (sizeof(VOICE_PROCESSED)-4*sizeof(void*))
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struct VOICE_PROCESSED
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{
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VOICE_PROCESSED()
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{
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memset(this, 0, sizeof(VOICE_PROCESSED));
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}
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~VOICE_PROCESSED()
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{
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}
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void SetVolume(int right);
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void StartSound();
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void VoiceChangeFrequency();
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void FModChangeFrequency(int ns);
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void Stop();
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SPU_CONTROL_* GetCtrl();
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// start save state
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s32 iSBPos; // mixing stuff
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s32 spos;
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s32 sinc;
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s32 iActFreq; // current psx pitch
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s32 iUsedFreq; // current pc pitch
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s32 iStartAddr, iLoopAddr, iNextAddr;
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ADSRInfoEx ADSRX; // next ADSR settings (will be moved to active on sample start)
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bool bIgnoreLoop, bNew, bNoise, bReverb, bOn, bStop, bVolChanged;
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s32 memoffset; // if first core, 0, if second, 0x400
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// end save state
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///////////////////
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// Sound Buffers //
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///////////////////
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u8* pStart; // start and end addresses
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u8* pLoop, *pCurr;
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_SPU_VOICE* pvoice;
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};
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struct ADMA
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{
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u16 * MemAddr;
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s32 IntPointer;
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s32 Index;
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s32 AmountLeft;
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s32 Enabled;
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};
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#endif /* __SPU2_H__ */
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